JPH0863407A - Information transfer controller - Google Patents

Abstract

PURPOSE: To prevent the throughput of an information transfer processor from decreasing by performing abnormal end processing by a status bus even at the time of transmission between a status and the status bus when abnormality of the status is recognized. CONSTITUTION: Function units 14 and 15 after receiving data on a data bus 10 completely sends the status to the transmission source within a certain time simultaneously with status validity to reply the reception state of the data, and data transfer between the replying source and transmission source is performed. A signal line 16 for reporting an abnormal state is provided between the function units 14 and 15, which are provided with informing and recognizing means 17 which report the abnormal state between the function units 14 and 15 through the signal line 16 and recognize it when the status validity or status becomes abnormal. When the informing and recognizing means 17 report the abnormal state through the signal line 16, function units of a reception source perform abnormal end processing even when the status and status validity reporting the normal reception of the data are sent.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a device composed of a plurality of functional units, and more particularly to a status valid indicating that the status of the data bus and the status bus and the status bus between the functional units are valid. The present invention relates to an information transfer control device capable of notifying an abnormality in the status or an abnormality in the status valid when they are coupled by a signal line for transferring the information.

In an information transfer control device composed of a plurality of functional units and mutually transferring data between the functional units, a functional unit for transmitting data is a master and a functional unit for receiving the data is a slave. , When the master sends data to the slave via the data bus, the slave sends a status to the master via the status bus to notify whether this data has been normally received, and Status indicating validity
The valid is simultaneously transmitted to the master via the dedicated signal line.

If the status valid is not received by the master, the master cannot receive the status, so normal termination processing becomes impossible,
Even if an error occurs in the status, normal termination processing becomes impossible.

Therefore, the master performs abnormal termination processing,
Since a retry operation such as data retransmission is performed, the data bus and status bus are occupied for a long time, and the processing efficiency of the information transfer control device is reduced. Therefore, countermeasures are required.

[0005]

2. Description of the Related Art FIG. 13 is a block diagram illustrating an example of a conventional technique. The disk controller 2 has a plurality of functional units,
That is, it is composed of the channel adapters 5 and 6, the device adapters 7 and 8, and the resource manager 9, and controls the data transfer between the channel 1 and the disk device 3 or 4.

When performing data transfer with the disk device 3, the channel 1 instructs the channel adapter 5 to write or read data by designating the machine number, cylinder number, head number and sector number of the disk device 3. .

When the channel adapter 5 obtains the right to use the data bus 10 from the resource manager 9, it connects with the device adapter 7 and instructs the device adapter 7 to specify the specified head of the disk device 3 for writing data. When it is positioned in the designated sector of the selected cylinder, the data sent by the channel 1 is transferred to the device adapter 7 via the data bus 10 and written in the disk device 3.

When the data reading is instructed, the channel adapter 5 instructs the device adapter 7 to position the head of the disk device 3 at the designated sector of the designated cylinder and read the head. The data to be output is received via the data bus 10 and transferred to the channel 1.

FIG. 14 is a time chart for explaining the operation of FIG. For example, when writing data to the disk device 3 from the channel adapter 5 through the device adapter 7, the channel adapter 5 synchronizes with the clock and stores, for example, 3 blocks of data in the buffer memory as shown in the master transmission unit of FIG. While writing one block at a time,
The data is sequentially sent to the data bus 10.

Therefore, as shown in the data bus of FIG. 14, three blocks of data are sequentially sent to the data bus 10 one block at a time, and the buffer memory of the device adapter 7 receives the slave data receiving section of FIG. Sequentially 1
Stored block by block.

At this time, as shown in the slave reception data check in FIG. 14, the error check circuit of the device adapter 7 checks the received data block by block to detect whether or not there is an error.

When this error check is completed, the device adapter 7 creates the result of this error check as a status of a plurality of bits as shown in the slave status transmission section of FIG.

Then, as shown in the status valid of FIG. 14, the status valid is sent to the signal line 12, and at the same time, the status is sent to the channel adapter 5 via the status bus 11 as shown in the status bus of FIG. Send out.

Since the status valid is sent to the signal line 12, the channel adapter 5 receives the status bus 11 as shown in the master status receiving section of FIG.
When the status of is received and this status notifies the normal reception of data, the processing at the normal time is performed.

FIG. 15 is a flow chart for explaining the operation of FIG. Step the master channel adapter 5
Data transmission is started in (1), and the status reception wait state is entered in step (2).

The slave device adapter 7 is stepped
The data reception is recognized in (7), and the received data is checked in step (8). When the reception data normality is recognized in step (9), status transmission is started in step (10), and normal processing is performed in step (11).

The master channel adapter 5 is a step
The status reception is recognized in (3), and the reception status is checked in step (4). That is, it is checked whether the result of the parity check is normal or whether the status is undefined.

Then, when the normal reception status is recognized in step (5), the normal processing is performed in step (6).
The operations of the channel adapter 6 and the device adapter 8 when the channel 1 transfers data to and from the disk device 4 are the same as those described above, and detailed description thereof will be omitted.

[0019]

FIG. 16, FIG. 17, and FIG.
8 is a flow chart for explaining the problems of the conventional technique.

FIG. 16 shows the operation when the status valid is not received by the master. That is, the master starts data transmission in step (1) and enters the status reception waiting state in step (2).

When the slave recognizes data reception in step (5), it checks the received data in step (6).
Then, when the normal reception data is recognized in step (7),
Initiate status transmission in step (8) and then in step (9)
To perform normal processing.

However, if the master does not receive the status valid indicating the validity of the status, the status sent to the status bus 11 cannot be taken in.

Therefore, the master cannot recognize the status reception at step (3), and the process at the time of abnormality is performed at step (4). FIG. 17 shows the operation when a parity error occurs in the status. That is, the master is step (1)
The data transmission is started with and the status reception waiting state is entered in step (2).

When the slave recognizes data reception in step (7), it checks the received data in step (8).
Then, when it is recognized that the received data is normal in step (9),
Start sending status in step (10), then step (11)
To perform normal processing.

The master recognizes the status reception in step (3) and checks the reception status in step (4). That is, it is checked whether the result of the parity check is normal or whether the status is undefined.

Then, in step (5), the reception status
If a parity error is recognized, the abnormal process is performed in step (6). FIG. 18 shows the operation when a code error occurs in the status and an undefined status is reported.

The master starts data transmission in step (1) and enters a status reception waiting state in step (2).
When the slave recognizes the data reception in step (7), it checks the received data in step (8). Then, when it is recognized that the received data is normal in step (9), step (10)
The status transmission is started with and the normal processing is performed in step (11).

The master recognizes the status reception in step (3) and checks the reception status in step (4). That is, it is checked whether the result of the parity check is normal or whether the status is undefined.

Then, when the reception status undefined code is recognized in step (5), the process at the time of abnormality is performed in step (6). As described above, when the status valid is not received by the master due to a failure of the driver or the receiver or the signal line 12, when the parity error occurs in the status sent by the slave, and when the status error sent by the slave has a code error. When an undefined status occurs and is received by the master, the master performs the processing at the time of abnormality, the slave normally receives the data, and the normal status is sent together with the normal status valid. The normal processing is performed without recognizing any abnormality.

Therefore, the master executes a retry defined by the specifications of the information transfer control device, such as resending data, so that the data bus 10 and the status bus 11 are occupied and the processing of the information transfer processing device is performed. There is a problem of reduced efficiency.

[0031]

FIG. 1 is a block diagram for explaining the principle of the present invention. The information transfer control device 13 includes a data bus 10 for transferring data, and the data bus 10
The data on the data bus 10 are coupled to each other by a status bus 11 for transferring a status notifying the data reception state and a signal line 12 for transferring a status valid indicating the validity of the status on the status bus 11. A plurality of functions for transmitting the status to the transmission source at the same time as the status valid within a fixed time after reception of the data, responding the reception status of the data, and transferring the data between the transmission source and the reception source. It is composed of units 14 and 15.

And, between each functional unit 14 and 15,
A new signal line 16 for notifying an abnormal state is provided, and each of the functional units 14 and 15 receives a status error when the status valid is not received within a predetermined time, or a parity error occurs in the status, or is undefined. When a code error indicating the status is generated, the functional unit serving as the sender notifies the functional unit serving as the receiver of the abnormal state via the new signal line 16 and recognizes the notification of the abnormal state. A notification and recognition means 17 is provided, and when this notification and recognition means 17 notifies an abnormal state via the new signal line 16, the functional unit of the receiving source reports the normal reception of data. Even if the status valid is sent, abnormal termination processing is performed.

When a parity error occurs in the status or a code error indicating an undefined status occurs, the signal line 12 for transferring the status valid and the new signal line 16 are used. With respect to the functional unit that is the sender, the functional unit that is the sender,
This is a notification that distinguishes between a parity error and a code error.

[0034]

With the above-described configuration, the content of the operation end processing does not differ between the functional unit of the transmission source and the functional unit of the reception source, and the processing ends abnormally.
0 and the status bus 11 are not occupied for a long time. Therefore, it is possible to prevent the processing efficiency of the information transfer control device from decreasing.

Further, it is notified by distinguishing between a parity error and a code error that when a parity error occurs in the status, it is a fault of the status bus 11, and when a code error indicating an undefined status occurs. ,
This is because it is not a failure of the status bus, and the effect of being relieved by retransmitting the status can be obtained.

[0036]

FIG. 2 is a block diagram of a circuit showing an embodiment of the present invention. In this embodiment, data transfer control between the channel 1 and the disk device 3 is executed by a plurality of functional units, that is, the channel adapter 18 and the device adapter 19.

The processor 22 of the channel adapter 18 operates by reading the program stored in the control memory 23, and receives the channel command word sent together with the start I / O command from the channel 1 through the interface circuit 20, Data transfer to / from the channel 1 is performed, and the shared bus control circuit 21 is controlled to control the data bus 10
Data is transferred to and from the device adapter 19 via the.

The processor 2 of the device adapter 19
6 operates by reading the program stored in the control memory 27, sends a command to the disk device 3 via the interface circuit 25, and designates the head of the disk device 3 based on the address given from the channel adapter 18. The data bus 1 is located at the address
Data is transferred to and from the channel adapter 18 via 0.

At this time, as described with reference to FIG. 13, the functional unit that has become a slave is a function that sends a status to the status bus 11 and at the same time sends a status valid to the signal line 12 to make the data reception state the master. It is reported in units.

The signal line 16 is from the master to the slave.
This is added to notify that the status valid cannot be detected.When the status valid is transferred normally and the master detects a parity error or code error in the status, the master becomes the slave. On the other hand, it is a status error, and further, this status error is combined with the signal line 12 to indicate whether it is a parity error or a code error, and is used to distinguish and notify by using a 2-bit signal.

FIG. 3 is a time chart for explaining the operation at the time of status valid error. For example, the channel adapter 18 is the master and the device adapter 19
Is a slave, the processor 22 receives the data to be transmitted from the channel 1 through the interface circuit 20, controls the shared bus control circuit 21 and stores it in a buffer memory (not shown) in the shared bus control circuit 21 shown in FIG. As shown in the master data transmission unit, three blocks are sequentially written.

Under the control of the processor 22, the shared bus control circuit 21 sequentially sends this data to the data bus 10 in three blocks with a delay of one clock as shown in the data bus of FIG.

The shared bus control circuit 24 controls the data sent to the data bus 10 under the control of the processor 26.
3 blocks are sequentially stored in the internal buffer memory, as shown in the slave data receiving section.

At this time, the error detection circuit in the shared bus control circuit 24 detects the presence / absence of an error for each data block as shown in the slave reception data check in FIG.
The shared bus control circuit 24 creates this error check result as a status, as shown in the slave status transmission section of FIG. 3, and sends it to the status bus 11 as shown in the status bus of FIG. The status valid is sent to the signal line 12 as shown by the dotted line of the valid.

Faulty signal line 12 or shared bus control circuit 2
The shared bus control circuit 21 cannot detect this status valid if the driver of No. 4 has a fault or the receiver of the shared bus control circuit 21 has a fault.

Therefore, as shown in the master status receiving section of FIG. 3, the shared bus control circuit 21 cannot receive the status. However, this status valid is sent three clock cycles after the master has finished sending data to the data bus 10.

Therefore, when the status valid is not detected after these three clock cycles, the processor 22 determines that the status is a valid error, controls the shared bus control circuit 21, and indicates the master status error notification of FIG. Thus, the error signal is sent to the signal line 16.

Therefore, the processor 26 recognizes via the shared bus control circuit 24 that the status has not been normally received by the master, as shown in the slave status error recognition in FIG.

FIG. 4 is a flow chart for explaining the operation at the time of status valid error. The processor 22 of the channel adapter 18, which is the master, starts data transmission in step (1) and enters a status reception waiting state in step (2).

The processor 26 of the slave device adapter 19 recognizes the data reception in step (6) and checks the received data in step (7). Then, when the normal reception data is recognized in step (8), step (9)
The status transmission is started with and the status error notification is monitored in step (10).

If the status reception is not recognized in step (3), the processor 22 of the channel adapter 18, which is the master, starts the transmission of the status error via the signal line 16 in step (4), and the error occurs in step (5). Process time.

The processor 26 of the slave device adapter 19 recognizes the status error in step (11) in response to the status error notification from the master, and carries out the abnormal process in step (12).

5 and 6 are time charts for explaining the operation at the time of status / parity error. FIG. 5 shows the case where the master notifies the slave of the status error, and FIG. 6 shows the case where the content of the status error notifies the parity error.

In FIG. 5, the channel adapter 1 of FIG.
Assuming that 8 is a master and the device adapter 19 is a slave, the processor 22 uses the interface circuit 2
The data to be transmitted from channel 1 via 0 is received, the shared bus control circuit 21 is controlled, and the buffer memory in the shared bus control circuit 21 (not shown) sequentially receives, for example, 3 blocks as shown in the master data transmission unit of FIG. Write.

Under the control of the processor 22, the shared bus control circuit 21 sequentially sends this data to the data bus 10 for three blocks with a delay of one clock as shown in the data bus of FIG.

The shared bus control circuit 24 controls the data sent to the data bus 10 under the control of the processor 26.
3 blocks are sequentially stored in the internal buffer memory, as shown in the slave data receiving section.

At this time, the error detection circuit in the shared bus control circuit 24 detects the presence or absence of an error for each data block as shown in the slave reception data check of FIG.
The shared bus control circuit 24 creates this error check result as a status, as shown in the slave status transmission section of FIG. 5, and sends it to the status bus 11 as shown in the status bus of FIG. As shown by the valid, the status valid is transmitted to the signal line 12.

The shared bus control circuit 21 performs a parity check upon receiving the status by the status valid reception, as shown in the master status receiving section of FIG. As a result of this parity check, when a parity error is detected as shown in the master status parity error of FIG. 5, the processor 22 controls the shared bus control circuit 21 to send the signal to the shared bus control circuit 24 via the signal line 16. As shown in the master status error notification of FIG. 5, a status error is sent out.

Therefore, the processor 26 recognizes through the shared bus control circuit 24 that an error has occurred in the status, as shown in the slave status error recognition in FIG.

In FIG. 6, the channel adapter 1 of FIG.
Assuming that 8 is a master and the device adapter 19 is a slave, the processor 22 uses the interface circuit 2
The data sent from the channel 1 via 0 is received, the shared bus control circuit 21 is controlled, and the buffer memory in the shared bus control circuit 21 (not shown) sequentially receives, for example, 3 blocks as shown in the master data transmission unit of FIG. Write.

Under the control of the processor 22, the shared bus control circuit 21 sequentially sends this data to the data bus 10 for three blocks with a delay of one clock as shown in the data bus of FIG.

The shared bus control circuit 24 controls the data sent to the data bus 10 under the control of the processor 26.
3 blocks are sequentially stored in the internal buffer memory, as shown in the slave data receiving section.

At this time, the error detection circuit in the shared bus control circuit 24 detects the presence or absence of an error for each data block as shown in the slave reception data check of FIG.
The shared bus control circuit 24 creates this error check result as a status, as shown in the slave status transmission section of FIG. 6, and sends it to the status bus 11 as shown in the status bus of FIG. As shown in the valid, the status on the signal line 12
Send a valid.

Upon reception of the status valid, the shared bus control circuit 21 performs a parity check when the status is received as shown in the master status receiving section of FIG. As a result of this parity check, when a parity error is detected as shown in the master status parity error in FIG. 6, the processor 22 causes the shared bus control circuit 21
6 to control the signal line 12 to send the status valid as shown in the status valid of FIG. 6, and to the signal line 16 to send the status error as shown in the master status error notification of FIG. Let

Therefore, the processor 26 receives via the shared bus control circuit 24 a status error as shown in the slave status error recognition in FIG. 6 and a status valid as shown in the slave status valid recognition in FIG. Recognize that they were done at the same time.

Since the processor 26 receives the status error and the status valid at the same time, the processor 26 determines that a parity error has occurred in the status, and carries out the processing at the time of abnormality.

7 and 8 are flow charts for explaining the operation at the time of status / parity error. FIG. 7 shows the case where the master notifies the slave of the status error, and FIG. 8 shows the case where the content of the status error notifies the parity error.

In FIG. 7, the processor 22 of the channel adapter 18, which is the master, starts data transmission in step (1) and enters a status reception waiting state in step (2).

The processor 26 of the slave device adapter 19 recognizes the data reception in step (8) and checks the received data in step (9). Then, when the normal reception data is recognized in step (10), step (11)
The status transmission is started with and the status error notification is monitored in step (12).

When the processor 22 of the master channel adapter 18 recognizes the status reception in step (3), it checks the parity of the reception status in step (4) and recognizes the parity error in the reception status in step (5). To do.

Therefore, the processor 22 starts the transmission of the status error in the step (6), and performs the processing at the time of abnormality in the step (7). The processor 26 of the slave device adapter 19 recognizes the status error in step (13) by the status error notification from the master, and performs the process at the time of abnormality in step (14).

In FIG. 8, the processor 22 of the channel adapter 18, which is a master, starts data transmission in step (1) and enters a status reception waiting state in step (2).

The processor 26 of the slave device adapter 19 recognizes the data reception in step (8),
Check the received data in step (9). Then, when the normal reception data is recognized in step (10), step (1
Status transmission is started in 1), and status valid and status error notification are monitored in step (12).

When the processor 22 of the master channel adapter 18 recognizes the status reception in step (3), it checks the parity of the reception status in step (4) and recognizes the parity error in the reception status in step (5). To do.

Therefore, the processor 22 starts the simultaneous transmission of the status valid and the status error in the step (6), and performs the processing at the time of abnormality in the step (7). When the processor 26 of the slave device adapter 19 recognizes the simultaneous reception of the status valid and status error from the master in step (13), the two signals are received at the same time, so that the status parity is received in step (14). Recognize the error, and perform the process at the time of abnormality in step (15).

9 and 10 are time charts for explaining the operation at the time of status code error. FIG. 9 shows the case where the master notifies the slave of the status error, and FIG. 10 shows the case where the content of the status error notifies the code error.

In FIG. 9, only the master status parity error of FIG. 5 becomes a master status code error, and the operation is the same as that of FIG. 5, so detailed description will be omitted. FIG.
2, if the channel adapter 18 of FIG. 2 is the master and the device adapter 19 is the slave,
The processor 22 receives the data to be transmitted from the channel 1 via the interface circuit 20, and the shared bus control circuit 21
Is controlled to sequentially write, for example, 3 blocks in the buffer memory in the shared bus control circuit 21 (not shown), as shown in the master data transmission section of FIG.

Under the control of the processor 22, the shared bus control circuit 21 sequentially sends this data to the data bus 10 for three blocks with a delay of one clock as shown in the data bus of FIG.

The shared bus control circuit 24 controls the data sent to the data bus 10 under the control of the processor 26.
As shown in the slave data receiving unit of 0, 3 blocks are sequentially stored in the internal buffer memory.

At this time, the error detection circuit in the shared bus control circuit 24 detects the presence or absence of an error for each data block as shown in the slave reception data check of FIG. The shared bus control circuit 24 creates this error check result as a status, as shown in the slave status transmission section of FIG. 10, and sends it to the status bus 11 as shown in the status bus of FIG. A status valid is sent to the signal line 12 as indicated by a valid position.

Upon reception of the status valid, the shared bus control circuit 21 checks whether or not the status is an undefined status when the status is received, as shown in the master status receiving section of FIG. As a result of this check, when a code error occurs and it is detected that the status is undefined, as shown in the master status code error in FIG. 10, the processor 22 controls the shared bus control circuit 21 and the signal line 12 On the other hand, the status valid is sent out as indicated by the status valid in FIG. 6, but the status error is not sent out to the signal line 16 as shown in the master status error notification in FIG.

Therefore, the processor 26 does not receive the status error via the shared bus control circuit 24 as shown in the slave status error recognition in FIG. 10, but receives only the status valid as shown in the slave status valid recognition in FIG. Recognize what was done.

Since only the status valid has been received, the processor 26 determines that a code error has occurred in the status, and carries out the processing at the time of abnormality. 11 and 12 are flow charts for explaining the operation when a status code error occurs.

FIG. 11 shows a case where the master notifies the slave of a status error, and FIG. 12 shows a case where the content of the status error is notified as a code error. 11 is different from FIG. 7 in that the operation of step (5) is the recognition of the reception parity error, but the recognition of the reception code error, and the other operations are the same, so the detailed description will be omitted.

In FIG. 12, the processor 22 of the channel adapter 18, which is the master, starts data transmission in step (1) and enters a status reception waiting state in step (2).

The processor 26 of the slave device adapter 19 recognizes the data reception in step (8),
Check the received data in step (9). Then, when the normal reception data is recognized in step (10), step (1
Status transmission is started in 1), and status valid and status error notification are monitored in step (12).

When the processor 22 of the channel adapter 18, which is the master, recognizes the status reception in step (3), it checks in step (4) whether the reception status is an undefined status, ) Recognizes a receive status code error and recognizes that the status is an undefined status.

Therefore, the processor 22 starts transmitting only the status valid in step (6), and
In step (7), handle the error. When the processor 26 of the slave device adapter 19 recognizes the reception of only the status valid from the master in step (13), only the status valid is received.
Recognize the status code error in (14), and
In step 5), handle the error.

[0089]

As described above, according to the present invention, since the status valid is not received, the contents of the operation end process are not different between the functional unit of the transmission source and the functional unit of the reception source, and both the abnormal termination process and the abnormal termination process are performed. Therefore, the data bus and the status bus are not occupied for a long time, and it is possible to prevent a decrease in the processing efficiency of the information transfer control device.

Further, since it is possible to distinguish whether the received status has a parity error or a code error, the functional unit of the receiving source retransmits the status to recover the error. It is possible to make a process decision such as

[Brief description of drawings]

FIG. 1 is a block diagram illustrating the principle of the present invention.

FIG. 2 is a block diagram of a circuit showing an embodiment of the present invention.

[Figure 3] Time chart explaining the operation at the time of status valid error

FIG. 4 is a flowchart explaining the operation at the time of status valid error.

FIG. 5 is a time chart explaining the operation at the time of status / parity error (No. 1)

FIG. 6 is a time chart explaining the operation at the time of status / parity error (No. 2)

FIG. 7 is a flowchart (part 1) explaining the operation at the time of status / parity error.

FIG. 8 is a flowchart (No. 2) explaining the operation at the time of status / parity error.

FIG. 9 is a time chart explaining the operation at the time of status code error (No. 1)

FIG. 10 is a time chart explaining the operation at the time of status code error (No. 2)

FIG. 11 is a flowchart (No. 1) explaining the operation at the time of status code error.

FIG. 12 is a flowchart (part 2) explaining the operation at the time of status code error.

FIG. 13 is a block diagram illustrating an example of conventional technology.

14 is a time chart explaining the operation of FIG.

FIG. 15 is a flowchart illustrating the operation of FIG.

FIG. 16 is a flowchart (part 1) explaining problems of the conventional technology.

FIG. 17 is a flowchart (part 2) explaining problems of the conventional technology.

FIG. 18 is a flowchart (part 3) explaining problems of the conventional technology.

[Explanation of symbols]

 1 channel 2 disk controller 3, 4 disk device 5, 6, 18 channel adapter 7, 8, 19 device adapter 9 resource manager 10 data bus 11 status bus 12, 16 signal line 13 information transfer controller 14, 15 functional unit 17 Notification and recognition means 20, 25 Interface circuit 21, 24 Shared bus control circuit 22, 26 Processor 23, 27 Control memory

Claims (2)

[Claims] 1. A data bus for transferring data, a status bus for transferring a status notifying a data reception state on the data bus, and a signal line for transferring a status valid indicating validity of the status on the status bus. After completion of receiving the data on the data bus, the status is transmitted to the transmission source at the same time as the status valid within a fixed time, and the reception state of the data is responded to and received by the transmission source. In the information transfer control device composed of a plurality of functional units for transferring data to and from the source, a new signal line for notifying an abnormal state is provided between the functional units, and each functional unit has the status -When a valid is not received within a predetermined time, or a parity error occurs in the above status, or a code indicating an undefined status. And a recognizing means for notifying an abnormal state from the functional unit that is the transmission source to the functional unit that is the reception source via the new signal line when a fault error occurs. When the notifying and recognizing means notifies an abnormal state via the new signal line, the functional unit of the receiving source transmits a status reporting normal reception of data and a status valid transmission. However, the information transfer control device is characterized by performing abnormal termination processing. 2. The information transfer control device, when a parity error occurs in the status or a code error indicating an undefined status occurs, a signal line for transferring the status valid and the new signal. 2. The information transfer control device according to claim 1, wherein the functional unit serving as the transmission source is distinguished from the functional unit serving as the receiving source by using a line to notify the functional unit as a parity error or a code error. .