JPH10334044A - Serial interface method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make the data communication reliably performable by recognizing a signal, which follows a response confirm signal, as data information when the response confirm signal is received and recognized. SOLUTION: When the R/W bit of received address signal (ADR) is '1', a reading instruction is recognized by the side of reception station. A data transmission part 11 on the side of reception station transmits a data signal (RDATA), to which data read to a response confirm (ACK) bit '10' are added, to the side of transmission station. When an address error or a bus error is found out, the address error bit is set to '1' and the RDATA is transmitted to the side of transmission station. A data reception part 4 on the side of transmission station receives the RDATA at the rising edge of CLK. When the ACK bit is detected from the received RDATA, an ACK recognizing part 5 reads the data of 34 bits after the ACL bit. These data are data requested to be read from the side of transmission station to the side of reception station.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a serial interface method used for data communication between an LSI, a board, and devices.

[0002]

2. Description of the Related Art As one of the conventional serial interface methods, a communication clock and a control signal transmitted from a transmitting station to a receiving station and a data signal transmitted bidirectionally between the transmitting station and the receiving station are used. Is transmitted via three signal lines (a three-wire interface method). In this method, the transmitting station sends address information to the receiving station,
The receiving station reads data from the specified address,
When transmitting the read data to the transmitting station, the receiving station must transmit the read data to the transmitting station a fixed time (for example, after 8 clocks) after receiving the address information. Also, when transmitting address information and data information from the transmitting station to the receiving station, and the receiving station writes the received data to the address specified by the address information transmitted from the transmitting station, the receiving station specifies The data is written to the specified address, and the write operation ends.
At this time, the receiving station does not notify the transmitting station of the end of the write operation. As described above, in the three-wire interface method, only the access from the transmitting station to the receiving station is defined. In other words, it is assumed that the receiving station does not actively access the transmitting station.

[0003]

As described above, in the conventional three-wire interface method, the receiving station must transmit data after a fixed time after receiving the address. If it is unknown or the time required to read data from the specified address (read access time) may be longer than the fixed time, data reliability cannot be ensured. There was a problem that it was not possible.

[0004] For this reason, it is desired to develop a serial interface method that can perform reliable data communication even when the data transmission delay time is unknown or the read access time may be longer than the fixed time. Was rare.

[0005]

SUMMARY OF THE INVENTION A serial interface method according to the present invention provides a serial interface for performing data communication between three transmitting lines between a transmitting station transmitting an instruction and a receiving station receiving an instruction. In the interface method, when reading data information on the receiving station side on the transmitting station side, transmitting information for executing a read command to the receiving station side; and receiving information from the transmitting station side on the receiving station side. Upon receipt, a response acknowledgment signal is generated, the read data is added immediately after the response acknowledgment signal, and the data is transmitted to the transmitting station. The transmitting station receives and acknowledges the response acknowledgment signal. Recognizing a signal following the confirmation signal as data information. In the present invention,
With the above steps, the receiving station does not need to transmit the data information read out after receiving the address information within a fixed time. That is, the transmission of the data information may be performed within an arbitrary time without being restricted by the fixed time.

[0006]

FIG. 1 is a block diagram of a communication circuit configuration to which a serial interface method according to an embodiment of the present invention is applied. In the figure, the transmitting station side includes the following 1 to 7. Reference numeral 1 denotes a synchronization signal transmitting unit that transmits a clock signal (CLK) that is a synchronization signal for data transmission.
CLK is always transmitted to the receiving station side. Reference numeral 3 denotes a data transmission unit, and reference numeral 4 denotes a data reception unit, which respectively transmits and receives data signals. Reference numeral 2 denotes a control signal transmitting unit that transmits a signal synchronized with the data transmitted from 3. Reference numeral 5 denotes an ACK recognizing unit that recognizes a response acknowledgment bit (ACK bit) added to the transmission data on the receiving station side. Reference numeral 6 denotes a data check unit for checking whether or not correct data having no error during transmission is obtained from the data received at 4. Reference numeral 7 denotes a transmitting station control unit that controls the entire transmitting station.

[0007] The receiving station includes the following 8 to 14: Reference numeral 8 denotes a synchronization signal receiving unit that receives a synchronization signal transmitted from the transmitting station. Reference numeral 9 denotes a control signal receiving unit that receives a control signal transmitted from the transmitting station. Reference numeral 10 denotes a data receiving unit that receives a data signal transmitted from the transmitting station. Reference numeral 11 denotes a data transmitting unit that transmits a data signal from the receiving station to the transmitting station. Reference numeral 14 denotes a receiving station-side control unit that controls the entire receiving station. Reference numeral 13 indicates whether the address and data received by the data receiving unit 10 are correct data without error during transmission, and whether a bus error has occurred when reading from an external circuit. An address / bus error check unit. 12
Is an ACK generation unit that generates an ACK bit. This A
The operation of the CK generation unit 12 will be described in detail together with the ACK recognition unit 5 after explaining the data format of FIG.

FIG. 2 is a diagram showing an example of a data format in the serial interface method according to the embodiment of FIG. In the figure, an address part (ADRS) is a first bit, a bit for determining a read or write command (R / W bit), a 31-bit address to be controlled, and a parity check bit (odd parity) for the 32 bits. , Even parity). The R / W bit is a bit that becomes “1” at the time of reading and “0” at the time of writing. The data section (DATA) includes an A error bit (1 bit) and a D error bit (1 bit), monitoring / control data (30 bits), and a parity check bit (1 bit each for odd parity and even parity). A
The error bit is set to "1" when a parity error of an address is detected at the receiving station side when a read command is issued and a bus error is detected at the time of data reading, and is set to "0" when not detected. This is a bit to notify. The D error bit is set to “1” when the transmitting station detects a parity error of data transmitted from the receiving station at the time of a read command, and is set to “0” when it is not detected. This is a bit to notify. The monitoring / control data is indicated by the address of the address part,
When the W bit is “1”, the data is transmitted from the receiving station to the transmitting station, and when the W bit is “0”, the data is transmitted from the transmitting station to the receiving station. The parity check bits are odd parity and even parity check bits for the 32 bits. The idle period (WAIT) is a period provided between ADRS and DATA during an 8-bit write operation.

FIG. 3 is a waveform diagram when a read command is issued from the transmitting station to the receiving station in the embodiment of FIG. Referring to the figure, the ACK generation unit 12 at the time of a read instruction
And the operation of the ACK recognition unit 5 will be described. In this case, the data transmission unit 3 on the transmitting station transmits a 34-bit address signal (ADRS) including the address to be read to the receiving station at the rising edge of CLK. At this time, A
The first R / W bit of the DRS is set to "1", and a 31-bit address is transmitted, followed by 2 parity bits. The data receiving unit 10 on the receiving station side receives the ADRS transmitted from the transmitting station side at the falling edge of CLK. Note that the synchronization signal transmitting unit 1 always transmits CLK to the receiving station side, and the synchronization signal receiving unit 8 receives CLK transmitted from the synchronization signal transmitting unit 1.

The address / bus error check unit 13 (A error check unit) on the receiving station side receives the R of the received ADRS.
An odd parity and an even parity check are performed on the / W bit and the address (total of 32 bits) to check whether there is a transmission error (whether an address error signal is generated). If no address error signal is found and it is determined that there is no transmission error, the following operation is continued.

The receiving station recognizes that this is a read command because the R / W bit of the received ADRS is "1". Then, after receiving the ADRS, the address specified by the falling edge of CLK is selected (chip select).
Then, the corresponding data is read. A error check unit 1
When data is read, a bus error signal (bus error occurs) or an ACK signal (no error occurs) is sampled at the rising edge of CLK. After the sampling ends, the chip select ends at the falling edge of CLK. When the ACK signal is sampled, A
The CK generation unit 12 generates an ACK bit “10”. The data transmission unit 11 on the receiving station side transmits a data signal (RDATA) to which the read data is added to the ACK bit “10” to the transmitting station side. If an address error or a bus error is found, the A error bit is set to "1" and R
The DATA is transmitted to the transmitting station. The A error bit only needs to detect an address error or a bus error, and it does not matter which error is detected.

The data receiving section 4 at the transmitting station receives RDATA at the rising edge of CLK. ACK recognition unit 5
When detecting the ACK bit for the received RDATA, reads 34-bit data after the ACK bit. This data is the data for which the transmitting station issues a read request to the receiving station. Thus, on the transmitting station side, AC
Since the bit sequence after the K bit can be recognized as the data requested to read from the transmitting station to the receiving station, the receiving station transmits the read data to the transmitting station within a fixed time after receiving the address. There is no need to perform data transmission within an arbitrary time. Further, the data check unit 6 of the transmitting station-side control unit 7 checks the read data to determine whether or not correct data having no error in the received data during transmission is obtained. The control signal transmitting unit 2 transmits a control signal (S
CN) to the receiving station side, and the data receiving unit 4 on the transmitting station side.
When the RDATA parity bit is received, the transmission of the signal ends (see SCN, ADRS, and RDATA in FIG. 3). The control signal receiving unit 9 receives the SCN transmitted from the control signal transmitting unit 2.

On the other hand, at the time of writing, A
A CK response is not required. However, a method utilizing the ACK bit is also possible. Here, a method of utilizing the ACK bit will be described. FIG. 4 is a waveform diagram when a write command is issued from the transmitting station to the receiving station in the embodiment of FIG. The operation of the write command ACK generation unit 12 and ACK recognition unit 5 will be described with reference to the drawings. In this case, the data transmitting unit 3 on the transmitting station side sets the ADRS indicating the writing position, the idle period (WAIT),
A 34-bit signal (WDATA) including ATA is transmitted to the receiving station at the rising edge of CLK. At this time, A
The head R / W bit of the DRS is set to “0”, and a 31-bit address is transmitted, followed by two parity bits. The data receiving unit 10 on the receiving station side receives the ADRS transmitted from the transmitting station side at the falling edge of CLK. Note that the synchronization signal transmitting unit 1 always transmits CLK to the receiving station side, and the synchronization signal receiving unit 8 receives CLK transmitted from the synchronization signal transmitting unit 1.

The address / bus error check section 13 (A error check section) on the receiving station side receives the R of the received ADRS.
/ W bit, address (total 32 bits) and DATA A
An odd parity and an even parity check are performed on the error, the D error, and the data (total of 32 bits) to check whether there is a transmission error (whether an address error signal or a data error signal is generated). If no address error signal or data error signal is found and it is determined that there is no transmission error, the following operation is continued.

Since the R / W bit of the received ADRS is "0", the receiving station recognizes that it is a write command. Then, at the falling edge of CLK after receiving the ADRS, the designated address is selected (chip selected) and the corresponding data is written. When writing data, the A error check unit 13 samples a bus error signal (a bus error occurs) or an ACK signal (an error does not occur) at the rising edge of the CLK.
After the sampling ends, the chip select ends at the falling edge of CLK. When the ACK signal is sampled, the ACK generation unit 12 generates an ACK bit “10”, and the data transmission unit 11 transmits the ACK bit to the transmitting station.

The data receiving section 4 on the transmitting station side receives the ACK bit at the rising edge of CLK, and
Detects the ACK bit. By detecting the ACK bit, the receiving station can recognize that the writing operation has been normally completed. In the conventional method, the receiving station does not notify the transmitting station of the end of the write operation, and thus the transmitting station cannot confirm whether the operation has been completed normally. You can check it. Address error, data error,
If any one of the bus errors is found, AC
It does not transmit K bits. The control signal transmitting unit 2 transmits a signal synchronized with the ADRS to the receiving station, and ends the transmission of the signal when the data receiving unit 4 of the transmitting station receives the ACK bit (SCN, WDATA, ACK
See).

Also, in the embodiment of FIG. 1, the transmitting station is provided with a timer for setting the waiting time of the ACK bit and a counter for setting the number of retransmissions.
If the ACK bit cannot be recognized within the waiting time, a process for accessing the receiving station again (read command or write command) is performed, and the above process is repeated a set number of times until the ACK bit can be received within the predetermined waiting time. Can have functions.

[0018]

As described above, according to the present invention, when the transmitting station issues a read command to the receiving station, the receiving station performs AC reading.
The data information read immediately after the K bit is added and transmitted to the transmitting station, and the transmitting station recognizes the bit sequence after the ACK bit as data information, so that the receiving station receives the address within a fixed time after receiving the address. It is not necessary to transmit the read data information to the user, and data can be transmitted within an arbitrary time.

[Brief description of the drawings]

FIG. 1 is a block diagram of a communication circuit configuration to which a serial interface method according to an embodiment of the present invention has been applied.

FIG. 2 is a diagram showing an example of a data format of a serial interface method according to the embodiment of FIG. 1;

FIG. 3 is a waveform diagram when a read command is issued from a transmitting station to a receiving station in the embodiment of FIG. 1;

FIG. 4 is a waveform chart when a write command is issued from the transmitting station to the receiving station in the embodiment of FIG. 1;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Synchronization signal transmission part 2 Control signal transmission part 3,11 Data transmission part 4,10 Data reception part 5 ACK recognition part 6 Data check part 7 Transmitting station side control part 8 Synchronization signal reception part 9 Control signal reception part 12 ACK generation part 13 Address bus error check unit 14 Receiving station side control unit

Claims (3)

[Claims] 1. A serial interface method for performing data communication between a transmitting station for transmitting an instruction and a receiving station for receiving the instruction via three signal lines. When reading the data information, a step of transmitting information for executing the read command to the receiving station side, and when the receiving station receives the information from the transmitting station side, generates a response confirmation signal, Adding the data information read immediately after the response acknowledgment signal and transmitting the data to the transmitting station; and receiving and recognizing the response acknowledgment signal on the transmitting station side. Recognizing the information as information. 2. A step of transmitting information and data information for executing a write command to a receiving station side when the transmitting station writes data information at a target position on the receiving station side; Receiving the information from the transmitting station and completing the data writing process, generating a response acknowledgment signal and transmitting the signal to the transmitting station; and receiving the response acknowledgment signal at the transmitting station. 2. The serial interface method according to claim 1, further comprising the step of: 3. If the transmitting station cannot receive a response confirmation signal within a predetermined waiting time, the transmitting station transmits the same information to the receiving station again to perform an access process,
3. The serial interface method according to claim 1, wherein the processing is repeated a set number of times until a response confirmation signal is received within a predetermined waiting time.