JP2825464B2 - Communication device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention provides two bus lines, enables the same data to be sent from each CPU to each data bus of the two bus lines, and compares the two data lines. And a communication device that disables transmission of data to the outside when a mismatch between the two data is detected.

[0002]

2. Description of the Related Art As a conventional communication device, for example, FIG.
And those shown in FIG. That is, each CP
The bus lines are extended from U1, respectively, and the same data can be sent from the respective CPUs 1 to the data buses 2 of both bus lines, and both the data are compared by the comparison circuit 3, and the failure of the CPU 1 or the software When the data becomes inconsistent due to runaway, the comparison circuit 3 detects this inconsistency and the coil of the relay 4 is not energized.
Are opened, the communication line is cut off, data transmission is controlled, and data cannot be transmitted from the transmission device 5 to the outside. By the above series of operations, the mismatched data is not transmitted, and the fail-safety and reliability of an external device such as a railway traffic signal are improved. Further, the transmitted data includes a check code for detecting an error in the data.

[0003]

However, in such a conventional communication device, as shown in FIGS. 3 and 4, the coil of the relay 4 is not energized after the comparison circuit 3 detects a mismatch, and the relay It takes at least several tens of milliseconds before the contact 4 is opened, the communication line is cut off, and data cannot be transmitted to the outside. Thus, for example, when data transmission speeds up, one of the two CPUs sends out mismatched data due to a failure or the like, and the comparison circuit 3 detects the data mismatch, and sends the data to the coil of the relay 4. When the power is turned off and the contacts are opened to control the transmission of mismatched data, the mismatched data is transmitted to the external device, that is, after the transmission to the external device is completed, fail-safe operation is performed. Etc. can not be secured,
The conventional communication device cannot be used as it is.

[0004] In order to ensure the fail-safe property, etc., data may be transmitted to an external device after the state of the relay 4 changes or not. If the data is transmitted after waiting for this, there is a problem that the speed of data transmission cannot be increased. The present invention has been made in view of such a conventional problem. An output bus line is formed by combining a data bus of one of two bus lines and a control bus of the other bus line. Configure, for example, one C
With the wrong bus control information sent from the CPU when the PU breaks down, the data and address information sent from the other CPU cannot be accurately written. For example, a data write error occurs and an incorrect When data is received by an external device, the external device checks for a data error, and the external device does not malfunction due to incorrect data. Thus, for example, data can be transmitted to an external device without waiting for the state of the relay to change or not, so that data transmission can be speeded up and fail-safety and reliability are improved. It is an object of the present invention to provide a communication device capable of performing such operations.

[0005]

The gist of the present invention for achieving the above object lies in the following matters. Two bus lines are provided, and the same data is sent to each data bus (21) of the two bus lines by each CPU.
(11), each of which can be transmitted, and when the two data are compared and a mismatch between the two data is detected,
In the communication device for disabling data transmission to the outside, data is transmitted to the outside by combining the data bus (21) of one of the two systems and the control bus (23) of the other system. A communication device comprising an output bus line (20) for performing the operation.

Next, the operation of the present invention will be described. An output bus line (20) is configured by combining a data bus (21) of one of the two bus lines (20) and a control bus (23) of the other bus line (20). Therefore, one of the two CPUs (1
1) If the CPU (11) sends erroneous bus control information due to the failure or the like, the erroneous bus control information includes data and address information sent from the other system CPU (11). For example, incorrect data cannot be correctly written to the transmitting device, and incorrect data is transmitted to an external device.

At this time, for example, it takes at least several tens of milliseconds until the state of the relay (16) changes after the comparison circuit (13) detects the data mismatch and the data cannot be transmitted to the outside. Since time is spent, transmission control of mismatched data is delayed, and erroneous data is transmitted from the transmission device (30) to an external device.
An external device can detect a data error by using a check code or the like of the received data, so that a malfunction does not occur due to the incorrect data. Also, the other CPU of the two systems
(11) sends out erroneous data or address information due to the failure or the like of the CPU (11), but if the CPU (11) can be accessed by the bus control information of one of the systems, the CPU (11) also outputs the relay (16). Incorrect data is transmitted from the transmitting device (30) to the external device due to the delay in the change of the state. However, the external device can detect a data error using a check code or the like of the received data. It will not malfunction. That is, for example, without waiting for the state of the relay (16) to change,
Even if the data is transmitted to the external device, the external device does not malfunction, so that the speed of data transmission can be increased.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. 1 and 2 show an embodiment of the present invention. As shown in FIG. 1, the motherboard of the computer 10 includes CPUs A-system and B-system.
And A-system and B-system buffer ICs 15 corresponding to each CPU 11, a comparison circuit 13 and a pendulum circuit 14
Are provided respectively. The memory 12 is connected to the CPU 11 via a memory bus. This CPU 11
Is a bus-synchronous type that generates and sends data in synchronization with a clock of a transmitting device 30 described later. here,
The data is transmitted in units of blocks and includes an information field, a check code for error detection, and the like.

An A-system bus line 20 extends from the A-system CPU 11, and a B-system bus line 20 extends from the B-system CPU 11. The data bus 21 of the A-system bus line 20 is extended via the A-system buffer IC 15 and constitutes the A-system bus line 20 as it is.
The address bus 22 of the A-system bus line is extended via the A-system buffer IC 15 and constitutes the A-system bus line as it is. The control bus 23 of the A-system bus line is connected to the B-system buffer IC 15,
The system bus line 20 is configured.

On the other hand, the data bus 21 of the B-system bus line 20 is extended via the B-system buffer IC 15 and constitutes the B-system bus line 20 as it is. The address bus 22 of the B-system bus line is connected to the B-system buffer IC 1.
5, and constitutes the B-system bus line 20 as it is. In addition, the control bus 23 of the B-system bus line is connected to the A-system buffer IC 15 to constitute the A-system bus line 20. That is, A
System data bus 21, A system address bus 22 and B
A system bus line 20 by system control bus 23
Is configured. Further, a B-system data bus 21, a B-system address bus 22, and an A-system control bus 23
Constitute the B-system bus line 20.

The comparison circuit 13 detects whether or not the data on the A-system data bus 21 and the data on the B-system data bus 21 match, and outputs a detection signal to the pendulum circuit 14.
Output to The comparison circuit 13 may be configured in the CPU 11. The coil of the relay 16 is connected to the output terminal of the pendulum circuit 14, and when a mismatch signal is input to the pendulum circuit 14, the coil of the relay 16 is de-energized,
Are configured to open. The contact of the relay 16 is provided in the transmission control unit 32 described later, and when the coil of the relay 16 is de-energized, the contact opens to cut off the communication line. An output bus line 20, which is an A-system bus line 20, is connected to a transmission device 30 for transmitting data to an external device. The transmission device 30 is connected to an external device via a transmission control unit 32 via a communication line. Examples of the external device include a railway, a traffic signal for a road, and a terminal device. The traffic light is provided with a receiving device for receiving data, a CPU for processing data, a control unit for driving and controlling the traffic light, and the like. The CPU in the traffic light associates the data with the check code, and when detecting that the data does not correspond to the check code, discards the data or the like and feeds back the discard information to the computer 10. It is configured. Error detection of data on transmission is performed by C
This is performed by a RC (Cyclic Redundancy Check), a checksum method, a parity check method, or the like. In the present embodiment, the output bus line 20 is configured by the A-system bus line 20, but may be configured by the B-system bus line 20.

Next, the operation of the present invention will be described with reference to FIG. In step 1, C of A system and B system
When data is sent from PU 11 to each data bus 21, both data are sent to comparison circuit 13, and in step 2, comparison circuit 13 compares both data.
If the two data match in step 3, a match signal is output to the pendulum circuit 14, the coil of the relay 16 is energized, the contact of the transmission control unit 32 is not opened, and the communication line is not interrupted. , The data can be transmitted from the transmission device 30 to the external device via the transmission control unit 32.

On the other hand, the data sent from the A-system CPU 11 is transmitted via the A-system data bus 21 to the A-system buffer I.
It is sent to C15 and sent to the A-system bus line 20 by the bus control signal of the B-system CPU11. In addition, C of A system
The address information sent from the PU 11 is sent to the A-system buffer IC 15 via the A-system address bus 22,
It is sent to the A-system bus line 20 by the system bus control signal. The data sent from the B-system CPU 11 is sent to the B-system buffer IC 15 via the B-system data bus 21, and is sent to the B-system bus line 20 by the bus control signal of the A-system CPU 11. The address information sent from the B-system CPU 11 is sent to the B-system buffer IC 15 via the B-system address bus 22, and is sent to the B-system bus line 20 by the A-system bus control signal.

In step 5, the transmitting device 30 is selected according to the address of the A-system CPU 11, and the A-system CPU 11 is selected.
The data of No. 11 is transmitted from the I / O port of the transmission device 30 to the external device via the transmission control unit 32 and the communication line. When the check code and the data are transmitted to the external device, the external device performs an error check on the data by the CRC or the like. An external device is drive-controlled.
In step 12, if there is a request for new data,
If a request for data is made to the computer and there is no request for new data, the data transmission to the external device ends in step 13.

On the other hand, if there is an error in the data during transmission in step 7, the data having the error is discarded in step 9, and if there is a data request in step 10, the data request is sent to the computer 10. Made to The computer 10 that has received the data request sends the data from each CPU 11 again. Step 10
If there is no data request at step 11, data transmission to the external device is terminated at step 11.

If the B-system CPU 11 sends erroneous bus control information due to a failure of the B-system CPU 11 or the like, the data and address information sent from the A-system CPU 11 are included in the B-system bus control information. Since it is not possible to write correctly in the transmitting device 30, for example, the transmitting device 30
The data that should be written is not written to the memory area.

At this time, even if the two data do not match in step 3, the required time (in step 4), the relay 16 is de-energized after the comparison circuit 13 detects the mismatch between the two data. The contacts open,
If the communication line is physically cut off and the time until data cannot be transmitted to an external device) has not elapsed, relay 1
6, the transmission control of the mismatched data is delayed, the contact of the relay 16 in the transmission control unit 32 is still closed, and the communication line is not physically cut off.
In, erroneous data is transmitted from the transmission device 30 to the external device via the transmission control unit 32. When incorrect data is transmitted to an external device, the external device
The received data is made to correspond to the check code, and it is detected that the data does not correspond to the check code. If there is a data error in step 7, the data is discarded in step 9, and The external devices do not malfunction. A signal indicating that data has been received even after a certain period
If it is not returned to 1 or if the data is discarded,
The discard information is fed back to the CPU 11, and data transmission is performed again.

The A-system CPU 11 sends erroneous data and address information due to the failure of the A-system CPU 11 and the B-system CPU 11 sends bus control information. In this case, according to the B-system bus control information,
The erroneous data or the like transmitted from the A-system CPU 11 when the transmission device 30 is specified is transmitted from the transmission device 30 to the transmission control unit 3.
Sent to 2. At this time, also in step 3,
The state change of the relay 16 is delayed, and in step 5,
Incorrect data is transmitted from the transmission device 30 to the external device via the transmission control unit 32.

When erroneous data and address information are transmitted to an external device, the external device does not receive erroneous data because the address cannot be specified, or the erroneous data and address information are transmitted to the external device. Even when the device receives the data, the external device associates the received data with the check code, detects that the data does not correspond to the check code, and in step 7, if there is an error such as data, In step 9, the data is discarded, and the external device does not malfunction due to the incorrect data. A signal indicating that data or the like has been received even after a certain time
If the data is not returned, or if the data is discarded,
The discard information is fed back to the CPU 11, and data transmission is performed again. On the other hand, in step 4, when the required time elapses, the coil of the relay 16 is de-energized, the contact of the relay 16 opens, the communication line is physically cut off, and no data is transmitted or the data is transmitted. Is also suspended.

[0020]

According to the communication apparatus of the present invention, an output bus line is formed by combining the data bus of one of the two systems and the control bus of the other system. In the case of erroneous bus control information sent from one CPU when one of the CPUs fails, the data and address information sent from the other CPU are not accurately written to the transmitting device, for example, so that an external device A data error can be detected, and when the other CPU fails, if the wrong data and address information are received by the external device, the external device can detect the wrong data. That is,
External devices do not malfunction with incorrect data. Thus, for example, data can be transmitted to an external device without waiting for the state of the relay to change or not, so that data transmission can be speeded up and fail-safety and reliability are improved. can do.

[Brief description of the drawings]

FIG. 1 is a conceptual diagram of a communication device according to an embodiment of the present invention.

FIG. 2 is a flowchart of a communication device according to an embodiment of the present invention.

FIG. 3 is a conceptual diagram of a communication device showing a conventional example.

FIG. 4 is an operation explanatory view of a communication device showing a conventional example.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 ... Computer 11 ... CPU 12 ... Memory 13 ... Comparison circuit 14 ... Pendulum circuit 15 ... Buffer IC 16 ... Relay 20 ... Bus line 21 ... Data bus 22 ... Address bus 23 ... Control bus 30 ... Transmission device 32 ... Transmission control part

Claims (1)

(57) [Claims] 1. Two bus lines are provided, the same data can be sent from each CPU to each data bus of the two bus lines, and both data are compared to compare the both data. In a communication device for disabling data transmission to the outside when a mismatch is detected, one data bus of the two bus lines and a control bus of the other bus line are combined to transmit data to the outside. A communication device comprising an output bus line for transmission.