JP3842764B2 - Bus interface circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a bus interface circuit for connecting an interlock transfer bus and a split transfer bus.
In an information processing system including a CPU including a personal computer, different transfer methods are often used for a local bus directly connected to the CPU and a system bus for connecting various peripheral devices to each other. .
Usually, the interlock transfer method is used for the local bus, the split transfer method is used for the system bus, and the local bus and the system bus are connected via an interface circuit.
[0002]
[Prior art]
FIG. 14 shows a configuration example of a general information processing system.
In FIG. 14, the local transfer bus connecting the CPU 401 and the memory 402 employs an interlock transfer method. When an access request is output by the CPU 401, the local bus until the transfer of data corresponding to the access request is completed. The bus is occupied by this access process.
[0003]
On the other hand, in the system bus adopting the split transfer method, after the order corresponding to the access request is output, the system bus is released while the processing on the input / output device 403 side is performed, and the data to be transferred When the system is ready, it acquires the system bus again and transfers data.
As described above, when the split transfer method is adopted as the transfer method in the system bus, other input / output devices 403 can use the system bus during the process in the input / output device 403 to be accessed, and the input / output in the input / output device 403 The time required for processing can be used effectively.
[0004]
By the way, as shown in FIG. 14, a bus interface circuit 404 is provided for connecting the interlock transfer local bus and the split transfer system bus so that the CPU 401 can access the input / output device 403. It is necessary to convert the request from the CPU 401 into an order according to the split bus transfer method and return the data from the input / output device 403 to the CPU 401 according to the interlock method.
[0005]
FIG. 15 shows a configuration example of a conventional bus interface circuit.
In FIG. 15, a local bus reception register 411 and a system bus transmission register 412 are connected to a local bus and a system bus via buffers, respectively. The local bus reception register 411 and the system bus transmission register 412 are a transmission buffer. 413 is connected.
[0006]
Further, the local bus reception management unit 414 and the system bus transmission management unit 415 shown in FIG. 15 control the operation of the transmission buffer 413 based on the information held in the transmission management buffer 416, thereby controlling the local bus. The request is received from the CPU 401 via this, and the request is converted into an order according to the split transfer method and sent to the system bus.
[0007]
The above-described local bus reception management unit 414 controls write addresses to the transmission buffer 413 and the transmission management buffer 416, and sequentially holds management information such as the address specified by the request from the CPU 401 and the type of request. And it is sufficient.
Further, the system bus transmission management unit 415 determines the split transfer method from the contents of the transmission buffer 413 and the transmission management buffer 416 according to the difference between the final write address by the local bus reception management unit 414 and the final read address by itself. An order according to the above may be created and sent via the system bus transmission register 412.
[0008]
On the other hand, in FIG. 15, the local bus transmission register 421 and the system bus reception register 422 are connected to the local bus and the system bus via buffers, respectively. The local bus transmission register 421 and the system bus reception register 422 are: Connection is made via a reception buffer 423.
Further, the local bus transmission management unit 424 and the system bus reception management unit 425 shown in FIG. 15 control the operation of the reception buffer 423 based on the information held in the reception management buffer 426, so that the system bus The output answer is received, converted into a response according to the interlock transfer method, and sent to the local bus.
[0009]
The system bus reception management unit 425 and the local bus transmission management unit 424 sequentially write the answer and management information received from the system bus to the reception buffer 423 in the same manner as the transmission side described above, and write address and read at that time The response transmission to the local bus may be managed by sequentially reading according to the difference from the address.
In addition, the local bus reception management unit 414 performs a protocol check and a parity check for each request received via the local bus. Depending on the result of these checks, the local bus reception management unit 414 performs a local check via the local bus transmission management unit 424. It is configured to send a retry request or error notification to the bus.
[0010]
The local bus reception management unit 414 is configured to start the timer 417 in response to the reception of a normal request, and the local bus transmission management unit 424 responds to a timeout notification from the timer 417. Is configured to notify the CPU 401 of a timer overflow for requests that are not returned.
Here, when the input / output device 403 is functioning normally, a sufficient time can be set in the timer 417 as a time required for returning a response from the input / output device 403 in response to a request from the CPU 401. That's fine.
[0011]
As a result, when any failure occurs on the input / output device 403 side, the response waiting state of the CPU 401 can be canceled in accordance with the above-described timeout notification, and the processing can be continued.
For detailed operations of the system bus transmission management unit and the system bus reception management unit, refer to Japanese Patent Laid-Open No. 3-67354 “Final data determination method in transfer data”.
[0012]
For a detailed description of the split transfer method, refer to Japanese Patent Application Laid-Open No. 3-253848 “Variable Bus Width Designation Method and Variable Bus Width Information Reception Method in Split Bus”.
By the way, in a system in which a plurality of CPUs are provided and information processing is duplicated or a system in which input / output devices are shared among a plurality of information processing systems, as shown in FIG. Further, there may be a case where a configuration connected via a bus expansion adapter and a bus controller is employed.
[0013]
In the information processing system as shown in FIG. 16, when the CPU 401a accesses the input / output device 403 connected to the extended system bus (hereinafter referred to as an expansion bus), the request sent by the CPU 401a to the local bus. Is converted into a corresponding order by the bus interface circuit 404a, transmitted to the system bus, and further transmitted to the target input / output device 403 via the bus expansion adapter 405 and the expansion bus.
[0014]
On the other hand, when the CPU 401b accesses the input / output device 403 described above, the request sent to the local bus by the CPU 401b is converted into a corresponding order by the bus interface circuit 404b and sent to the system bus. To the system bus on the CPU 401a side, and further transmitted to the input / output device 403 via the expansion bus adapter and the expansion bus.
[0015]
The answer sent to the expansion bus by the input / output device 403 is converted into a corresponding response by one of the bus interface circuits 404a and 404b, following the path through which the corresponding request is transmitted. To the CPUs 401a and 401b via the local bus.
[0016]
[Problems to be solved by the invention]
As described above, the conventional bus interface circuit manages the read operation from each of the transmission buffer 413 and the reception buffer 423 according to the difference between the write address and the read address, thereby enabling the order of requests and the order of answers. These correspondences were managed using only
[0017]
However, in an actual information processing system, a write answer may occur for a read operation due to a failure that has occurred in the system bus.
In such a case, the conventional bus interface circuit 404 may return indefinite data to the CPU 401 as read data from the input / output device 403, causing a failure of the information processing system. There is.
[0018]
In the conventional bus interface circuit, when an answer is simply returned within a predetermined time, it is received as a normal answer.
However, in the case of the extended information processing system as shown in FIG. 16, the route through which the request is transmitted and the route through which the answer is transmitted are complicated, so that the access is made according to the time-out notification from the timer 417. May be returned to the bus interface circuit 404 from the input / output device 403 side.
[0019]
Here, when the answer from the system bus side arrives after the timer overflow, the reception itself of the answer can be rejected by the command reject function provided in the local bus transmission management unit 424.
However, if an answer arrives immediately before the timer overflow, the answer is held in the reception buffer 423 of the bus interface circuit 404 as a normal answer, and then the access process is terminated without being read by the timer overflow. May end up.
[0020]
In such a case, as a response to the new request from the CPU 401, the answer returned immediately before the timer overflow described above is erroneously output to the local bus, thereby causing the information processing system to operate abnormally. There is a possibility that.
As shown in FIG. 14, in the case where the information processing system has a relatively simple configuration, in response to the timer overflow notification described above, both the local bus and the system bus are reset, so It was possible to clear the contents of the buffer and restore the information processing system.
[0021]
However, in the expanded system configuration as shown in FIG. 16, resetting the entire system due to an abnormality of some input / output devices leads to a serious service degradation. Can not be adopted.
Furthermore, as described above, the bus interface circuit 404 is merely an intermediary for exchanging information between the local bus and the system bus, and the CPU 401 has an interrupt request with a high priority. The normal access request processing is interrupted, and the interrupt request processing is preferentially performed.
[0022]
Therefore, as shown in FIG. 17, while the order 1 sent to the system bus in response to the access request 1 from the local bus side is being processed by the corresponding input / output device, it is sent from another input / output device. When the interrupt order is sent to the local bus as a corresponding interrupt request via the bus interface circuit, the CPU 401 interrupts the processing of the access request 1 and preferentially processes the interrupt request. Start.
[0023]
In this case, the CPU 401 returns a response to the interrupt request described above to the system bus side via the bus interface circuit, and then performs a retry process for the interrupted access request.
[0024]
At this time, since a parity error or the like is included in the retried access request 1, when an error response is returned from the bus interface circuit, the CPU 401 ends the processing of the access request 1 and starts the processing of another access request 2. There is a case.
At this time, when the answer 1 corresponding to the above-described order 1 is input to the bus interface circuit, the bus interface circuit sends the answer 1 held in the reception buffer 423 as a response corresponding to the access request 2 to the local bus. Will be output.
[0025]
In this way, when the occurrence of an interrupt order from the system bus side and the retry failure of an interrupted access request overlap, there is a possibility that the correspondence between the access request and the answer will be confused in the bus interface circuit. There was, and could not guarantee the normal operation after.
Therefore, there is a need for a technique that can flexibly cope with various abnormal answers caused by a failure in the system bus or an expanded system configuration, and guarantee the normal operation of the information processing system.
[0026]
An object of the present invention is to provide a bus interface circuit capable of performing appropriate management according to the characteristics of answers.
[0027]
[Means for Solving the Problems]
FIG. 1 shows a principle block diagram of the bus interface circuit of the present invention.
[0028]
The bus interface circuit connects the first bus of the interlock transfer method and the second bus of the split transfer method, and sends the access request received from the first bus as an order to the second bus side via the transmission buffer 101. In the bus interface circuit configured to send the answer returned from the second bus as a response to the first bus side via the reception buffer 102, the access request to the second bus side output to the first bus is transmitted. The matching means 111 for matching the characteristics with the characteristics of the answer held in the reception buffer 102 in response to the access request, and the answer held in the reception buffer 102 based on the matching result by the matching means 111 A first answer judging means 112 for judging whether or not the answer is an unnecessary answer having a feature different from the above-mentioned feature, and an unnecessary answer. Depending on the effect of the determination result, and a answer discarding means 113 for discarding the corresponding answer of the receive buffer 102.
[0029]
In this bus interface circuit, the first answer determination unit 112 performs a determination operation according to the collation result by the collation unit 111, and the answer discard unit 113 discards the answer held in the reception buffer 102 according to the determination result. By doing so, it is possible to detect a mismatch in characteristics between the access request received from the first bus side and the answer returned from the second bus side, and discard the unnecessary answer.
[0030]
  In this case, for example, when a write answer is erroneously returned from the second bus side in response to a read request, this write answer can be discarded as an unnecessary answer, and therefore undefined data is sent to the first bus side. It is possible to prevent an erroneous response such as outputting.
  The bus interface circuit of the present invention connects the first bus of the interlock transfer method and the second bus of the split transfer method, and the first busOutput toA bus interface circuit configured to send an access request as an order to the second bus side via the transmission buffer 101 and send an answer returned from the second bus as a response to the first bus side via the reception buffer 102 Access to the second bus sideAfter accepting access requestsWhen a predetermined time elapses, a timer 114 that outputs a time-out notification indicating that, and an unnecessary answer that has been invalidated on the first bus side in response to the time-out notification, the answer held in the reception buffer 102 has already become invalid. Second answer judging means 115 for judging whether or not the answer is present, and answer discard means 113 for discarding the corresponding answer in the reception buffer 102 in accordance with the judgment result that the answer is unnecessary. Features.
[0031]
In this bus interface circuit, the second answer determination unit 115 performs a determination operation in response to a time-out notification from the timer 114, and the answer discard unit 113 determines the answer held in the reception buffer 102 in accordance with the determination result. By discarding, it is possible to remove from the reception buffer 102 an answer that is no longer needed because the access processing on the first bus side is completed.
[0032]
As a result, regardless of the time required for reading from the reception buffer 102, the answer returned from the second bus side at the critical timing immediately before the timer overflow can be discarded as an unnecessary answer without being leaked. Operation can be guaranteed.
The bus interface circuit connects the first bus of the interlock transfer method and the second bus of the split transfer method, and the access request received from the first bus is ordered to the second bus side via the transmission buffer 101. In the bus interface circuit configured to send the answer returned from the second bus as a response to the first bus side via the reception buffer 102, the first error occurred after the start of the access operation to the second bus side. A mode setting means 116 for setting an answer discard waiting mode in response to an access error on the one bus side, and a new access request from the first bus to the second bus side during the period in which the answer discard waiting mode is set In response to the request acceptance control means 117 that returns a response to the response and the answer discard waiting mode, In response to the third answer determination means 118 for determining whether the received answer is an unnecessary answer that has already been invalidated on the first bus side, and in accordance with the determination result that the answer is an unnecessary answer. Answer discarding means 113 for discarding the corresponding answer, and mode canceling means 119 for canceling the answer discard waiting mode upon completion of the answer discarding operation by the answer discarding means 113.
[0033]
In this bus interface circuit, the answer setting waiting mode is set and released by the mode setting means 116 and the mode releasing means 119, and the third answer determining means 118 makes a determination according to whether or not the answer discard waiting mode is set. In response to this determination result, the answer discarding unit 113 discards the answer held in the reception buffer 102, so that the answer invalidated on the first bus side due to the error is discarded as an unnecessary answer. can do.
[0034]
Further, depending on whether the answer discard waiting mode is set, the request acceptance control means 117 replies to the access request with a retry, thereby rejecting acceptance of a new access request until the above-mentioned unnecessary answer is discarded. And the access request can be prevented from being confused with each other.
Further, the bus interface circuit outputs a timeout notification indicating that a predetermined time has elapsed from the start of the access operation to the second bus side, and outputs to the reception buffer 102 in response to the timeout notification. And a second answer determination unit 115 that determines whether the held answer is an unnecessary answer that has already been invalidated on the first bus side.
[0035]
This bus interface circuit operates in response to the determination result by the third answer determination means 118 or the determination result by the second answer determination means 115, so that the answer discard means 113 operates, even if the answer to be discarded does not arrive. In response to the overflow, the answer discard waiting mode can be canceled and the acceptance of a new access request can be resumed.
[0036]
In addition, the bus interface circuit includes a matching unit 111 that checks the characteristics of the access request to the second bus output to the first bus and the characteristics of the answer held in the reception buffer 102 in response to the access request. The first answer determination means 112 for determining whether the answer held in the reception buffer 102 is an unnecessary answer having a characteristic different from the characteristics of the access request based on the result of the comparison by the matching means 111. ing.
[0037]
Since this bus interface circuit can reliably prevent the correspondence between the answer and the access request from being confused by the operation of the request reception control means 117, the collating means 111 makes a part of the feature information indicating the characteristics of the access request. And a part of the feature information indicating the answer feature can be detected reliably, so that the amount of hardware required to configure the matching means 111 is greatly reduced. can do.
[0038]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
FIG. 2 shows a bus interface circuit related to the present invention.
The bus interface circuit shown in FIG. 2 has a verification circuit 211 and an answer discard processing unit 212 added to the bus interface circuit shown in FIG. Answer characteristics received from the bus are collated, and according to the collation result, the answer discard processing unit 212 controls the local bus transmission management unit 424 and the system bus reception management unit 425 to be held in the transmission buffer 423. The answer is discarded.
[0039]
This collation circuit 211 corresponds to the above-mentioned collation means 111, and requests management information such as request type and block access as well as the request destination address is requested via the local bus reception register 411. The answer management information similar to the request management information described above may be received together with the answer source address via the reception management buffer 426, and the information may be collated with each other.
[0040]
The collation result by the collation circuit 211 is input to the local bus transmission management unit 424 via the OR gate 201 together with the error notification from the local bus reception management unit 414.
FIG. 3 shows a detailed configuration of the verification circuit 211.
In the verification circuit 211 shown in FIG. 3, the address verification unit 213 is configured to verify at least a part of the requested address and at least a part of the answer source address, and the management information verification unit 214 includes: The request management information and the answer management information are collated.
[0041]
The collation result by the address collation unit 213 and the collation result by the management information collation unit 214 are input to the OR gate 201 as an output of the collation circuit 211 via the OR gate 215.
Note that the address matching unit 213 and the management information matching unit 214 may be configured to output a logic “0” when the two input data match and output a logic “1” when they do not match.
[0042]
When the request management information corresponding to the read request and the answer management information corresponding to the write answer are input to the verification circuit 211, the output of the management information verification unit 214 becomes logic “1”. , A logic “1” indicating a mismatch is output.
In this way, the mismatch between the characteristics of the request and the answer is detected, and the detection result is notified to the local bus transmission management unit 424 via the OR gate 201, so that the answer error due to the failure occurring on the system bus side is detected. Can be notified to the CPU 401 as an error similar to the protocol error, as shown in FIG.
[0043]
In response to an error notification input via the OR gate 201, the local bus transmission management unit 424 sends a data transfer completion and error indication to the local bus via the local bus transmission register 421, and notifies the CPU 401 of the occurrence of the error. do it.
Also, in response to the collation result indicating that the request and answer characteristics do not match, for example, the answer discard processing unit 212 instructs the local bus transmission management unit 424 to stop reading from the reception buffer 423 and sets the read address. Just increment it.
[0044]
As described above, the collation circuit 211 obtains a collation result indicating whether or not a feature mismatch is detected, and the answer discard processing unit 212 operates according to the collation result. The functions of the 1 answer determination unit 112 and the answer discard unit 113 can be realized, and an answer having a feature that does not match the requested feature can be discarded as an unnecessary answer.
[0045]
As a result, an erroneous answer as described above can be discarded as an unnecessary answer instead of being read out from the reception buffer 423 and used for response processing, and the CPU 401 can respond to the error notification described above with an appropriate error. By performing the processing, for example, when a write answer is erroneously returned in response to a read request, it is possible to prevent the CPU 401 from fetching the erroneous answer.
[0046]
In this way, it is possible to flexibly cope with an abnormal answer generated due to a failure in the system bus or the like, to prevent a subsequent malfunction of the information processing system, and to improve the reliability of the bus interface circuit.
Next, a method for dealing with an answer that arrives after a timer overflow will be described.
[0047]
  FIG. 5 shows an embodiment of the bus interface circuit of the present invention.
  The bus interface circuit shown in FIG. 5 adds an answer control unit 221 to the bus interface circuit shown in FIG. 15, and the answer control unit 221 receives a signal from the local bus reception management unit 414.Access request acceptance notification ( To be described later )The local bus transmission management unit 424 controls the operation of the local bus transmission management unit 424 in response to a local bus access error notification from the local bus transmission management unit 424.
[0048]
  Here, the local bus reception management unit 414 performs the same parity check and protocol check as the conventional one, and when it is determined that the access is appropriate,Access request acceptance notification indicating that an access request to the system bus has been acceptedThe logic “1” is output.
  In addition, the timer 417 starts the timing operation in response to the system bus access start notification described above, and outputs a time-out notification indicating that a predetermined time has elapsed, thereby realizing the function of the timer 114 described above. It has become.
[0049]
The local bus transmission management unit 424 outputs logic “1” as a local bus access error notification when receiving at least one of the error notification from the local bus reception management unit 414 and the timeout notification from the timer 417. It has a configuration.
In this case, as shown in FIG. 6, an answer control unit 221 is configured by including a notification creation unit 224 and an answer discard processing unit 225 including an OR gate 222 and a JK flip-flop 223, and this notification creation unit 224. The answer discard processing unit 225 may be configured to control the local bus transmission management unit 424 in response to the answer waiting notification obtained in the above.
[0050]
  In FIG. 6, the notification creation unit 224Access request acceptance notificationIn response, the J-K flip-flop 223 is set and reset in response to a local bus access error notification or an answer reception notification, so that the local bus side is waiting for an answer from the system bus, that is, has reached An answer waiting notification is generated to indicate whether the answer is valid.
[0051]
Here, the notification creation unit 224 may receive a notification that a new answer has been written from the reception management buffer 426 and input it to the JK flip-flop 223 via the OR gate 222 as an answer reception notification.
Also, the answer discard processing unit 225 immediately increments the read address when the answer waiting notification becomes logic “0” in response to the timeout notification from the timer 417, indicating that the answer waiting has been released. The answer may be discarded.
[0052]
In this way, the notification creation unit 224 creates an answer waiting notification that changes in response to the start of system bus access and the occurrence of a timer overflow, and the answer discard processing unit 225 operates in response thereto, thereby The functions of the second answer determination unit 115 and the answer discard unit 113 can be realized, and the answer that has already been invalidated on the local bus side can be discarded.
[0053]
As a result, as shown in FIG. 4B, even when an answer is returned at a critical timing immediately before the timer overflow, the answer can be reliably discarded regardless of a delay in the bus interface circuit. .
As a result, only the answer returned at a timing that can be processed by the CPU 401 is sent as a response to the local bus, and the answer to the access request whose processing in the CPU 401 is terminated can be discarded as an unnecessary answer. It is possible to guarantee the operation.
[0054]
In particular, as shown in FIG. 16, if the present invention is applied to a bus interface circuit provided in an information processing system with an expanded bus configuration to guarantee an operation after a timer overflow, a very large effect is expected. it can.
This is because in such an extended information processing system, there is a high possibility that an answer will be returned at the critical timing described above due to the complexity of the request and answer transmission path, and in response to a timer overflow. This is because resetting all the buses to recover leads to a serious service degradation.
[0055]
Next, a method for dealing with the confusion of the correspondence between access requests and answers that occur in the case shown in FIG. 17 will be described.
FIG. 7 shows a bus interface circuit related to the present invention.
In FIG. 7, the bus interface circuit includes an answer control unit 231 and an acceptance control unit 232 instead of the answer control unit 221 shown in FIG. 5, and the answer control unit 231 passes the local bus transmission management unit 424. Answer discard control is performed, and an answer discard waiting notification to be described later is created. In response to the answer discard waiting notification, the admission control unit 232 sends a new access request via the local bus reception management unit 414. The reception process is controlled.
[0056]
As shown in FIG. 8, the answer control unit 231 includes a notification creation unit 235 including an AND gate 233 and a JK flip-flop 234, and an answer discard processing unit 236. The answer creation unit 235 obtains an answer. The answer discard processing unit 236 controls the read addresses of the reception buffer 423 and the reception management buffer 426 via the local bus transmission management unit 424 in response to the discard waiting notification and the answer reception notification.
[0057]
  In FIG. 8, the notification creation unit 235Access request acceptance notificationThe JK flip-flop 234 is set according to the logical product of the local bus access error notification and reset according to the answer discard end notification described later, so that the answer discard is output as the output of the JK flip-flop 234. It is configured to obtain a waiting notification.
[0058]
The answer discard processing unit 236 receives the answer reception notification indicating that the answer has been received when the logic “1” is input as the answer discard waiting notification, and sends the answer to the local bus transmission management unit 424. Thus, the read address is instructed to be incremented to the position where the corresponding answer is stored, and after the increment process is completed, an answer discard end notification indicating that the answer discard has ended is sent to the notification creating unit 234. ing.
[0059]
Therefore, the answer discard waiting notification becomes logic “1” in response to the occurrence of a local bus access error after the system bus access is started, and indicates that the answer discard is waiting. It becomes logic “0” in accordance with the end of the answer discard to be performed.
That is, the answer discard waiting notification indicates whether or not the processing on the local bus side regarding the unreached answer has been terminated.
[0060]
Therefore, the notification creation unit 235 realizes the functions of the mode setting unit 116 and the mode release unit 119 described above by creating the answer discard waiting notification as described above, and also the answer discard waiting notification. Accordingly, the answer discard processing unit 236 operates to realize the functions of the third answer determination unit 118 and the answer discard unit 113, and discard the answer that has been processed on the local bus side as an unnecessary answer. Can do.
[0061]
In FIG. 7, the reception control unit 232 corresponds to the request reception control unit 117 described above, and when the logic “1” is input as the answer discard waiting notification, the reception control unit 232 stores the logic in the local bus reception register 411. When a new access request is input, the local bus reception management unit 414 may be instructed to make a retry response to the access request via the local bus transmission management unit 424.
[0062]
In this case, as shown in FIG. 9, when the interruption of the processing corresponding to the access request 1 due to the interrupt request and the occurrence of an error in the retry request 1 corresponding to the access request 1 overlap, Accordingly, the answer discard waiting notification becomes logic “1”, and in response to this, a retry response is returned to the access request 2 issued from the CPU 401 thereafter.
[0063]
In response to the order 1 corresponding to the access request 1 interrupted by the interrupt request, the answer 1 returned from the system bus side is operated by the answer discard processing unit 236 operating in response to the answer discard waiting notification. Discarded.
In this way, until the answer 1 for the order 1 corresponding to the access request 1 interrupted by the interrupt request is received and discarded, a plurality of answers are returned by replying to a new access request. It is possible to eliminate the possibility of coming in and prevent the confusion between the correspondence between the access request and the answer in the bus interface circuit.
[0064]
As a result, even in a special situation as shown in FIG. 9, it is possible to guarantee normal operation of the information processing system thereafter by preventing confusion between the correspondence between the access request and the answer as described above. it can.
[0065]
However, as described above, if the answer is awaiting until the answer is received and the discard process is completed, there remains a problem in the operation when the answer is not returned due to a failure of the corresponding input / output device.
Hereinafter, a method for guaranteeing normal operation regardless of a failure on the system bus side will be described.
[0066]
FIG. 10 shows a bus interface circuit related to the present invention.
This bus interface circuit includes an answer control unit 241 instead of the answer control unit 231 shown in FIG. 7, creates an answer discard waiting notification in consideration of timer overflow in the answer control unit 241, and receives the control unit 232. And discarding the answer via the local bus transmission management unit 424.
[0067]
FIG. 11 shows a detailed configuration of the answer control unit 241.
In FIG. 11, the answer control unit 241 has a configuration in which an AND gate 233 and a JK flip-flop 234 are added to the notification creation unit 224 shown in FIG. 6 instead of the notification creation unit 235 shown in FIG. 8. A creation unit 242 is provided, and the answer discard processing unit 243 operates in response to the answer discard waiting notification obtained by the notification creation unit 242 and the timeout notification from the timer 417.
[0068]
This notification creation unit 242 inputs the answer waiting notification and local bus access error obtained by the JK flip-flop 223 to the input terminal J of the JK flip-flop 234 via the AND gate 233, and the answer discarding is completed. The notification is input to the input terminal K, and an answer discard waiting notification is obtained as an output of the JK flip-flop 234.
[0069]
The answer discard processing unit 243 starts operating in response to the release of the answer waiting state indicated by the answer discarding waiting notification, and reads it to the local bus transmission management unit 424 in response to reception of a new answer or a timeout notification. A configuration may be adopted in which an increment of the address is instructed to perform an answer discard process, and an answer discard end notification is sent to the notification creation unit 242 in response to the end of the answer discard process.
[0070]
In this case, in response to the occurrence of an error on the local bus in the answer wait state, the answer discard wait notification becomes logic “1” to indicate the answer discard wait state, and the answer to the discard target is received or the timer overflows. In response to the completion of the answer discarding process performed, the answer discard waiting state is released.
Therefore, as shown in FIG. 12, when the processing of the access request 1 is interrupted by the interrupt processing and an error occurs in the retry processing of the access request 1, the answer to be discarded reaches the set time of the timer 417. If not, the answer discard waiting state is canceled in response to the answer discard process accompanying the timer overflow, and a new access request can be accepted.
[0071]
If the answer 1 for the access request 1 shown in FIG. 12 is returned after the timer overflows, the processing may be left to the normal command reject function.
In this way, by controlling the answer discarding process in response to the answer discarding waiting notification in consideration of the timer overflow, the access request and answer in the bus interface circuit can be controlled regardless of the occurrence of a failure on the system bus side. Can be prevented, so that the reliability of the information processing system can be further improved.
[0072]
Further, since the local bus access error notification shown in FIG. 11 becomes logic “1” in response to the detection of the access error by the local bus reception management unit 414 and the occurrence of the timer overflow, the special error as described above occurs. Even if the timer overflow occurs, the JK flip-flop 234 is set due to the delay in the JK flip-flop 223, and the answer discard waiting notification becomes logic “1”.
[0073]
In response to this, the answer discard processing unit 243 immediately performs the answer discard process, so that even if an answer is returned at a critical timing as shown in FIG. Normal operation can be guaranteed.
By the way, if the characteristics of the answer 1 and the characteristics of the access request 2 shown in FIG. 17 are strictly verified by the verification circuit 211 shown in FIG. 2, the access request and the answer in the bus interface as described above are matched. It is also possible to prevent confusion between correspondences.
[0074]
However, in this case, the information to be collated by the collation circuit 211 is at least the entire address and the entire management information, and the number of gates necessary to configure the collation circuit 211 is greatly increased. The circuit scale becomes large.
Next, a method for preventing confusion between the correspondence between the access request and the answer as well as an erroneous response while suppressing the circuit scale of the bus interface circuit will be described.
[0075]
FIG. 13 shows a bus interface circuit related to the present invention.
This bus interface circuit adds the answer control unit 231 and the reception control unit 232 shown in FIG. 7 to the bus interface circuit shown in FIG. 2, and the answer discard processing unit 212 and the answer control unit 231 serve as a local bus transmission management unit. The reception control unit 232 controls the local bus reception management unit 414 according to the answer discard waiting notification obtained by the answer control unit 231.
[0076]
In this case, the admission control unit 232 operates in response to the answer discard waiting notification, responds to a new access request waiting for answer discard, and rejects the access request itself, as shown in FIG. Even in such a special case, the answer to be processed in the bus interface circuit can be specified.
[0077]
Accordingly, since it is not necessary to distinguish the characteristics of answers corresponding to similar access requests in the collation circuit 211, it is possible to narrow down information to be collated in the collation circuit 211.
In this case, for example, by comparing the upper few bits of the address with the management information, it is possible to sufficiently detect a mismatch between the characteristics of the access request and the characteristics of the answer. Compared to the case, the circuit scale of the verification circuit 211 can be greatly reduced.
[0078]
【The invention's effect】
As described above, the invention of claim 1 discards the answer in the reception buffer in response to the time-out notification, so that the access processing by the timer overflow can be performed regardless of the presence or absence of delay in the bus interface circuit. The normal operation of the information processing system after termination can be guaranteed.
[Brief description of the drawings]
FIG. 1 is a principle block diagram of a bus interface circuit of the present invention.
FIG. 2 is a diagram showing a bus interface circuit related to the present invention.
FIG. 3 is a detailed configuration diagram of a verification circuit.
FIG. 4 is a diagram illustrating an operation of a bus interface circuit.
FIG. 5 is a diagram showing an embodiment of a bus interface circuit of the present invention.
FIG. 6 is a detailed configuration diagram of an answer control unit.
FIG. 7 is a diagram showing a bus interface circuit related to the present invention.
FIG. 8 is a detailed configuration diagram of an answer control unit.
FIG. 9 is a diagram illustrating the operation of a bus interface circuit.
FIG. 10 is a diagram showing a bus interface circuit related to the present invention.
FIG. 11 is a detailed configuration diagram of an answer control unit.
FIG. 12 is a diagram illustrating the operation of a bus interface circuit.
FIG. 13 is a diagram showing a bus interface circuit related to the present invention.
FIG. 14 is a diagram illustrating a configuration example of a general information processing system.
FIG. 15 is a diagram illustrating a configuration example of a conventional bus interface circuit.
FIG. 16 is a diagram illustrating a configuration example of an extended information processing system.
FIG. 17 is a diagram for explaining the operation of the bus interface circuit;
[Explanation of symbols]
101 Transmission buffer
102 Receive buffer
111 verification means
112 First answer determination means
113 Answer disposal means
114, 417 timer
115 Second answer determination means
116 Mode setting means
117 Request reception control means
118 Third answer determination means
119 Mode release means
201, 215, 222 OR gate
211 Verification circuit
212, 225, 236, 243 Answer disposal unit
213 Address verification unit
214 Management information verification unit
221, 231, 241 Answer control unit
223, 234 JK flip-flop
224, 235, 242 notification creation unit
232 reception control unit
233 Andgate
401 CPU
402 memory
403 I / O device
404 Bus interface circuit
405 Bus expansion adapter
406 Bus controller
411 Local bus reception register
412 System bus transmission register
413 Transmission buffer
414 Local bus reception manager
415 System bus transmission manager
416 Transmission management buffer
421 Local bus transmission register
422 System bus reception register
423 Receive buffer
424 Local bus transmission manager
425 System Bus Reception Manager
426 Reception management buffer

Claims (1)

Connecting the first bus of the interlock transfer method and the second bus of the split transfer method, and sending the access request output to the first bus as an order to the second bus side through a transmission buffer; In a bus interface circuit configured to send an answer returned from the second bus as a response to the first bus side via a reception buffer,
A timer that outputs a time-out notification indicating that when a predetermined time has elapsed since the start of accepting an access request to the second bus side;
Answer determination means for determining whether the answer held in the reception buffer is an unnecessary answer that has already been invalidated on the first bus side in response to the timeout notification;
A bus interface circuit, comprising: an answer discarding unit for discarding a corresponding answer in the reception buffer according to a determination result indicating that the answer is an unnecessary answer.

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