JPH10289200A - Bus interface circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a bus interface circuit capable of performing appropriate management corresponding to the feature of an answer. SOLUTION: This bus interface circuit for connecting the first bus of an interlock transfer system and the second bus of a split transfer system is provided with a collation means 111 for collating the feature of an access request to a second bus side outputted to the first bus with the feature of the answer held in a reception buffer 102 corresponding to the access request, a first answer judgement means 112 for judging whether or not the answer held in the reception buffer 102 is an unrequired answer provided with the feature different from the feature of the access request based on a collated result by the collation means 111 and an answer abandonment means 113 for abandoning the pertinent answer inside the reception buffer 102 corresponding to the result of judging that it is the unrequired answer.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bus interface circuit for connecting an interlock transfer type bus and a split transfer type bus. In an information processing system including a CPU, such as a personal computer, different transfer methods are often used for a local bus directly connected to the CPU and a system bus for connecting various peripheral devices to each other. .
Normally, an interlock transfer system is used for a local bus, and a split transfer system is used for a system bus. The local bus and the system bus are connected via an interface circuit.

[0002]

2. Description of the Related Art FIG. 14 shows a configuration example of a general information processing system. In FIG. 14, an interlock transfer method is adopted for a local bus connecting the CPU 401 and the memory 402. When an access request is output from the CPU 401, the local bus continues until data transfer in response to the access request is completed. The bus is occupied by this access processing.

On the other hand, in the system bus adopting the split transfer system, after the order corresponding to the access request is output, the system bus is released while the processing on the input / output device 403 side is being performed, and the transfer is performed. When data to be prepared is ready, the system bus is acquired again to transfer data. As described above, if the split transfer method is adopted as the transfer method in the system bus, the other input / output device 403 can use the system bus during the processing in the input / output device 403 to be accessed, and the input / output The time required for processing can be used effectively.

As shown in FIG. 14, a local bus of an interlock transfer system is connected to a system bus of a split transfer system, and a bus interface circuit 404 is required for the CPU 401 to access the input / output device 403. To convert a request from the CPU 401 into an order according to the split bus transfer method, and return data from the input / output device 403 to the CPU 401 according to the interlock method.

FIG. 15 shows a configuration example of a conventional bus interface circuit. In FIG. 15, a local bus reception register 411 and a system bus transmission register 412
Are connected to a local bus and a system bus via buffers, respectively. The local bus reception register 411 and the system bus transmission register 412 are connected via a transmission buffer 413.

The local bus reception management unit 414 and the system bus transmission management unit 415 shown in FIG. 15 control the operation of the transmission buffer 413 based on the information held in the transmission management buffer 416. The configuration is such that a request from the CPU 401 is received via the local bus, the request is converted into an order according to the split transfer method, and transmitted to the system bus.

The above-described local bus reception management section 414
Are the transmission buffer 413 and the transmission management buffer 416
The write address to the CPU 401 may be controlled, and the management information such as the address specified by the request from the CPU 401 and the type of the request may be sequentially stored. Further, the system bus transmission management unit 415 determines the split transfer scheme from the contents of the transmission buffer 413 and the transmission management buffer 416 according to the difference between the last write address by the local bus reception management unit 414 and the last read address by itself. The system bus transmission register 412
Can be sent via the Internet.

On the other hand, in FIG. 15, a local bus transmission register 421 and a system bus reception register 422
Are connected to a local bus and a system bus via buffers, respectively. The local bus transmission register 421 and the system bus reception register 422 are connected via a reception buffer 423. FIG.
The local bus transmission management unit 424 and the system bus reception management unit 425 shown in FIG. 5 control the operation of the reception buffer 423 based on the information held in the reception management buffer 426, and are output to the system bus. An answer is received, converted into a response according to the interlock transfer method, and transmitted to the local bus.

The system bus reception management unit 425 and the local bus transmission management unit 424 sequentially write the answer and management information received from the system bus to the reception buffer 423 in the same manner as the above-described transmission side, and write at that time. What is necessary is just to read sequentially according to the difference between the address and the read address, and manage the response transmission to the local bus. Further, the local bus reception management unit 414 performs a protocol check and a parity check for each request received via the local bus, and according to the results of these checks, performs a local check via the local bus transmission management unit 424. The configuration is such that a retry request or an error notification is made to the bus.

The local bus reception management section 414
Is configured to start the timer 417 in response to the reception of a normal request, and the local bus transmission management unit 424
In response to the timeout notification from the timer 417, a timer overflow is notified to the CPU 401 for a request for which no answer has been returned. Here, when the input / output device 403 is functioning normally, C
A sufficient time may be set in the timer 417 as a time required for returning a response from the input / output device 403 to a request from the PU 401.

In this way, in the case where some trouble occurs on the input / output device 403 side, the response waiting state of the CPU 401 can be released and the processing can be continued in response to the above-mentioned timeout notification. For the detailed operation of the system bus transmission management unit and the system bus reception management unit, refer to Japanese Patent Application Laid-Open No. 3-67354, "Method of Determining Last Data in Transfer Data".

For a detailed description of the split transfer method, refer to Japanese Patent Application Laid-Open No. 3-253848, "Variable Bus Width Designation Method and Variable Bus Width Information Receiving Method in Split Bus". By the way, in a system having a plurality of CPUs for duplicating information processing or a system sharing an input / output device among a plurality of information processing systems, as shown in FIG. Further, there is a case where a configuration connected via a bus expansion adapter and a bus controller is employed.

In the information processing system as shown in FIG. 16, the CPU 401a includes an input / output device 4 connected to an extended system bus (hereinafter referred to as an extension bus).
03, the request sent from the CPU 401a to the local bus is transmitted to the bus interface circuit 404.
The data is converted into a corresponding order by a and transmitted to the system bus, and further transmitted to the target input / output device 403 via the bus expansion adapter 405 and the expansion bus.

On the other hand, when the CPU 401b accesses the above-mentioned input / output device 403, the request sent to the local bus by the CPU 401b is converted into a corresponding order by the bus interface circuit 404b and sent to the system bus. The data is passed to the system bus on the CPU 401a side via the bus controller 406, and furthermore, the input / output device 40
3 is transmitted.

The answer sent to the extension bus by the input / output device 403 reverses the path through which the corresponding request was transmitted, and the bus interface circuit 4
04a or 404b, and is converted into a corresponding response.
a, 401b.

[0016]

As described above, the conventional bus interface circuit manages the read operation from the transmission buffer 413 and the reception buffer 423 in accordance with the difference between the write address and the read address. Manages these correspondences using only the order of requests and the order of answers.

However, in an actual information processing system, a failure or the like occurring in the system bus causes
A write answer may occur for a read operation. In such a case, the conventional bus interface circuit 404 may return indefinite data as read data from the input / output device 403 to the CPU 401, which may cause a failure of the information processing system. There is.

In the conventional bus interface circuit, when an answer is simply returned within a predetermined time,
I received it as a normal answer. However, in the case of the extended information processing system as shown in FIG. 16, since the path for transmitting the request and the path for transmitting the answer are complicated, the access is performed in response to the timeout notification from the timer 417. Is interrupted, the answer from the input / output device 403 side becomes the bus interface circuit 4
04 in some cases.

Here, when the answer from the system bus arrives after the timer overflow, the reception of the answer itself can be rejected by the command reject function provided in the local bus transmission management unit 424. However, if the answer arrives immediately before the timer overflow, the bus interface circuit 404
May be held in the receiving buffer 423 as a normal answer, and thereafter, due to a timer overflow, the access process may be terminated without reading this answer.

In such a case, the answer returned immediately before the timer overflow is erroneously output to the local bus as a response to the new request from the CPU 401, whereby the information processing system becomes abnormal. There is a possibility of operating. As shown in FIG. 14, when the information processing system has a relatively simple configuration, by resetting both the local bus and the system bus in response to the above-mentioned timer overflow notification, the bus interface circuit 404 Was cleared, and the information processing system was restored.

However, in the extended system configuration as shown in FIG.
Resetting the entire system can lead to too severe a service degradation, so that no resetting recovery can be employed. Further, as described above, the bus interface circuit 404 merely mediates the transmission and reception of information between the local bus and the system bus. , Interrupt the processing of the normal access request, and perform the processing of the interrupt request with priority.

Therefore, as shown in FIG. 17, while the order 1 sent to the system bus in response to the access request 1 from the local bus side is processed by the corresponding input / output device, another order is received. When the interrupt order from the output device is transmitted to the local bus as a corresponding interrupt request via the bus interface circuit, the CPU 401
The processing of the access request 1 described above is interrupted, and the processing of the interrupt request is started preferentially.

In this case, after returning a response to the above-described interrupt request to the system bus via the bus interface circuit, the CPU 401 performs retry processing of the interrupted access request.

At this time, when an error response is returned from the bus interface circuit because the retryed access request 1 includes a parity error or the like, the CPU 40
1 may end processing of access request 1 and start processing of another access request 2. Now, at this time, when the answer 1 for the order 1 is input to the bus interface circuit, the bus interface circuit responds to the access request 2 by the reception buffer 423.
Answer 1 held in the memory is output to the local bus.

As described above, when the occurrence of the interrupt order from the system bus side and the retry failure of the interrupted access request overlap, the confusion of the correspondence between the access request and the answer occurs in the bus interface circuit. And normal operations could not be guaranteed thereafter. Therefore, there is a need for a technique for flexibly coping with various abnormal answers caused by a failure in a system bus or an extended system configuration and guaranteeing a normal operation of the information processing system.

An object of the present invention is to provide a bus interface circuit capable of performing appropriate management according to the characteristics of an answer.

[0027]

FIG. 1 is a block diagram showing the principle of a bus interface circuit according to the present invention.

According to the first aspect of the present invention, the first bus of the interlock transfer system is connected to the second bus of the split transfer system, and an access request received from the first bus is transmitted via the transmission buffer 101 to the second bus side. As an order to
In the bus interface circuit configured to send the answer returned from the second bus as a response to the first bus side via the reception buffer 102, the characteristics of the access request to the second bus side output to the first bus are described below. A matching unit 111 for matching the answer held in the reception buffer 102 in response to the access request; and an answer held in the reception buffer 102 based on the matching result by the matching unit 111. First answer determination means 112 for determining whether the answer is an unnecessary answer having a feature different from that of the first answer
And answer discarding means 113 for discarding the answer in the reception buffer 102 in accordance with the result of the determination that the answer is unnecessary.

According to the first aspect of the present invention, the first answer judging means 112 performs a judging operation according to the collation result by the collating means 111, and the answer discarding means 11
3 discards the answer held in the reception buffer 102, detects a feature mismatch between the access request received from the first bus side and the answer returned from the second bus side, and discards the unnecessary answer. be able to.

In this case, for example, if a write answer is erroneously returned from the second bus side in response to a read request, the write answer can be discarded as an unnecessary answer. It is possible to prevent an erroneous response such as outputting indefinite data to the device. The invention of claim 2 is
The first bus of the interlock transfer system is connected to the second bus of the split transfer system, and an access request received from the first bus is transmitted as an order to the second bus via the transmission buffer 101, and the second bus is transmitted. When the bus interface circuit configured to send the answer returned from the host as a response to the first bus side via the reception buffer 102, when a predetermined time has elapsed from the start of the access operation to the second bus side, A timer 114 that outputs a time-out notification indicating that the answer is affirmative, and a second method for determining whether or not the answer held in the reception buffer 102 is an unnecessary answer that has already become invalid on the first bus side in response to the time-out notification. Answer determining means 115 and an answer discarding means for discarding a corresponding answer in the receiving buffer 102 in accordance with a result of the determination that the answer is unnecessary. Characterized in that a 13.

According to a second aspect of the present invention, the second answer determination means 115 performs a determination operation in response to a time-out notification from the timer 114, and the answer discarding means 113 stores in the reception buffer 102 in accordance with the determination result. By discarding the answer that has been received, the answer that has become unnecessary due to the completion of the access processing on the first bus side is received.
02 can be removed.

Thus, regardless of the time required for the reading process from the reception buffer 102, the answer returned from the second bus at the critical timing immediately before the timer overflow can be discarded as an unnecessary answer without omission. The subsequent normal operation can be guaranteed. According to a third aspect of the present invention, the first bus of the interlock transfer system is connected to the second bus of the split transfer system, and an access request received from the first bus is ordered to the second bus side via the transmission buffer 101. In the bus interface circuit configured to transmit the answer returned from the second bus as a response to the first bus side via the reception buffer 102, and generate the answer generated after the start of the access operation to the second bus side. Mode setting means 116 for setting an answer discard wait mode in response to an access error on one bus side, and a new access request from the first bus to the second bus side during the period in which the answer discard wait mode is set. A request reception control unit 117 that returns a retry response to the request, and an answer stored in the reception buffer 102 depending on whether the answer discard wait mode is set. The third answer determination means 118 determines already whether the unnecessary answer became disabled in the first bus side
An answer discarding unit 113 for discarding a corresponding answer in the reception buffer 102 in accordance with the determination result that the answer is unnecessary, and an answer discard wait mode in response to completion of the answer discarding operation by the answer discarding unit 113. And a mode canceling means 119 for canceling.

A third aspect of the present invention is the mode setting means 116.
And the mode canceling means 119 to set and cancel the answer discarding wait mode. The third answer judging means 118 performs a judging operation according to the presence or absence of the answer discarding waiting mode, and according to the judgment result. Answer discarding means 1
13 discards the answer held in the reception buffer 102, so that an answer that has become invalid on the first bus side due to an error can be discarded as an unnecessary answer.

Also, depending on whether the answer discard wait mode is set or not, the request reception control means 117 replies to the access request and rejects the reception of a new access request until the unnecessary answer is discarded. However, confusion in the correspondence between the answer and the access request can be reliably prevented. According to a fourth aspect of the present invention, in the bus interface circuit according to the third aspect, when a predetermined time has elapsed from the start of the access operation to the second bus side, the timer 114 outputs a time-out notification indicating that. A second answer determination unit 115 that determines whether the answer held in the reception buffer 102 is an unnecessary answer already invalidated on the first bus side in response to the timeout notification. And

According to a fourth aspect of the present invention, the third answer determination means 1
18 or the second answer determination means 115
The answer discarding means 113 operates in accordance with the result of the determination to cancel the answer discard wait mode in response to the timer overflow and resume accepting a new access request even if the answer to be discarded does not arrive. Can be.

According to a fifth aspect of the present invention, in the bus interface circuit of the third aspect, the characteristics of the access request to the second bus side output to the first bus and the reception buffer 102 in response to the access request. A collation unit 111 for collating with the characteristics of the held answer, and based on the collation result by the collation unit 111, whether the answer held in the reception buffer 102 is an unnecessary answer having characteristics different from those of the access request. First answer determination means 1 for determining whether or not
12 is provided.

The invention according to claim 5 is characterized in that the request reception control means 11
7 can reliably prevent the correspondence between the answer and the access request from being confused. Therefore, the collation unit 111 allows the collation unit 111 to provide a part of the characteristic information indicating the characteristic of the access request and one of the characteristic information indicating the characteristic of the answer. By comparing with the unit, it is possible to reliably detect the mismatch of the feature, so that the amount of hardware required to configure the matching unit 111 can be significantly reduced.

[0038]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 2 shows an embodiment of the bus interface circuit according to claim 1. The bus interface circuit shown in FIG. 2 has a configuration in which a matching circuit 211 and an answer discard processing unit 212 are added to the bus interface circuit shown in FIG. The feature of the answer received from the bus is collated, and according to the collation result, the answer discarding unit 212 controls the local bus transmission management unit 424 and the system bus reception management unit 425, and is stored in the transmission buffer 423. It is configured to discard answer records.

This collating circuit 211 corresponds to the collating means 111 described in claim 1, and via the local bus reception register 411, together with the address of the request destination, whether the request type is block access or not. If the request management information is received as characteristics of the request, and the answer management information similar to the request management information described above is received together with the address of the answer source via the reception management buffer 426, and these information are mutually collated, Good.

The collation result by the collation circuit 211 is input to the local bus transmission management unit 424 via the OR gate 201 together with the error notification by the local bus reception management unit 414. FIG. 3 shows a detailed configuration of the matching circuit 211. Matching circuit 2 shown in FIG.
11, the address collation unit 213 is configured to collate at least a part of the request destination address with at least a part of the answer source address, and the management information collation unit 214 includes the request management information and the answer management information. Are compared.

The comparison result by the address collation unit 213 and the collation result by the management information collation unit 214 are as follows.
The configuration is such that the output of the matching circuit 211 is input to the OR gate 201 via the OR gate 215. Note that the address collation unit 213 and the management information collation unit 214 may be configured to output logic “0” when two input data match and output logic “1” when they do not match.

When the request management information corresponding to the read request and the answer management information corresponding to the write answer are input to the matching circuit 211, the output of the management information matching unit 214 becomes logic "1" and the matching circuit 211 Is output as logic "1" indicating mismatch. In this way, the inconsistency in the characteristics between the request and the answer is detected, and this detection result is sent to the local bus transmission manager 42 via the OR gate 201.
By notifying the error to the CPU 401, the error of the answer due to the fault occurring on the system bus side is regarded as the same error as the protocol error, as shown in FIG.
Can be notified.

In response to the input of the error notification via the OR gate 201, the local bus transmission management unit 424 sends a data transfer end and an error indication to the local bus via the local bus transmission register 421, and
01 may be notified of the occurrence of the error. Further, in response to the collation result indicating that the characteristics of the request and the answer do not match, the answer discarding unit 212 instructs, for example, the local bus transmission management unit 424 to stop reading from the reception buffer 423 and changes the read address. You only have to increment.

As described above, the collation circuit 211 obtains a collation result indicating whether or not a feature mismatch has been detected, and the answer discard processing unit 212 operates according to the collation result. By realizing the functions of the first answer determination unit 112 and the answer discarding unit 113 described in claim 1, an answer having a feature that does not match the feature of the request can be discarded as an unnecessary answer.

As a result, instead of reading out the erroneous answer from the reception buffer 423 and providing the answer for the response processing, the answer can be discarded as an unnecessary answer. In response to the error notification, the CPU 401 By performing appropriate error processing, for example, when a write answer is erroneously returned in response to a read request, it is possible to prevent the CPU 401 from capturing the erroneous answer.

As described above, it is possible to flexibly cope with an abnormal answer generated due to a failure in the system bus or the like, to prevent a subsequent malfunction of the information processing system, and to improve the reliability of the bus interface circuit. Can be. Next, a method for responding to an answer that arrives after a timer overflow will be described.

FIG. 5 shows an embodiment of the bus interface circuit according to claim 2. The bus interface circuit shown in FIG. 5 adds an answer control unit 221 to the bus interface circuit shown in FIG. 15, and this answer control unit 221 sends a system bus access start notification and a local bus transmission from the local bus reception management unit 414. The configuration is such that the operation of the local bus transmission management unit 424 is controlled in response to the local bus access error notification from the management unit 424.

Here, the local bus reception management section 414
Is configured to perform a parity check and a protocol check in the same manner as in the related art, and output a logical "1" as a system bus access start notification when it is determined that the access is appropriate. Further, in response to the system bus access start notification described above, the timer 417 starts the time counting operation and outputs a timeout notification indicating that a predetermined time has elapsed, thereby enabling the function of the timer 114 described in claim 2 to be performed. It is a configuration that realizes it.

Also, the local bus transmission management section 424
When at least one of an error notification from the local bus reception management unit 414 and a timeout notification from the timer 417 is received, a logical “1” is output as a local bus access error notification. In this case, as shown in FIG.
An answer control unit 221 includes a notification creating unit 224 including a flip-flop 223 and an answer discarding unit 225.
The answer discard processing unit 225 may control the local bus transmission management unit 424 in response to the answer waiting notification obtained by the notification creating unit 224.

In FIG. 6, the notification creator 224 sets the JK flip-flop 223 in response to the system bus access start notification, and resets it in response to the local bus access error notification or the answer reception notification, thereby providing a local bus access error. An answer waiting notification indicating whether or not the bus side is waiting for an answer from the system bus, that is, whether or not the reached answer is valid, is generated.

Here, the notification creating unit 224 receives a notification that a new answer has been written from the reception management buffer 426, and inputs it to the JK flip-flop 223 via the OR gate 222 as an answer reception notification. I just need. In addition, the answer discard processing unit 225
In response to the timeout notification from 17, the answer waiting notification becomes logic “0”, indicating that the answer waiting has been released, the read address is immediately incremented and the answer is discarded. .

As described above, the notification creating unit 224 creates the answer waiting notification that changes in response to the start of the system bus access and the occurrence of the timer overflow, and the answer discarding unit 225 operates in response to this. Accordingly, the functions of the second answer determination means 115 and answer discarding means 113 described in claim 2 can be realized, and the answer already invalidated on the local bus side can be discarded.

As a result, as shown in FIG. 4B, even when the answer is returned at a critical timing immediately before the timer overflows, the answer is reliably discarded regardless of the delay in the bus interface circuit. be able to. As a result, only the answer returned at the timing that can be processed by the CPU 401 is sent to the local bus as a response, and the answer to the access request for which the processing in the CPU 401 has been completed can be discarded as an unnecessary answer. Operation can be guaranteed.

In particular, as shown in FIG. 16, the above-mentioned invention of claim 2 is applied to a bus interface circuit provided in an information processing system having an extended bus configuration to guarantee the operation after the timer overflows. If this is the case, a very large effect can be expected. Because, in such an extended information processing system, due to the complexity of the transmission path of the request and the answer, there is a high possibility that the answer is returned at the strict timing as described above. This is because resetting and restoring all buses leads to serious service degradation.

Next, a method for coping with the confusion of the correspondence between the access request and the answer that occurs in the case shown in FIG. 17 will be described. FIG. 7 shows a third embodiment of the bus interface circuit. 7, the bus interface circuit includes an answer control unit 221 shown in FIG.
In place of the above, an answer control unit 231 and an admission control unit 232 are provided. The answer control unit 231 performs answer discard control via the local bus transmission management unit 424, and generates an answer discard waiting notification described later. Also, in response to the answer discard waiting notification, the reception control unit 232
Is configured to control the process of accepting a new access request via the local bus reception management unit 414.

As shown in FIG. 8, the answer control unit 231 includes an AND gate 233 and a JK flip-flop 2.
34 and the answer discard processing unit 2
In response to the answer discard waiting notification and the answer reception notification obtained by the notification creating unit 235, the answer discard processing unit 236 causes the reception buffer 423 and the reception management buffer 426 via the local bus transmission management unit 424. Is controlled.

In FIG. 8, the notification creation unit 235 determines the JK flip-flop 2 according to the logical product of the system bus access start notification and the local bus access error notification.
34, and resetting in response to the answer discard end notification described later, the JK flip-flop 23
As an output of No. 4, an answer discard waiting notification is obtained.

When the answer discard processing unit 236 receives the answer reception notification indicating that the answer has been received while the logical "1" is input as the answer discard waiting notification, the local bus transmission management unit Instruct 424 to increment the read address to the position where the corresponding answer is stored, and send an answer discarding completion notification to the notification creating unit 234 to the effect that answer discarding has been completed after this incrementing process. It has a configuration.

Therefore, the answer discard waiting notification becomes logic "1" in response to the occurrence of the local bus access error after the system bus access is started, indicating that the answer discarding is waiting. Becomes logical "0" in response to the end of answer discarding performed in accordance with. That is, the answer discard waiting notification indicates whether or not the processing on the local bus side regarding the unanswered answer has been completed.

Accordingly, the function of the mode setting means 116 and the mode releasing means 119 described in claim 3 is realized by the notification creating section 235 creating the answer discard waiting notification as described above. In response to the answer discard waiting notification, the answer discard processing unit 236 operates to realize the functions of the third answer judging means 118 and the answer discarding means 113, and the answer for which the processing on the local bus has been terminated is determined. It can be discarded as unnecessary answer.

In FIG. 7, the reception control unit 232
Corresponds to the request reception control means 117 described in claim 3, and is a logical "1" as the answer discard waiting notification.
Is input, the local bus reception register 4
11, when a new access request is input, the local bus reception management unit 414 may be instructed to make a retry response to the access request via the local bus transmission management unit 424.

In this case, as shown in FIG. 9, when the interruption of the processing corresponding to the access request 1 due to the interrupt request and the occurrence of the error in the retry request 1 corresponding to the access request 1 overlap, this error In response to the occurrence, the answer discard waiting notification becomes a logical “1”.
Thereafter, a retry response is returned to the access request 2 issued from the CPU 401.

For the order 1 corresponding to the access request 1 interrupted by the interrupt request, the answer 1 returned from the system bus is operated by the answer discard processing unit 236 in response to the answer discard waiting notification. To be discarded. In this manner, until the answer 1 for the order 1 corresponding to the access request 1 interrupted by the interrupt request is received and discarded, a plurality of answers are returned by retrying a response to the new access request. It is possible to eliminate the possibility of the access request and to confuse the correspondence between the access request and the answer in the bus interface circuit.

Thus, even in a special situation as shown in FIG. 9, by preventing confusion between the correspondence between the access request and the answer as described above, the normal operation of the information processing system thereafter is guaranteed. can do.

However, as described above, if the answer is awaited until the answer is received and discarded, the operation remains to be performed when the answer is not returned due to a failure in the corresponding input / output device. . Hereinafter, a method of guaranteeing normal operation regardless of a failure on the system bus side will be described.

FIG. 10 shows an embodiment of the bus interface circuit of claim 4. This bus interface circuit includes an answer control unit 241 in place of the answer control unit 231 shown in FIG. 7, and creates an answer discard waiting notification in consideration of a timer overflow inside the answer control unit 241, and And the control of discarding the answer via the local bus transmission management unit 424.

FIG. 11 shows a detailed configuration of the answer control unit 241. In FIG. 11, the answer control unit 241
6 is provided with a notification creation unit 242 having a configuration in which an AND gate 233 and a JK flip-flop 234 are added to the notification creation unit 224 shown in FIG. The answer discard processing unit 243 operates in response to the obtained answer discard waiting notification and the timeout notification from the timer 417.

The notification creating unit 242 sends the answer waiting notification and the local bus access error obtained by the JK flip-flop 223 to the J through the AND gate 233.
An input to the input terminal J of the -K flip-flop 234, an answer discard end notification is input to the input terminal K, and an answer discard waiting notification is obtained as an output of the JK flip-flop 234.

The answer discard processing unit 243 starts operating in response to the release of the answer waiting state indicated by the answer discard waiting notification, and responds to the reception of a new answer or a timeout notification in response to the local bus transmission managing unit. 42
4 is instructed to increment the read address, and the answer is discarded.
The answer discard end notification may be sent to the notification creating unit 242.

In this case, in response to the occurrence of an error in the local bus in the answer waiting state, the answer discard waiting notification becomes logic "1" to indicate the answer discard waiting state. The answer discard wait state is released in response to the end of the answer discarding process performed in response to the overflow. Therefore, as shown in FIG. 12, when the processing of access request 1 is interrupted by the interrupt processing and an error occurs in the retry processing of access request 1, the answer to be discarded arrives within the time set by timer 417. If not, the answer discard wait state is released according to the answer discarding process due to the timer overflow, and a new access request can be accepted.

Note that after the timer overflows,
In the case where the answer 1 to the access request 1 shown in (1) is returned, the processing may be left to the processing by the normal command reject function. In this way, by controlling the answer discarding process in response to the answer discard waiting notification in consideration of the timer overflow, regardless of the occurrence of a failure on the system bus side, the access request in the bus interface circuit and the answer Can be confused.
The reliability of the information processing system can be further improved.

The local bus access error notification shown in FIG. 11 becomes logic "1" in response to the detection of the access error by the local bus reception management unit 414 and the occurrence of the timer overflow. Even if no error occurs, the JK flip-flop 234 is set due to the delay in the JK flip-flop 223 in response to the timer overflow, and the answer discard waiting notification becomes logic "1".

In response, the answer discard processing unit 243 immediately performs answer discard processing.
It is possible to flexibly cope with a case where an answer is returned at a strict timing as shown in FIG. By the way, the matching circuit 21 shown in FIG.
1, the characteristics of the answer 1 shown in FIG. 17 and the characteristics of the access request 2 are strictly collated to prevent confusion in the correspondence between the access request and the answer in the bus interface as described above. It is possible.

However, in this case, the matching circuit 21
The information to be collated by 1 is at least the entire address and the entire management information, so that the number of gates required to configure the collation circuit 211 is greatly increased, and the circuit scale of the entire bus interface circuit is increased. Next, while suppressing the circuit scale of the bus interface circuit,
A method of preventing confusion in the correspondence between the access request and the answer together with the erroneous response will be described.

FIG. 13 shows a bus interface circuit according to an embodiment of the present invention. This bus interface circuit adds an answer control unit 231 and an admission control unit 232 shown in FIG. 7 to the bus interface circuit shown in FIG. 2, and provides an answer discard processing unit 212 and an answer control unit 231.
Controls the local bus transmission manager 424,
In response to the answer discard waiting notification obtained by the answer control unit 231, the reception control unit 232 switches the local bus reception management unit 4
14 is controlled.

In this case, the reception control unit 232 operates in response to the notification of waiting for the answer discard, replies to a new access request waiting for the answer discard, and rejects the reception of the access request 2 itself. In the special case as shown in FIG. 17, the answer to be processed in the bus interface circuit can be specified.

Therefore, since it is not necessary to distinguish the characteristics of answers corresponding to similar access requests in the matching circuit 211, it is possible to narrow down information to be compared in the matching circuit 211. In this case, for example,
By comparing the upper few bits of the address with the management information, it is possible to sufficiently detect a mismatch between the characteristics of the access request and the characteristics of the answer. The circuit size of the matching circuit 211 can be greatly reduced.

[0078]

As described above, according to the first aspect of the present invention, when an answer having a feature that does not match the feature of the access request arrives, the answer can be discarded as an unnecessary answer. It is possible to flexibly cope with an abnormal answer caused by a failure or the like occurring on the system bus side corresponding to the second bus, and prevent an erroneous response to the local bus side corresponding to the first bus.

Further, according to the present invention, the answer in the reception buffer is discarded in response to the time-out notification, so that regardless of the presence or absence of the delay in the bus interface circuit, the access processing after the timer overflow is terminated. Normal operation of the information processing system can be guaranteed. Further, according to the invention of claim 3, according to the setting and release of the answer discard wait mode, a new access request accepting operation and an answer discarding operation of the answer arrived from the second bus side are performed, so that an internal bus interface circuit is provided. Since the correspondence between the access request and the answer can be prevented from being confused, even if the processing of the interrupted access request is terminated due to an error or the like, the subsequent normal operation of the information processing system can be guaranteed. it can.

Further, the invention of claim 4 applies the invention of claim 3 in combination with the invention of claim 2, and releases the answer discard wait mode in response to the arrival of the answer to be discarded or the timer overflow. Accordingly, it is possible to flexibly cope with a case where the answer to be discarded has not reached due to the occurrence of a failure on the system bus side. Also,
According to the invention of claim 5, by applying the invention of claim 3 in combination with the invention of claim 1, it is possible to narrow down the information to be collated by the collating means, and to form the collating means. The amount of hardware can be reduced.

[Brief description of the drawings]

FIG. 1 is a principle block diagram of a bus interface circuit of the present invention.

FIG. 2 is a diagram showing an embodiment of the bus interface circuit of claim 1;

FIG. 3 is a detailed configuration diagram of a matching circuit.

FIG. 4 is a diagram illustrating the operation of the bus interface circuit.

FIG. 5 is a diagram showing an embodiment of a bus interface circuit according to claim 2;

FIG. 6 is a detailed configuration diagram of an answer control unit.

FIG. 7 is a diagram showing an embodiment of a bus interface circuit according to claim 3;

FIG. 8 is a detailed configuration diagram of an answer control unit.

FIG. 9 is a diagram illustrating the operation of the bus interface circuit.

FIG. 10 is a diagram showing an embodiment of a bus interface circuit according to claim 4;

FIG. 11 is a detailed configuration diagram of an answer control unit.

FIG. 12 is a diagram illustrating the operation of the bus interface circuit.

FIG. 13 is a diagram showing an embodiment of a bus interface circuit according to claim 5;

FIG. 14 is a diagram illustrating a configuration example of a general information processing system.

FIG. 15 is a diagram illustrating a configuration example of a conventional bus interface circuit.

FIG. 16 is a diagram illustrating a configuration example of an extended information processing system.

FIG. 17 is a diagram illustrating the operation of the bus interface circuit.

DESCRIPTION OF SYMBOLS 101 transmission buffer 102 reception buffer 111 collation means 112 first answer determination means 113 answer discarding means 114,417 timer 115 second answer determination means 116 mode setting means 117 request reception control means 118 second answer determination means 119 Mode release means 201, 215, 222 OR gate 211 Collation circuit 212, 225, 236, 243 Answer discard processing unit 213 Address collation unit 214 Management information collation unit 221, 231, 241 Answer control unit 223, 234 JK flip-flop 224, 235, 242 Notification creation unit 232 Reception control unit 233 AND gate 401 CPU 402 Memory 403 Input / output device 404 Bus interface circuit 405 Bus expansion adapter 406 Bus controller 411 Row Bus reception register 412 system bus transmission register 413 transmission buffer 414 local bus reception management unit 415 system bus transmission management unit 416 transmission management buffer 421 local bus transmission register 422 system bus reception register 423 reception buffer 424 local bus transmission management unit 425 system bus reception Management unit 426 Reception management buffer

Continued on the front page (72) Inventor Makoto Okazaki 4-1-1, Kamidadanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture Inside Fujitsu Limited (72) Inventor Katsuyuki Okada 3-192-2 Nishishinjuku, Shinjuku-ku, Tokyo Nippon Telegraph and Telephone Telephone Co., Ltd. (72) Inventor Tokuo Hosaka 3-19-2 Nishi Shinjuku, Shinjuku-ku, Tokyo Japan Telegraph and Telephone Co., Ltd.

Claims (5)

[Claims] 1. A first bus of an interlock transfer system and a second bus of a split transfer system are connected, and an access request received from the first bus is sent as an order to the second bus via a transmission buffer. A bus interface circuit configured to transmit the answer returned from the second bus as a response to the first bus side via a reception buffer, wherein the bus interface circuit outputs the answer to the second bus side output to the first bus. Collating means for collating the characteristics of the access request and the characteristics of the answer held in the receiving buffer in response to the access request; and the answer held in the receiving buffer based on the collation result by the collating means. First answer determining means for determining whether the answer is an unnecessary answer having characteristics different from those of the access request, and a determination result indicating that the answer is an unnecessary answer And an answer discarding means for discarding a corresponding answer in the reception buffer in response to the request. 2. A first bus of an interlock transfer system and a second bus of a split transfer system are connected, and an access request received from the first bus is sent as an order to the second bus via a transmission buffer. A bus interface circuit configured to transmit the answer returned from the second bus as a response to the first bus side via a reception buffer, wherein the bus interface circuit transmits a response to the second bus side from a start of an access operation to the second bus side. A timer for outputting a time-out notification indicating that the time has elapsed; and an answer stored in the reception buffer in response to the time-out notification. Second answer determining means for determining whether there is any answer, and discarding the corresponding answer in the reception buffer according to the determination result that the answer is unnecessary. A bus interface circuit comprising answer discarding means. 3. A first bus of an interlock transfer system and a second bus of a split transfer system are connected, and an access request received from the first bus is sent as an order to the second bus via a transmission buffer. A bus interface circuit configured to send an answer returned from the second bus as a response to the first bus via a reception buffer, wherein the answer occurs after the start of the access operation to the second bus. Mode setting means for setting an answer discard wait mode in response to an access error on the first bus side; and a period from the first bus to the second bus side during the period in which the answer discard wait mode is set. Request reception control means for returning a retry response to a new access request; and, in the reception buffer, Third answer determining means for determining whether or not the received answer is an unnecessary answer that has already been invalidated on the first bus side; and a third answer determining means for determining whether the answer is an unnecessary answer. A bus interface circuit comprising: an answer discarding unit for discarding an answer corresponding to the above condition; and a mode canceling unit for canceling the answer discarding waiting mode in response to completion of the answer discarding operation by the answer discarding unit. 4. The bus interface circuit according to claim 3, wherein when a predetermined time elapses from the start of the access operation to the second bus side, a timer for outputting a timeout notification indicating that, and the timeout A second answer determination unit configured to determine, in response to the notification, whether the answer held in the reception buffer is an unnecessary answer already invalidated on the first bus side. Interface circuit. 5. The bus interface circuit according to claim 3, wherein a characteristic of an access request to the second bus side output to the first bus and an answer of the answer held in the reception buffer in response to the access request. Collating means for collating the characteristic; and, based on a collation result by the collating means, determining whether or not the answer held in the reception buffer is an unnecessary answer having a characteristic different from the characteristic of the access request. A bus interface circuit comprising: a first answer determination unit.