JP2941005B2 - Storage controller - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] A storage control device for controlling two storage devices such as a main storage device and a system storage device. And a register capable of holding a processing request for the first storage device, and a register for determining whether a processing request for data transmission / reception to / from the second storage device is held. A queue buffer capable of temporarily storing transmission / reception data between the second storage device, a counter for managing the number of data stored in the queue buffer, And data management means for managing the number of data transmitted / received to / from the storage device and detecting whether there is remaining data to be transmitted / received. When a failure occurs during data transfer between the storage devices, writing of transfer data to the destination storage device is suppressed, and only processing requests for the specified number of transfer data items are executed and terminated. .

[Industrial applications]

The present invention relates to two storage systems, such as main storage and system storage.
The present invention relates to a storage controller that controls two storage devices, and more particularly to processing in a storage controller when a failure occurs during data transfer between two storage devices.

2. Description of the Related Art In recent years, information processing apparatuses are provided with a large-capacity system storage device in addition to a main storage device in order to increase processing speed and processing capacity. Reference or update to the system storage device is performed by data transfer between the system storage device and the main storage device by the storage control device. In data transfer between storage devices, a certain amount of data can be processed by a single processing request in order to increase processing efficiency. At this time, if a failure occurs in processing individual data, appropriate processing is required for unprocessed data.

[Conventional technology]

FIG. 3 is a configuration diagram of a conventional example of a storage control device to which the present invention is directed.

In FIG. 3, reference numeral 1 denotes a processing request source device such as a CPU or CHP, and only one device is shown for simplification of the drawing.

 2 is a storage control device.

 3 is a main storage device.

 4 is a system storage device.

A system storage device control circuit 5 controls writing and reading of data to and from the system storage device 4.

Reference numeral 6 denotes a transfer data number management circuit, which instructs the system storage device control circuit 5 on the number of remaining data associated with the progress of processing based on the number of transfer data specified by the processing request.

Reference numeral 7 denotes a queue buffer which temporarily holds transfer data between the main storage device 3 and the system storage device 4 in the order of input.

Reference numeral 8 denotes a queue buffer management circuit, which counts up each time data is input to the queue buffer 7 and counts down each time data is output from the queue buffer 7, and counts the transfer data held in the queue buffer 7. The number is indicated to the system storage control circuit 5.

Reference numeral 9 denotes a decoder, which detects a data transfer activation request between storage devices among the processing requests from the processing request source device 1 and notifies the system storage device control circuit 5 of it.

Reference numeral 10 denotes a register, which is a port for holding a processing request input from the processing request source device 1.

Reference numeral 11 denotes a priority selection circuit, which takes priority on a processing request from the processing request source apparatus 1 or another apparatus (not shown) and selects one processing request.

The inter-storage data transfer activation request output from the processing request source device 1 during operation is set in the register 10, and when selected by the priority selection circuit 11, the system storage device control circuit 5 is activated and the data transfer amount is simultaneously reduced. It is set in the transfer data number management circuit 6. Data transfer from the system storage device 4 to the main storage device 3 or from the main storage device 3 to the system storage device 4 based on the request is performed by the queue buffer management circuit 8 via the queue buffer 7.

[Problems to be solved by the invention]

In conventional data transfer between storage devices, even if a failure occurs during individual data transfer, the processing is intended to be continued until the processing of a given data amount is completed. In addition, when a serious failure occurred, the processing was immediately interrupted.

Therefore, if data transfer between storage devices is continued even after a failure occurs, erroneous data may be written to the write destination storage device, or data transfer may not be continued with data remaining in the queue buffer. There has been a problem that the data cannot be written and the data hangs.

Further, when the data transfer is interrupted in the middle, or when the number of transmission / reception data specified in advance and the number of processing requests for the corresponding main storage device do not match, the processing for the main storage device after the data transfer is completed. There is a possibility that the request may remain, causing problems such as destroying the contents of the main storage device and making it indistinguishable from a processing request for the main storage device relating to data transfer between subsequent storage devices.

The present invention is intended to minimize the influence of a failure in data transfer between storage devices, to ensure that subsequent processing can be started correctly, and to prevent data in the storage device from being destroyed. It is an object of the present invention to provide a storage control device capable of performing such operations.

[Means for solving the problem]

The present invention suppresses writing to a data transfer destination storage device when a failure occurs during data transfer between two storage devices such as a main storage device and a system storage device in a storage control device. In addition to eliminating the possibility of erroneous data being written, the processing of a data transfer processing request continues at the beginning for the number of data transfers specified at the beginning, and ends. To get rid of it.

 FIG. 1 is a diagram showing the basic configuration of the present invention.

In the figure, 1 is a processing request source device, 2 is a storage control device, 3 is a main storage device (corresponding to a first storage device in claims), and 4 is a system storage device (second storage device in claims). 5 is the system storage device control circuit, 6
Is a transfer data number management circuit, 7 is a queue buffer, 8 is a queue buffer management circuit, 9 is a decoder, 10 is a register, and 11 is a priority selection circuit, and their functions have been described in the conventional device in FIG. Same as the ones. Also
Numeral 12 is a fault occurrence latch, which is set to ON when any data transfer fault occurs. A gate 13 is controlled when data transfer between storage devices is suppressed.

The data transfer start request between the storage devices from the processing request source device 1 is set in the register 10, and when selected by the priority selection circuit 11, the system storage device control circuit 5 is started, and at the same time, the data transfer amount is reduced by the transfer data number. It is set in the management circuit 6. Data transfer between the main storage device 3 and the system storage device 4 is performed by the queue buffer management circuit 8.
Is performed via the queue buffer 7.

If a failure occurs during this data transfer, the failure occurrence display latch 12 is turned on, so that the control of the queue buffer 7 is suppressed based on this, and the write data to the main storage device 3 is gated and the system storage Writing to the device 4 is also prohibited. The system storage device control circuit 5 outputs the output of the decoder 9 for detecting that the main storage device processing request for data transfer between the storage devices is held at the port 10 and the amount of data remaining in the queue buffer 7. After referring to the output of the queue buffer management circuit 8 indicating the number of transfer data and the output of the transfer data number management circuit 6 indicating the number of remaining transfer data, after recognizing that all the processing requests to the main storage device 3 have been processed, It operates to end the data transfer processing.

[Action]

According to the present invention, when a failure occurs during data transfer, data transfer can be suppressed, and writing of erroneous data to the main storage device 3 can be prohibited. Also, writing to the system storage device 4 can be prohibited. Further, by processing all remaining processing requests to the main storage device 3,
The contents of the main storage device 3 can be prevented from being destroyed, and the data transfer between the subsequent storage devices can be correctly started.

〔Example〕

An embodiment of the present invention will be described with reference to FIG. The figure is a block diagram of the apparatus of the embodiment, and elements 1 to 12 in the figure correspond to the elements of the same number in FIG. Also added in FIG.
13 to 16 are gates, and 17 to 37 are signal lines.

When the processing request source device 1 issues a data activation request between storage devices and a processing request to the main storage device 3 accompanying the request, the processing request is set to the register 10 used as a port by the signal line 17. The processing request set in the register 10 is output from the signal line 18 and waits for selection by the priority selection circuit 11.

When the data transfer start request between the storage devices is selected by the priority selection circuit 11, the start of the data transfer between the storage devices is instructed to the system storage device control circuit 5 by the signal line 20, and at the same time, the data transfer amount becomes the transfer data number. It is set in the management circuit 6.

As a result, the system storage device control circuit 5
The queue buffer 7 and the queue buffer management circuit 8 are initialized by 25, and then data transfer between the storage devices is started. During normal operation, the fault indication latch is OFF, and gates 13 and 16 are open at this time.

First, a case of data transfer from the main storage device 3 to the system storage device 4 will be described.

The data read request from the main storage device 3 is issued from the processing request source device 1 and is set in the register 10 by the signal line 17. When this request is selected by the priority selection circuit 11 via the signal line 18, a read request is sent to the main storage device 3 via the signal line 19.

As a result, when read data is output from the main storage device 3 via the signal line 37, an input instruction signal is output from the system storage device control circuit 5 to the queue buffer 7 using the signal line 28. This instruction signal passes through the gate 14 and the signal line 29
Is input to the queue buffer 7.

When the system storage device 4 does not output a write data reception disable signal to the signal line 32, an output instruction is issued from the control circuit 5 to the queue buffer 7 by the signal line 26, and this is transmitted through the gate 13 to the queue buffer 7 from the signal line 27. When input to the buffer 7, the signal is sent from the queue buffer 7 to the signal line 23.
The data is output to At this time, the control circuit 5
A signal indicating that the write data is valid is output by the signal 34, the gate 15, and the signal line 35, and the write is instructed to the system storage device 4.

If a failure occurs during data transfer from the main storage device 3 to the system storage device 4, the failure occurrence display latch 12 is turned on.
And the gates 13 to 16 are all inhibited by the signal line 31, and the input to the queue buffer 7, the output from the queue buffer 7, the write instruction to the system storage device 4, and the reception of write data from the system storage device 4 are disabled Reference to the signal indicating is prohibited.

On the other hand, the decoder 9 checks whether a processing request for the main storage device 3 for data transfer between the storage devices is held in the register 10, and the result is output to the signal line 21.

Further, whether or not processing corresponding to the data transfer amount designated in advance remains is output from the transfer data number management circuit 6 to the signal line 22. Further, the presence / absence of data to be held in the queue buffer 7 when no failure occurs is output from the queue buffer management circuit 8 via a signal line 30.

After recognizing that all processing requests to the main storage device 3 for data transfer between storage devices have been processed based on these pieces of information, the system storage device control circuit 5 ends the data transfer process. At this time, the fault occurrence display latch 12 is reset to OFF by the signal line 36, and the gates 13 to 16 are opened.

Next, a case of data transfer from the system storage device 4 to the main storage device 3 will be described.

Data read from the system storage device 4 is transmitted through a signal line.
When the data is output from the control circuit 5 to the signal line 28 to the queue buffer 7 and from the gate 14 to the signal line 29, the data is input to the queue buffer 7. When an output instruction from the control circuit 5 to the queue buffer 7 is output to the queue buffer 7 via the signal line 26, the gate 13, and the signal line 27, the signal line 24
The data is output to

The write data to the main storage device 3 is set in the register 10 together with the write request to the main storage device 3 issued from the processing request source device 1. When this is selected by the priority selection circuit 11 by the signal line 18, the signal line
At 19, a write request is sent to the main storage device 3.

Even when a failure occurs during data transfer from the system storage device 4 to the main storage device 3, the failure occurrence display latch 12 is set, the gates 13 to 16 are inhibited by the signal line 31, and the input to the queue buffer 7 is performed. , Output from the queue buffer 7 is prohibited.

In the same manner as in the case of data transfer from the main storage device 3 to the system storage device 4, it is checked whether all processing requests to the main storage device 3 for data transfer between storage devices have been processed. The transfer process ends. At this time, the fault occurrence latch
12 is reset.

As described above, when a failure occurs during data transfer between storage devices, useless data writing is prohibited, and after all processing requests to the main storage device for data transfer between storage devices are processed. It operates to end the data transfer process.

〔The invention's effect〕

As described above, according to the present invention, even when a failure occurs in data transfer between storage devices, it is possible to prevent data in the storage device from being destroyed and to set a state where subsequent processing can be started correctly. Therefore, the reliability in using the system storage device can be significantly improved.

[Brief description of the drawings]

FIG. 1 is a block diagram of the principle of the present invention, FIG. 2 is a block diagram of a device according to an embodiment of the present invention, and FIG. 3 is a block diagram of a conventional example of a storage control device. 1, a processing request source device 2: a storage control device 3: a main storage device 4: a system storage device 5: a system storage device control circuit 6: a transfer data number management circuit 7: a queue buffer 8: a queue buffer management circuit 9 : Decoder 10: Register (port) 11: Priority selection circuit 12: Failure occurrence display latch

Claims (2)

(57) [Claims] A storage device connected to a first storage device and a second storage device and having a function of transmitting and receiving data between the first storage device and the second storage device in response to a processing request. In the control device, a register capable of holding a processing request for the first storage device, and decoder means for detecting whether the register holds a processing request for data transmission / reception to / from the second storage device, , A queue buffer capable of temporarily storing data transmitted to and received from the second storage device;
A queue buffer management circuit that manages the number of data stored in the queue buffer; and data that manages the number of data sent and received between the second storage device and can detect whether there is remaining data to be sent and received. Management means, and when a failure occurs during data transfer between the first storage device and the second storage device, the writing of the transfer data to the storage device at the data transfer destination is suppressed and the processing request is issued. Perform the processing of
A storage control device for terminating a data transfer process when all processing requests corresponding to a previously specified number of data to be transmitted and received have been processed. 2. The method according to claim 1, wherein the fault is a fault for which it is not possible to guarantee that the number of data to be transmitted and received specified in advance and the number of processing requests to the corresponding first storage device cannot be guaranteed. What is claimed is: 1. A storage control device, wherein a data transfer process is terminated when all processing requests for a first storage device have been processed, regardless of whether there is remaining data to be transmitted or received.