JPH05265789A - Memory copy system - Google Patents

Abstract

PURPOSE:To quickly and accurately copy memory information in a duplex system by providing a common bus controller which recognizes write to the information storage part of a first unit and transfers this information to a second unit to copy it. CONSTITUTION:When recognizing write to an information storage part 1b in a first unit 1, a common bus controller 3 sets a confounding line on a bus to transfer write information to a second unit 2. The second unit 2 receives write information to store it in an information processing part 2b connected to an information processing part 2a by this processing part 2a. In this duplex system, information can be read out of the second unit 2 when a fault occurs in the information storage part 1b of the first unit 1, and the time of access from the first unit 1 to the second unit 2 is shortened because the access passes a common bus 5.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a plurality of processing systems connected by a common bus for transferring information, and stores information stored in any processing system to another processing system via a processing device and a memory bus. The present invention relates to a memory copying method in a duplicated system for copying.

[0002]

2. Description of the Related Art With recent advances in computer system hardware and software technologies, online systems such as local area networks (LAN) and world area networks (WAN) have been remarkably popularized. Further improvement in reliability is required. That is, in the device control device that constitutes the local area network, etc., two processing systems are required in order to enable prompt recovery when a failure occurs. It has a dual configuration.

A duplex system used in an electronic exchange or the like has two processing systems each having at least a central processing unit and a main storage unit, and one processing unit and the other main storage unit are connected to a bus. The write operation is executed from the central processing unit of one system to the main memory devices of both systems, and the read operation is executed only from one of the main memory devices of both systems. It has become.

According to this dual configuration system, since the contents stored in the main storage devices of both systems are the same, when a failure occurs in the main storage device of one system, the main storage device of the other system is operated. The process can be continued by reading the information. As a result, the system can be started up faster than the method of retrying after the checkpoint.

In such a redundant configuration system, although the machine cycle of the central processing unit is shortened by using the element having a high operating speed, the access time to the main memory is still long, and the operating speed and the main memory of the central processing unit are still long. There is a gap between the access time and the device. In other words, when considering the processing capacity of the entire redundant system, the processing as a whole will be performed according to the main storage device with a slow access time, during which idle time will occur in the central processing unit, and the processing of the entire system will occur. It was an obstacle to improving their abilities.

Therefore, in order to consume the above play time, a buffer memory device is provided between the central processing unit of each processing system and the main memory device, and information to be written in the main memory device is temporarily stored in this buffer memory device. By temporarily storing the data, the central processing unit can immediately proceed to the next processing as soon as the processing is completed.

When accessing a specific address from the central processing unit, if the content of the specific address is stored in the buffer storage device, the information is read from the buffer storage device, and if not stored, the main memory is stored. The contents are read from the device and rewritten with the least frequently used contents in the buffer storage device.

Here, in a duplex configuration system using a buffer storage device, in the copy back system in which only the contents of the buffer storage device are rewritten when a request is made to rewrite the memory contents from the central processing device, the central processing device Since the memory device is rewritten and read, there is an advantage that the processing speed can be increased.

However, in response to a memory content rewriting request from the central processing unit, only the contents of the buffer memory device are rewritten, so that there is information that does not exist in the main memory device but only in the buffer memory device. That is, the contents of the main storage devices of both systems are the same, but the contents of the buffer storage device may be different. At this time, if a failure occurs in the buffer storage device of one system, the information existing only in the buffer storage device of one system is erased, and there is a problem that the processing cannot be continued. Therefore, further, a memory bus between the buffer storage devices of both systems and a memory bus control device for setting a confounding path on the memory bus are set, and the memory bus control device writes / writes to the buffer storage device in one processing system. A memory copy method has been known in which, when a rewrite request is recognized, a confounding path is set on the memory bus and the write / rewrite content is copied to the buffer storage device of the other system.

According to this, the sameness of the contents of the buffer storage device is guaranteed along with the main storage devices of both systems, so that even if a failure occurs in the main storage device or the buffer storage device in one processing system, the other Since the data can be read from the main storage device or the buffer storage device of the processing system, the processing can be continuously executed.

[0011]

However, the above-mentioned method has a problem that even if the processing device is speeded up, the access speed to the buffer storage device is slow and the processing capacity of the entire system is not improved.

Further, it is uneconomical to improve the processing capability of the entire system by providing a high-speed buffer storage device because the system becomes expensive. On the other hand, even if a large capacity memory bus is used, it is meaningless because there is a limit to the access time to each information storage device.

Further, it is necessary to provide a dedicated device for setting the confounding path on the memory bus, which has the drawbacks of complicated control and increased delay time. Therefore, the present invention has been made in view of the above problems, and it is a technical problem to provide a method capable of economically and rapidly realizing the copying of stored contents in a system including a duplicated information storage device. And

[0014]

The present invention has the following features to solve the above problems. This will be described based on the principle diagram of FIG.

The duplex system according to the present invention comprises first and second units 1, 2 having at least information processing units 1a, 2a and information storage units 1b, 2b connected thereto.
A common bus 5 connecting the first and second units,
It has a common bus control device 3 installed on the bus.

The common bus control device 3 recognizes the writing to the information storage unit 1b in the first unit 1, sets an interlinking path on the common bus 5, and sets the write information to the second information. Is a device for transferring to the unit 2 and copying to the information storage unit 2b.

Also, the first and second units 1, 2
Is an information discriminating apparatus 1 for discriminating data to be copied.
c and 2c may be provided. In this case, the memory bus controller 4 for setting the confounding path between the information storage units 1b and 2b is provided on the memory bus 6.

[0018]

According to the present invention, when the common bus control device recognizes writing to the information storage unit in the first unit, the common bus control device sets a confounding path on the bus and writes the write information. To the second unit.

In the second unit which has received the write information, the information processing section stores the write information in the information storage section connected to itself. With this, in the duplex system, information can be read from the second unit when a failure occurs in the information storage unit in the first unit, and the first unit can transfer the information to the first unit in order to pass the common bus. The access time to the second unit can be shortened.

Further, by providing an information discriminating device in each unit and connecting the information storage units of both processing systems via a memory bus and a memory bus control device for setting a confounding path on the memory bus, common When the bus controller and the memory bus controller recognize writing in the information storage unit in the first unit, the common bus controller sets a confounding path on the common bus and the memory bus controller confounds on the memory bus. A path is set and transfer / copy is performed to the information storage unit of the other system. At this time, the information discriminating apparatus of the other system compares the information transferred via the common bus with the information transferred via the memory bus, and compares the information arriving earlier to the unit with the information. Copying to the storage unit enables more efficient copying.

[0021]

EXAMPLES Specific examples of the present invention will be described below. (Embodiment 1) FIG. 2 is a schematic configuration diagram of a duplex system in the present embodiment 1.

The duplex system in the first embodiment is composed of a working system unit 7 and a standby system unit 8 which are connected via a common bus 15 and common bus control devices 12 and 13.

The active system unit 7 in the first embodiment is
It has an input / output device 7a connected to the common bus 15a via the interface unit 9, a central processing unit (hereinafter referred to as CPU) 7b, and a memory 7c connected to the CPU 7b.

The standby system unit 8 includes an input / output device 8a and a CPU 8b which are connected to the common bus 15b through an interface section 9, and a memory 8c which is connected to the CPU 8b.
To have.

Input / output device 7a / 8a in the first embodiment
Is an apparatus for inputting / outputting data to / from the active system unit 7 / standby system unit 8. The memories 7c / 8c are devices for storing data.

The CPUs 7b / 8b are devices for processing data input / output to / from the active system unit 7 / standby system unit 8 and controlling writing / reading of data in the memories 7c / 8c.

The common bus control unit 12 on the working system side has one end via the interface unit 9 and the common bus 15 on the working system side.
The other end is connected to the common bus control device 13 on the standby system side through the confounding path.

As described above, the common bus control device 13 on the backup system side has one end connected to the common bus control device 12 on the working system side via the confounding path and the other end on the backup system side via the interface section 9. It is connected to the common bus 15b.

The common bus controller 12 has a common bus 15a.
Is a device for recognizing data writing to the memory 7c, setting a confounding path from itself to the common bus control device 13 of the standby system, and transferring the write data.

The common bus controller 13 transfers the write data transferred through the confounding path to the memory 8 of the spare system.
This is a device for copying to c. FIG. 3 is a flowchart showing an operation process of memory copy of the duplex system in the first embodiment.

In the duplex system in the first embodiment,
When a data write command is input from the input / output device 7a of the active system unit 7 to the memory 7c (step 3
01), the CPU 7b receives the write command and writes the write data to the memory bus 7c (step 3).
02), the common bus control device 12 recognizes the write command (step 303) and monitors the common bus 15a to detect the write data (step 30).
4).

Here, the common bus control device 12 sets a confounding path for the common bus control device 13 on the side of the standby system unit 8 (step 305) and transfers the write data through it (step 306).

The common bus controller 13 on the side of the standby system unit 8 which has received the write data is the standby system CPU 8b.
The write data is transferred to and the copy instruction to the memory 8c is issued (step 307).

C which has received the copy instruction of the write data
The PU 8b copies the write data to the memory 8c (step 308). Therefore, according to the first embodiment, since the memory data to be copied is transferred from the active system unit to the standby system unit through the common bus, the transfer time can be shortened. That is, it is possible to improve the processing capacity of the entire duplex system.

(Embodiment 2) FIG. 4 is a schematic configuration diagram of a duplex system in the present embodiment 2. The duplex system in the second embodiment is composed of an active system unit 7 and a standby system unit 8 connected via a common bus 15 and common bus control devices 12 and 13.

Further, in the second embodiment, the memory 7c and the memory 8c are connected to the first embodiment described above through the memory bus control devices 10 and 11. The active system unit 7 according to the second embodiment includes an input / output device 7a and a central processing unit (hereinafter referred to as CPU) 7b connected to a common bus 15a via an interface unit 9 and the CPU 7b via a memory bus 14a. It has a connected memory 7c.

The standby system unit 8 comprises an input / output device 8a and a CPU 8b which are connected to the common bus 15b via the interface section 9, and a memory 8c which is connected to the CPU 8b via a memory bus 14b.

The input / output device 7a / 8a is a device for inputting / outputting data to / from the working system unit 7 / standby system unit 8. The memories 7c / 8c are devices for storing data.

The CPUs 7b / 8b are devices for processing the data input / output to / from the active system unit 7 / standby system unit 8 and controlling the writing / reading of data in the memories 7c / 8c.

Input / output device 7a / 8a in the second embodiment
Is an apparatus for inputting / outputting data to / from the active system unit 7 / standby system unit 8. The memories 7c / 8c are devices for storing data.

The CPUs 7b / 8b are devices for processing data input / output to / from the active system unit 7 / standby system unit 8 and controlling writing / reading of data in the memories 7c / 8c.

The common bus control unit 12 on the working system side has one end via the interface unit 9 and the common bus 15 on the working system side.
The other end is connected to the common bus control device 13 on the standby system side through the confounding path.

As described above, the common bus control device 13 on the backup system side has one end connected to the common bus control device 12 on the working system side via the confounding path and the other end on the backup system side via the interface section 9. It is connected to the common bus 15b.

The common bus controller 12 is the same as that of the first embodiment.
On the other hand, when recognizing the writing of data to the memory 7c, a function of determining whether or not this data should be transferred to the common bus control device 13 on the side of the standby system unit based on the identifier given to the write data. This is a device which, when transferring, sets a confounding path from itself to the common bus control device 13 on the side of the standby system unit and transfers the write data as in the first embodiment.

The common bus control device 13 is a device for copying the data transferred through the confounding path to the memory 8c on the spare side. When the memory bus control device 10 recognizes the data writing to the memory 7c as compared with the first embodiment, the memory bus control device 10 controls the memory bus control on the side of the standby system unit based on the identifier given to the write data. Has a function of determining whether or not to transfer to the device 11,
When transferring, it is a device which sets a confounding path from itself to the memory bus control device 11 on the side of the standby system unit and transfers the write data as in the first embodiment.

The memory bus control device 11 is a device for copying the data transferred through the confounding path to the memory 8c on the spare side. FIG. 5 is a flowchart showing an operation procedure of memory copying of the duplex system in the second embodiment.

In the duplex system according to the second embodiment,
In the active system unit 7, when a data write command is input from the input / output device 7a to the memory 7c (step 501), the write command and data are input to the CPU 7b through the common bus 15a.

The CPU 7b receiving the write command writes the write data in the memory 7c (step 5).
02) At the same time, the memory bus controller 10 and the common bus controller 12 recognize the write command to the memory 7c (steps 503 and 504).

Recognizing the write command, the memory bus control device 10 monitors the memory bus 14a to detect the write data, and also detects an identifier from this data (step 505). Then, based on this identifier, it is determined whether or not the data should be transferred to the memory bus control device 11 on the side of the standby system unit 8 (step 50).
6).

If it is determined that the data is not transferred, the memory bus controller 10 does not operate (that is, the common bus controller 12 is copied to the standby system). If it is determined that the data is to be transferred, a confounding path is set from itself to the memory bus control device 11 on the side of the standby system unit 8 (step 507), and the data is transferred (step 508).

Memory bus control device 1 receiving the data
1 copies the data into the memory 8c of the spare unit 8 (step 509). On the other hand, the common bus control device 12 which has recognized the write command monitors the common bus 15a to detect the write data, and also detects the identifier from the write data (step 510).

Then, based on the identifier, the standby system unit 8
It is determined whether or not the data should be transferred to the common bus control device 13 on the side (step 511). Here, when it is determined that the transfer is not performed, the common bus control device 12 does not operate (that is, the memory bus control device 10 is copied to the standby system).

When it is determined that the data is to be transferred, the common bus control device 12 sets a confounding path from itself to the common bus control device 13 on the standby system side (step 512) and transfers the data.

The common bus control device 13 of the transfer destination transfers the write data to the CPU 8b and gives a copy instruction to the memory 8c (step 514). CPU that received the copy instruction
8c copies the write data to the memory 8c (step 515).

Therefore, according to the second embodiment, it is possible to automatically select whether to copy through the common bus or the memory bus depending on the characteristics of the data to be copied. (Third Embodiment) FIG. 6 is a schematic configuration diagram of a duplex system according to the third embodiment.

The duplex system according to the third embodiment comprises a working system unit 7 and a standby system unit 8 which are connected via a common bus 15 and common bus control devices 12 and 13.

Further, in the third embodiment, the data discriminating devices 16a and 16b are provided in the units of each system as compared with the second embodiment.
The data discriminating device 16a / 16b includes data transferred from the memory bus controller 10/11,
This is a device for comparing the data transferred from the common bus control device 12/13 and copying the data to the memory 7c / 8c when the two match.

The common bus controller 12 is the same as that of the second embodiment.
When the data write to the memory 7c is recognized, the common bus control device 13 on the standby system unit side from itself is recognized.
Is a device for setting a confounding path to and transferring the write data.

The common bus control device 13 is a device for copying the data transferred via the confounding path to the memory 8c on the spare side. The memory bus control device 10 sets a confounding path to the memory bus control device 11 on the standby system unit side from itself when the data write to the memory 7c is recognized, as compared with the second embodiment. A device that transfers data.

The memory bus control device 11 is a device for copying the data transferred through the confounding path to the memory 8c on the spare side. Other configurations are the same as those in the second embodiment.
The description is omitted because it is similar to the above.

FIG. 7 is a flow chart showing an operation process of memory copy of the duplex system in the third embodiment. In the duplex system in the third embodiment, when the data write command is input from the input / output device 7a to the memory 7c in the active system unit 7 (step 70).
1) When the CPU 7b receives the data write command and writes the write data into the memory 7c (step 702), the active memory bus controller 10 and the common bus controller 12 simultaneously recognize the write command. (Steps 703 and 704).

Here, the memory bus control device 10 that has recognized the write command detects the write data by monitoring the memory bus 14a (step 704), and from itself to the memory bus control device 11 on the spare side. To set a confounding path (step 706).

Then, the memory bus control unit 1 on the active system side
0 transfers the write data to the memory bus control device 11 on the spare side through the confounding path (step 70).
6).

The memory bus control device 11 on the spare system side which has received the write data transfers the write data to the data discriminating device 16b on the spare system side. On the other hand, the common bus control device 12, which has recognized the write command of the write data on the active system side, monitors the common bus and detects the write data (step 709).

Then, the common bus control device 12 sets a confounding path from itself to the common bus control device 13 on the standby system side (step 710) and sends the write data to the common bus control device 13 on the standby system side. Transfer (Step 71)
1).

Upon receiving the write data, the common bus control device 13 on the spare side transfers the write data to the data discriminating device 16b (step 712). here,
The data discriminating device 16b which has received the write data from the memory bus control device 11 and the common bus control device 13 compares both data (step 713), and when both data match, the write data is stored in the memory 8c. A copy is made (step 714).

On the other hand, if they do not match, the data discriminator 16b sends an error signal (step 71).
5). Therefore, according to the third embodiment, the write data of the active system can be accurately copied to the standby system.

Further, the data discriminator 16 compares the data transferred from the memory controller 11 with the data transferred from the common bus controller 13, and the data transferred earlier is stored in the memory 8c. It may be arranged to have a function of writing to.

According to this, the processing capacity of the duplex system can be improved.

[0070]

According to the present invention, in a plurality of processing systems connected by a common bus for information transfer, information stored in any processing system is passed to another processing system via a processing device and a memory bus. In the duplication system for copying, the memory information can be copied at high speed and accurately.

[Brief description of drawings]

FIG. 1 is a principle diagram of the present invention.

FIG. 2 is a schematic configuration diagram of a duplex system according to the first embodiment.

FIG. 3 is a flowchart showing an operation process of memory copy according to the first embodiment.

FIG. 4 is a schematic configuration diagram of a duplex system according to a second embodiment.

FIG. 5 is a flowchart showing an operation process of memory copy according to the second embodiment.

FIG. 6 is a schematic configuration diagram of a duplex system according to a third embodiment.

FIG. 7 is a flowchart showing an operation process of memory copy in the third embodiment.

[Explanation of symbols]

 1-First unit 1a-Information processing unit 1b-Information storage unit 1c-Information discriminating device 2-Second unit 2a-Information processing unit 2b-Information storage unit 2c-Information discrimination device 3 ... Common bus control device 4 ... Memory bus control device 5 ... Common bus 6 ... Memory bus 7 ... Active system unit 7a ... Input / output device 7b ... Central processing unit (CPU) 7c ... Memory 8 ..Spare system unit 8a..I / O device 8b..CPU 8c..Memory 9..Interface unit 10..Memory bus control device 11..Memory bus control device 12..Common bus control device 13..Common bus Control device 14 ··· Memory bus 15 · · Common bus 16 · · Data discriminating device

Claims (2)

[Claims] 1. A first and second unit (1, 2) having at least an information processing section (1a, 2a) and an information storage section (1b, 2b) connected thereto, and the first and second units. A common bus (5) for connecting the units (1, 2) and a memory for connecting the information storage unit (1b) of the first unit (1) and the information storage unit (2b) of the second unit (2). A bus (6); and a common bus control device (3) for setting a confounding path between the first and second units (1, 2) on the common bus (5), the common bus control When the device (3) recognizes the information to be written in the information storage unit (1b) in the first unit (1), the common bus control device (3) stores the information in the second unit (2). To the information storage unit (2b) of the second unit (2) Memory copying method characterized by shooting. 2. The first and second units (1, 2)
Is an information discriminating device (1
c, 2c) and the information storage units (1b, 2c) on the memory bus (6).
Memory bus controller (4) for setting the confounding path between b)
When the common bus control device (3) and the memory bus control device (4) recognize the information to be written in the information storage section (1b) in the first unit (1), the common bus control device is provided. (3) and memory bus controller (4)
Respectively transfer the information to the second unit (2), and the information discriminating device (2c) of the second unit (2) is transferred via the common bus (5) and the memory bus (6). The information which arrives first at the second unit (2) is compared with the incoming information and copied to the information storage section (2b) of the second unit (2). Memory copy method.