JPS59112496A - Memory copying system - Google Patents

Abstract

PURPOSE:To obtain a memory copying system which is capable of shortening a copying time by comparing information at the same address of an existing and a stand-by main storage devices, and copying the contents of the main storage device in accordance with a dissidence signal. CONSTITUTION:The existing and the stand-by main storage devices MM0, MM1 are accessed with the same address from an existing central control device CC0, and the read-out data from the device MM0 is stored in a register REG, etc. to compare with the read-out data from the device MML by a comparing circuit CMP. The stored contents of the register REG are written in the device MML in the following processing period only at the time of dissidence by a timing circuit TMG responding to the dissidence signal (ne). Accordingly, copying is not executed at every address, it is executed only when the contents of the devices MM0, MM1 do not coincide with each other, to obtain a memory copying system shortening the copying time.

Description

DETAILED DESCRIPTION OF THE INVENTION (al) Technical Field of the Invention The present invention relates to a memory copying method, particularly to reducing the time required for copying storage contents between main storage devices in an information processing system equipped with a central control unit and a plurality of main storage devices. Concerning memory copying methods.

(bl Background of the Technology As a means to improve the reliability of an information processing system, multiple sets of each central control unit and main memory device are provided, -
A redundant system is widely used in which one set is operated as the active system, the other set is put on standby as a standby system, and if the active system suffers a failure, the standby system immediately starts operating as the active system. In such a duplex system, the storage contents of the backup main storage device must always match the storage contents of the active main storage device. Therefore, for example, it is necessary to copy the entire storage contents of the active main memory to the main memory after the repair of the faulty part has been completed.

(C) Prior Art and Problems FIG. 1 is a diagram showing an example of a conventional memory copying method in this type of information processing system, and FIG. 2 is a diagram showing an example of the operation process in FIG. 1. Figures 1 and 2
In the figure, when the current central controller CCO copies the storage contents of the current main memory MMO to the backup main memory MMI, the current central controller CCO copies the contents of the current main memory MMO to the backup main memory MMI.
O transmits address a and read signal rc to current and backup main memories MMO and MMI.

The active main memory MMO transmits the memory contents of the received address a as successive data rdo to the active central control unit CCO, and the backup main memory MMI transmits the received memory contents of the same address a as successive data rdl. The information is transmitted to the central controller CC1. In the subsequent second cycle T2, the current central control unit CCO writes the read data rdQ from the current main memory MMO in the first cycle T1 to the current and backup main memories MMO and MMI as write data wd together with the address a. Further, the read signal rc is transmitted to the current and backup main memories MMO and MMI. As a result, address a of the spare main memory MMI
The contents stored at the same address a in the current main memory MMO are copied to.

By performing the above operation process for all addresses a, all the storage contents of the current main memory device MMO are copied to the backup main memory device MMI.

As is clear from the above explanation, in the conventional memory copying method, the current and backup main memories MMO and M
The first and second cycles TI and T2 are required for every address a of MI, which has the drawback of increasing the time required for copying. FIG. 3 is a diagram showing another example of a conventional memory copying method that has improved this drawback, and FIG.
It is a figure which shows an example of the operation|movement process in a figure. In FIG. 3, a timing circuit TMG is added.

In Figures 3 and 4, the current central control unit CCO
transmits the address a and the read signal rc to the current and backup main memories MMO and MMI, the subsequent data r read from the corresponding address a of the current main memory MMO
do is transmitted to the active central control unit CCO and also to the timing circuit TMG. timing circuit T
The MG stores the received successive data rdQ in the spare main storage device M.
It is transmitted together with write signal WC as write data wdl for Ml. As a result, the contents stored at the same address a in the active main memory MMO are copied to address a in the spare main memory MM1 within one cycle T3. By performing this operation process for all addresses a, all the contents of the current main memory MMO are copied to the backup main memory MMI. However, in such a memory copying method, the access time Tal for reading the read data rdQ from the active main memory MMO and the access time Ta2 for writing the write data wdl to the backup main memory MMI are one period T3. Therefore, the effect of shortening the copying time is not as great as that shown on the left compared to the memory copying method shown in FIG.

(d+ Purpose of the Invention The purpose of the present invention is to provide a means for eliminating the drawbacks of the conventional memory copying method as described above and reducing the time required to copy the contents of the current main storage device to the backup main storage device as much as possible. It lies in the realization.

(el) Structure of the Invention This object is to provide an information processing system that includes a central control unit and a plurality of main storage devices, and in which the central control device specifies operating modes such as active and standby for each of the main storage devices. The control device is provided with means for comparing data read simultaneously from the same address of the current and backup main storage devices, and when the means detects a mismatch between the two compared data, the control device compares the data read from the current main storage device. This is achieved by writing to the corresponding address in the spare main memory.

(fl　Embodiments of the invention An embodiment of the present invention will be described below with reference to the drawings.

FIG. 5 is a diagram showing a memory copying method according to an embodiment of the present invention, and FIGS. 6(a) and (bl) are diagrams showing an example of the operation process in FIG. Symbols indicate the same objects. In FIG. 5, the timing circuit TMG, the comparison circuit CMP, and the register REG
is provided. The switching unit 1-31 normally connects the control signal bus CB from the currently active central controller CCO to the backup main memory MMI, and the switching unit S2 normally connects the control signal bus CB from the currently active central controller CCO to the write data bus WDB from the currently active central controller CCO. is connected to the spare main memory MMI. Figures 5 and 6
In Figure (al), the current central controller CCO stores the current and backup main memories MMO and
When the address a and the read signal rc are transmitted to the MI, the current main memory device MMO uses the stored contents of the received address a as the subsequent data rdQ of the current central control device CC01 comparison time 1i! %CMP and register REG, and the backup main memory MMI transmits the stored contents of the received address a as subsequent data rdl to the backup central control unit CCI and the comparison circuit CMP. Comparison circuit CMP compares read data rdQ and rdl received from current and backup main memories MMO and MMI, and does not output a mismatch signal r1e if a match is detected between the two. The central controller CCO for realizing this result does not perform any write operation,
A comparison operation (first cycle TI) of read data rdo and rdl from the next address a of the current and backup main memories MMO and MMI is immediately started. Next, in FIGS. 5 and 6 (bl), the current central controller CCO transmits the address a and the successive signal rc to the current and backup main memories MMO and MMI in the first period TI,
The storage contents of the address a received by the active main memory device MMO are transmitted as successive data rdQ to the comparison circuit CMP and register REG of the current central controller CC01, and the storage contents of the address a received by the backup main memory device MM1 are transmitted as successive data. When the comparison circuit CMP compares the read data rdQ and rdl received from the current and backup main memories MMO and MMI and detects a mismatch between them, a mismatch signal ne is transmitted as the data rdl. output, timing circuit T
Convey to MG. The timing circuit TMG that received the mismatch signal ne sends a waiting signal w to the active central control unit CCO.
t, a hold signal hd to the register REG, and a write signal wcl to the switching gate 31.

Upon receiving the waiting signal wt, the current central control unit CCO postpones the read operation for the next address a of the current and backup main memories MMO and MMl for one cycle. Furthermore, the register REG that has received the hold signal hd is stored in the current main memory M
The successive data rdO received from the MO is accumulated and transmitted to the switching device S2 as write data wdl. Next, the timing circuit TMG controls the switching gate S in the second period T2.
A switching signal sw is transmitted to S1 and S2. As a result, the switching gate S1 disconnects the control signal bus CB from the active central controller CCO from the backup main memory MMI, transmits the write signal wcl received from the timing circuit TMG to the backup main memory MMI, and also ) S2 disconnects the write data bus WDB from the active central control unit CCO from the backup main memory device MM1, and transmits the write data wdl transmitted from the register REG to the backup main memory device MMI. As a result, the backup main memory MMI stores the address a that has been transmitted from outside the active central controller CC since the first period TI.
Write data wdl transmitted from the register REG via the switching switch S2 is written to the register REG. As a result, address a of the spare main memory MMI contains the current main memory MMO.
The contents stored at the same address a are copied.

As is clear from the above description, according to this embodiment, the comparison circuit CMP is connected to the current and backup main memories MMO and M.
Read data rdQ read from the same address a of MI
and rdl, and only when a mismatch between the two is detected, a mismatch signal ne is sent and the copying for the corresponding address a is provided. If a match is detected, the copying process is performed without going through the second cycle T2. , immediately compare the read data rdo and rdl from the next address a of the current and backup main memories MMO and MMI (first period TI)
Start. Therefore, if the storage contents of the backup main memory device MMI roughly match the storage contents of the active main storage device MMO, most of the addresses a elapse in only the first period T1, and as shown in FIG. 4 as well as FIG. The overall copying time is also shortened when compared to

Note that FIGS. 5 and 6 (al and mountains) are only one embodiment of the present invention, and for example, the central control unit CCO and the main memory MMO are not limited to the active system, and are Even when the device CC1 and the main storage device MMI are active systems, the effects of the present invention remain unchanged.

(a) Effects of the Invention As described above, according to the present invention, in the information processing system, the time required to copy storage contents between the current and backup main storage devices is reduced overall.

[Brief explanation of drawings]

Figure 1 is a diagram showing an example of a conventional memory copying method;
The figures are diagrams showing an example of the operation process in Figure 1, Figure 3 is a diagram showing another example of the conventional memory copying method, Figure 4 is a diagram showing an example of the operation process in Figure 3, and Figure 5 is a diagram showing an example of the operation process in Figure 3. FIG. 6 is a diagram showing a memory copying method according to an embodiment of the present invention.
al and (bl are diagrams showing an example of the operation process in FIG. 5, FIG. In the figure, CCO and CC1 are the central controller, MM
O and MMI are main memory devices, TMG is a timing circuit, CMP is a comparison circuit, REG is a register, Sl and S
2 is a switching gate, CB is a control signal bus, AB is an address bus, WDB is a write data bus, RDBO and RDBI are read data buses, a is an address, rc is a read signal, wc and wcl are write signals, rdQ and rdl are read data, wd and wd
l is write data, ne is mismatch signal, hd is hold signal,
sw indicates a switching signal, and wt indicates a waiting signal. 2 / Figure 2 Figure 3 Figure 4

Claims (1)

[Claims] In an information processing system comprising a central controller and a plurality of main storage devices, the central controller specifies operating modes such as active and backup for each of the main storage devices, wherein the central controller specifies operation modes such as active and backup main storage. Means for comparing data read simultaneously from the same address of the device is provided, and when the means detects a mismatch between the two compared data, the data read from the current main memory is transferred to the corresponding address of the spare main memory. A memory copying method characterized by writing.