JPS5845116B2 - Duplex storage device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a dual storage device in which a plurality of computers and two shared storage devices are each connected through an interface, and the shared storage device can be accessed from the plurality of computers. The transfer operation is performed to match the stored contents with each other while accessing the data.

Conventionally, in order to realize highly reliable calculation control, a method of duplicating shared storage devices (hereinafter simply referred to as storage devices) has often been adopted.

In order to duplicate storage devices, two storage devices with the same memory content are required, and the accessing computer (hereinafter referred to as C
(abbreviated as PU) not only requires means for writing the same contents into both systems and reading from both systems to check whether the contents match, but also requires the following means.

In other words, when starting up the system, or when the storage device of one system has failed and only the other system is operating, in order to repair the failed system and return to redundant operation, it is necessary to resume normal operation. A means is required to transfer the contents from the storage device that is continuing to the storage device that is to start operation.

There are several conventional methods for this purpose.

One is when changing from single system operation to duplex operation, C
There is a method that completely prohibits access from the PU and performs high-speed transfer under the control of hardware.

Depending on the storage capacity of the storage device, this method takes tens to hundreds of milliseconds for 64 words, for example, so it is not suitable for calculation control that requires online, real-time processing.

According to another method, an interface dedicated to transfer is provided between the duplexed storage devices, and the transfer operation of the storage devices when switching from single-system operation to dual-system operation requires CPU read and write operations. Using behavior.

That is, the transfer is performed by a double write operation in which reading is performed from an address of the storage device that was in operation on one side, for example, address α, and writing is performed using the above-mentioned transfer-only interface to address α of the storage devices on both sides. is running.

In this case, by copying from address O to the maximum address of the installed storage device, the contents of the storage devices of both systems can be completely matched.

The disadvantage of this method is that it requires CPU operation, making the software and programs complex.

In particular, while double writing to address α after reading from address α in the above example, it is not only necessary to disable interrupts, but also if the input/output device is DMA (Direct Memo).
ry Access ), it is necessary to take care not to execute the write operation to the above storage device.

Realizing this with a software program is a major constraint.

Furthermore, according to this method, when multiple CPUs use the storage device, a write operation by a CPU other than the CPU executing this transfer is required between reading from address α and writing to address α. It also requires hardware that prohibits all of the following, making the design extremely difficult.

Furthermore, according to another method, a duplex storage device and a CPU using this storage device are operated synchronously, and C
There is one that performs access to the PU, etc., and transfers memory contents between the two systems.

That is, as shown in FIG. 1, the storage device 2 accessed by the CPU 1 is connected by a CPU-memory interface 6, and the storage device 2 is composed of a memory control unit 3 and duplicated memories 4 and 5. There is.

Therefore, which of the duplicated memories should be transferred is determined by the copy one-direction instruction signal 8 manually transmitted from the outside and the transfer interface 7.
As shown in FIG. 2, the transfer is performed in a time-division manner.

The CPU access acceptance time period A and the transfer operation permission time period B shown in FIG. 2 are created by the memory control unit 3 based on the clock transferred from the CPU 1.

According to this method, the adverse effect on online processing due to the delay in the CPU's access to the storage device is reduced, but it has the following drawbacks.

1. Although the transfer operation between duplex storage devices is only necessary for a few hundred milliseconds at most when starting up the system or when transitioning from single-system operation to dual-system operation, it is constantly transferred from the CPU. Having the access acceptance time zone A and the transfer operation permission time zone B leads to functional deterioration in calculation control.

2. It is difficult to duplicate the memory control unit 3 in FIG.
There are problems with reliability and it is not suitable for highly reliable calculation control.

3. In order to allow multiple CPUs to use the storage device 2, it is necessary to add special hardware.

The present invention was invented in view of the above-mentioned points, and its purpose is to have high responsiveness and high reliability without wasted time, suitable for online, real-time calculation control, and to
An object of the present invention is to provide a dual storage device that facilitates access from a PU.

One object of the present invention is to perform a transcription operation while accepting completely asynchronous accesses from multiple CPUs, with almost no adverse effect on online, real-time processing;
Furthermore, the transfer mode is terminated when the transfer operation is executed for all addresses of the memory contents, and thereafter, a duplex storage device is provided which operates without any time gap even when accessed by a plurality of CPUs. It is in.

One object of the present invention is to provide a dual storage device that does not require support by a software program in a CPU that transfers stored contents.

A feature of the present invention is that a plurality of computers and two storage devices are each connected through an interface, and each of the storage devices can be accessed from the plurality of computers, and at the same time, the two storage devices have the same specifications as the interface. This means that each storage device can be accessed by connecting it with an interface.

One feature of the present invention is that each storage device includes selection means for selecting one of the access activation request signals from a plurality of computers and other storage devices, and one interface corresponding to the output of the selection means. A multiplexer electrically connects the storage device to the own storage unit, and a transfer control circuit that outputs an access activation request to the other storage device and executes a transfer operation.

FIG. 3 shows the overall configuration of the duplex storage device according to the present invention, which includes a CPU 11 t 12 and storage devices 13 and 14.
are interfaces 15°16 and 15', respectively.
The storage devices 13 and 14 are connected by an interface 17.

Here, interfaces 15, 15', 16°16'
and 17 have the same specifications.

An embodiment of the present invention is shown in FIG.

FIG. 4 shows a specific example of the storage devices 13 and 14 in FIG.

Here, since the internal circuits of the storage devices 13 and 14 are exactly the same, only one will be described with reference numerals, and the others will be omitted.

As shown in FIG. 4, the storage device 13 includes a storage section 23 for storing data and a memory control section 19.

The latter further receives activation request signals 26 to 28 from the plurality of CPUs accessing the storage device 13 and the storage device 14.
a selection circuit 20 which selects one of the CPUs or memory devices 14 selected by the selection circuit 20 and responds to each activation request in order for each word transfer; and a data signal line 24 corresponding to the CPU or storage device 14 selected by the selection circuit 20.
25 or 29 electrically to the storage unit 23; and a transfer control unit that outputs an activation request signal to the storage device 14 when the contents of the storage device 13 are transferred to the storage device 14. It is composed of a circuit 21.

Each data signal line 24.degree.25.29 is used to transmit and receive addresses and data to and from the storage device.

Further, the selection circuit 20 accesses the storage device (CP
In order to respond fairly to U and storage devices, in other words, to minimize service waiting time for accessing CPUs and storage devices, an activation request signal is accepted every time a word is transferred. is desirable, and if multiple activation request signals are received at the same time, the C that generated the activation request signal.
It is desirable to transfer the data one word at a time to the PU or the storage device, and when the transfer is completed, to start the operation of accepting the activation request signal again.

Note that when there is no activation request signal, the device does not operate and waits until the signal arrives.

In this way, CPs that access completely asynchronously
Since each word is transferred fairly to the U or storage device, the CPU can also handle online real-time processing with high responsiveness.

Now, to describe in detail the transfer operation between the storage devices 13 and 14 in the above device, in the storage device to be transferred, the activation request signal from the storage device to be transferred is no different from the activation request signal from other CPUs. The selection circuit 20 selects them without distinction, and the multiplexer 22 electrically couples the storage unit 23 with the data signal line 29 between the storage devices 13 and 14 to perform a read operation.

That is, in the storage device to be transferred, there is no difference in operation between access from the CPU and access from the storage device to be transferred.

On the other hand, in the storage device to be transferred, the transfer control circuit 21
starts up and continues the following operations until all the memory contents of the other party's storage device have been transferred.

That is, (1) - For each word transcription, an activation request signal is output to the other party's storage device.

(2) Give the memory address to be transferred sequentially from address 0 to the maximum address of the storage device.

(3) A read operation request is issued to the storage device to be transferred to the other party, and a write operation is performed to the storage device to be transferred to the own system.

(4) CPU before transcription ends for all addresses
It is executed in response to a write operation to the self-system storage device from , but not in response to a read operation.

It has the following functions.

Function (4) is because if it does not respond to a write operation to an address for which transfer has already been completed, there is a risk that the memory contents of both systems will be different.The reason why it does not respond to a read operation is that
This is because the contents of addresses for which transcription has not been completed are meaningless information.

FIG. 5 describes the block diagram of FIG. 4 in more detail.

Each data signal line 24, 25° 29, the interface 30 between the memory control unit and the storage unit has a read/write designation signal line 51, 54° 57.60, and an address and data signal line 53° 56, 59, 62, The access end signal lines 52, 55, 58, and 61 to the storage section are provided.

The selection path 20 includes a priority encoder 63, a decoder 64, and a flip switch that indicates the master/slave system to be described later.
It consists of a flop 65.

The priority encoder 63 receives the activation request signal 26
, 27, and 28 at the same time, it also has a function to individually reset the latched contents corresponding to CPUs or storage devices whose service has ended, and as mentioned above, activation request signals are simultaneously accepted at a certain point, It is desirable to forward the received documents fairly, word by word.

Further, the output of the decoder 64 is connected to the multiplexer 22, and the corresponding data signal lines 24, 25, 29 are connected to the interface 30 between the memory control section and the storage section.

The flip-flop 65 makes one of the storage devices 13 and 14 a master system and the other a slave system.

That is, the main system is a system that selects whether to accept access from the CPU, and the slave system is a system that responds to the selected access signal.

In this example, the one that is operating normally first is the main system.
The system that starts up later is called the subordinate system.

If they start up at the same time, one of them will become the main system, but the details are omitted.

When in the slave system, the output of the concoder 64 is prevented from being outputted by the slave signal 66, so only the main system can select whether to accept access from the CPU.

Note that the selection circuit 20 sends an activation signal 68 to the storage unit 23.
Output.

Therefore, in response to an access from the CPU 11, the activation request signal 27 is first selected by the priority encoder 63 and sent to the multiplexer 22 as a selection signal 67 through the decoder 64, and the data signal line 24 is sent to the multiplexer 22 as a selection signal 67. An interface 30 between the storage unit 23 and the storage unit 23
At the same time, the storage section 23 is activated by the storage section activation signal 68.

Next, an access completion signal 61 from the storage section 23 is also responded through the signal line 52.

Now, the transfer control circuit 21 includes a transfer address counter 69 that sends out an address to be transferred, an end address detection circuit 70 that detects a transfer end address, and a flip-flop 71 that outputs an activation request signal 26 to the storage device 13. .

The method of transfer using this circuit is as follows.

A start request is issued to the storage device 13 by setting the start request signal flip-flop 71 under the AND condition of the signal 72 indicating that the partner system is in a normal operating state and the signal 73 indicating that the own system starts operation. The signal 26 and a read instruction are sent through the signal line 57, and a write instruction is also sent to the self-system storage device 14 through the signal line 74.

When the selection circuit 20 selects this activation request, the data signal line 29 between the storage devices 13 and 14 is connected to the interface between the memory control unit 19 and the storage unit 23, a read operation is performed, and an access end signal is output. 61 is output, it is reported to the storage device 14 through the signal line 58, and the storage device 1
4 starts the write operation.

The transfer address counter 69 counts up by +1 in response to the storage device 14 access completion signal 61.

Furthermore, when the end address detection circuit 70 detects the end of the transfer, it resets the startup request signal flip-flop,
Transfer is completed without outputting the activation request signal 26.

Note that in this embodiment, the storage device 13 is in a waiting state until the write operation of the storage device 14 is completed;
This problem can be resolved by adding a register to store the output data and once withdrawing the activation request signal.

As described above, according to the present invention, it is possible to easily perform transfer operations between dual storage devices while responding in real time to completely asynchronous accesses from multiple CPUs, and the storage devices can always be operated at full capacity. This makes it possible to realize a highly responsive system with no gaps in service time.

Therefore, the present invention can provide a duplex storage device suitable for calculation control requiring online, real-time operation and suitable for a multi-CPU system.

Further, since support by a software program of the CPU is not required for the transfer operation, the CPU can operate without knowing whether the storage device is duplicated or not.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a hardware configuration in an example of the prior art, FIG. 2 is a diagram explaining the operation of the conventional example shown in FIG. 1, and FIG. 3 is a dual storage device of the present invention. FIG. 4 is a block diagram showing the overall hardware configuration of a specific embodiment of the present invention, and FIG. 5 is a block diagram showing the internal configuration of a storage device in a specific embodiment of the present invention. FIG. 2 is a detailed block diagram illustrating the access operation and transfer operation of FIG. 11.12... Calculator, 13,14...
- Shared storage device, 15-17... Interface, 20... Selection circuit, 21... Transfer control circuit, 22... Multiplexer, 23...
...Memory section.

Claims (1)

[Claims] 1. In a duplex storage device in which multiple computers and two shared storage devices are each connected with an interface so that the shared storage devices can be accessed from each of the multiple computers, the two shared storage devices are configured with the same specifications as the interfaces. The configuration is connected with the interface of
Further, in the shared storage device, there is a selection means for selecting one of the access activation request signals from the plurality of computers and the other storage devices, and a corresponding one interface is electrically connected to the local storage section by the output of the selection means. What is claimed is: 1. A duplex storage device comprising: a multiplexer that is connected to the storage device; and a transfer control circuit that outputs an access activation request to another storage device and executes a transfer operation.