JPS6326903B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a memory system in which two memory devices are accessed by a plurality of computers.

Two global memories (hereinafter referred to as GM)
In a memory system that connects multiple computers to a computer and shares data between them,
In order to increase reliability, if a shared GM was to be duplicated, the entire address space had to be duplicated.

However, the important data that must be duplicated is a small portion of the total capacity of the GM, and there was a problem that the memory was not used effectively.

Also, when debugging a newly created program, it is necessary to use one GM at full duplex because it will have a negative effect on the program running online.
The problem was that it had to be made to operate offline, which reduced reliability.

Furthermore, since the control information for the input/output devices used by the two computers is stored on the GM, there is a problem that the input/output devices used online cannot be used for debugging.

An object of the present invention is to enable duplication of only a specific portion of the entire address space of the GM, thereby making it possible to use memory effectively, without reducing reliability even during program debugging, and to provide online support. An object of the present invention is to provide a memory system in which control information of input/output devices used can be accessed.

In order to achieve such an object, the present invention provides register means for holding the same address in two memory devices, and divides each memory device into two areas according to this address.
The feature is that in one area, only one specified memory device processes the access, and in the other area, both memory devices process the access.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 shows the configuration of an example of a memory system according to the present invention, and shows an example of duplicated GMs and three computers that access them.

In FIG. 1, 1 and 2 are GMs, 3 to 5 are computers, 6 and 7 are memories, 8 to 13 are access control signals from each computer, 14 is a signal between GMs 1 and 2, and 15 and 16 are memories. The fence register that divides the address space of 6 and 7 into two is shown.

Memories 6 and 7 of GMs 1 and 2 are divided into two by fence registers 15 and 16, and addresses smaller than the contents of fence registers 15 and 16 serve as a dual area DL, and addresses larger than that serve as a single area.
They are S ₁ and S ₂ . Computers (hereinafter referred to as CPUs) 3 to 5 transmit access requests to GMs 1 and 2 using signals 8 to 13.

Access requests from CPUs 3 to 5 are as shown in Figure 2a.
As shown in the figure, the access function, address, and write data for mode R/W, which indicates whether to read or write, and mode M/R, which indicates whether to access the memory or register in GM. (Valid only when writing) In addition, the access mode S ₁ /S ₂ indicates whether the request is to access the GM specified in S ₁ or the GM specified in S ₂ . There is. These access requests are sent to GM1 and GM2 simultaneously.

Access requests sent in this way will be sent to the GM
It is compared with the operating modes in 1 and 2, and the memory or register in the GM is accessed depending on the result.

GM operation modes are divided into operation mode, area designation, and master/slave designation indicating whether to take the lead in access processing.

Among these, the operation mode refers to the following four states.

(1) Power off: Refers to a state where the power is cut off.

(2) Local: Refers to a state where memory access is not possible. However, register access is possible.

(3) Copy: Copy the memory of the redundant area DL to both GMs.
This refers to a state in which data is copied from the master GM to the own GM so that the values are the same.

(4) On-service: A state in which memory access can be performed and data is not copied to the own GM.

In addition, area specification means fence register 1
It distinguishes the address part above the contents of 5 and 16, and takes either the single area S ₁ or S ₂ . (You can set either GM1 or GM2 as _S1 , but
In Figure 1, GM1 is designated as _S1 . ) Figure 3 shows the relationship between these operating modes and the memory areas that can be accessed by the CPU.

In FIG. 3, the portions marked with a circle are accessible, and the portions marked with an x are inaccessible.

Now, both GMs are thinking about the on-service status. However, GM1 is the master GM and GM2 is the slave GM.

Here, when accessing single area S ₁ of memory 6 of GM 1, CPU 1 requests access to GM 1 and ₂ in access mode S 1 and at an address with a value larger than the contents of fence registers 15 and 16. are sent out as signals 8 and 11.

After accepting this access request, GM1
On the _other hand, GM2 does not perform access processing because its own system is not in area _S1 .

Also, when accessing the redundant area DL,
An access request is issued in the same way as the access to the single area _S1 , but the only difference is that the address has a smaller value than the contents of the fence registers 15 and 16.

Therefore, the CPUs 3 to 5 can access the duplex area DL and the single areas S ₁ and S ₂ without being aware of them. Then, this access request is made by the master GM
1, and then performs access processing for the duplex area DL and notifies the slave system GM2 that it is an access to the duplex area.
The slave GM 2 does not attempt to perform the duplex access process itself, but performs the duplex area DL access process based on the information sent from the master GM.

Furthermore, only write access to the duplex area DL is accepted for GMs that are in service mode. The reason read data is not accepted in this mode is because copying is in progress, so read data is not accepted by the master system.
This is because it may not be the same as GM.

Next, we will explain how to use GM when debugging a program. In addition, CPU4 is a slave system.
Consider the case of program debugging using GM2.

During online operation, both GMs operate online, the fence register is set to the maximum address of the installed memory, and all memory areas are often duplicated. However, even at this time, the area has been designated, and the designation is simply not valid.

Here, by register access of CPU4,
Set the contents of the fence register to an address smaller than the memory area used by the program being debugged. As a result, the area specification of S ₁ and S ₂ becomes valid, and online GM1 is accessed by online CPUs 3 and 5 in S ₁ access mode, and GM2 for program debugging is accessed in S ₂ access mode. It can be done.

In this way, online data at the same address as the area used by CPU4 can only be accessed in _S1 access mode, so it is
CPU4 does not adversely affect online CPUs3 and 5.

Furthermore, since the control information for the input/output device is included in areas S ₁ and S ₂ , it can be accessed even in the S ₂ access mode, and the input/output device can be used from the CPU 4 for debugging.

Next, a device that implements the above-mentioned functions will be explained.

FIG. 4 shows an embodiment of the overall configuration of the memory system according to the present invention, and shows the GM1 portion. In FIG. 4, 17 is a memory control circuit (MCV), 18 is an access request selection circuit, 19 is a register group and its control circuit, and 20 to 22 are each
A request receiving circuit (CPUP) from the CPU, 23 a copy control circuit (CPYP), and 24 to 31 signals.
Note that the signals 26 and 27 correspond to the signal 14 in FIG.

Figure 5 shows the register group in Figure 4 and its control circuit 1.
9 details are shown. In the figure, 191 is a register write control circuit, 192 is a fence register (FFNCE) (corresponding to 15 in Figure 1), 193 is an area specification register (AREA), 194 is a mode register (MOD), and 195 is write data. The conversion circuit 196 is an OR gate.

Figure 6 shows the request reception circuit 2 from CPUs 3 to 5.
This shows the details of 0 to 22, and the request reception circuit 20
Here is an example. In FIG. 6, 201 is a comparator (CMP), and 202 is a programmable logic array (Programmable Logic Array).
It's called PLA. ), 203 is an and gate, 204
is a delay line, and 205 to 207 are three-state gates.

FIG. 7 shows an outline of the CPU 3. 301 is an arithmetic processing unit, 302 is an address conversion and access request sending circuit, 303 is a response reception circuit from GM, 3
04 is a selector, 305 is a control circuit for the selector 304, and 306 is a 3-state gate. Also,
In the response reception circuit 303, 307 to 309 are AND gates, and 300 is an OR gate.

FIG. 8 shows details of the copy control circuit 23.
231 is a one-shot multivibrator (OS), 232 is a flip-flop (flag), 2
33 is the counter (CPYADDR), 234 is PLA,
235 is a comparator (CMP), 236 to 239
indicates a 3-state gate.

First, processing of an access request from the CPU 3 will be explained using FIGS. 4 to 7. CPU3
An access request to the GM from the arithmetic processing unit 301 in the control circuit 302 is sent at the logical address 401.
can be conveyed to. Here, while exchanging the logical address 401 to physical addresses 802 and 112,
An access request 801, 111 is output to the GM with an access mode 803, 113 indicating which area is to be accessed. This request is
The request reception circuit 20 of GM1 and the request reception circuit of GM2 are transmitted. The operation in GM1 will be explained below.

Address 802 from CPU3 is register group 1
9 and the result is output to PLA 202. On the other hand, the access request signal 801 is
The signal is applied to the AND gate 203 via a delay line 204 having a delay time equal to the delay caused by 02. The other input of the AND gate 203 is
The output from PLA202 is added, and the self-system
When the request is not to the GM1, this output is not output, and the access request signal 281 to the access request selection circuit 18 inside the GM1 is not output. This control is performed as follows. The access mode and access function from the CPU 3 (indicates whether the register access is a memory access, read or write) 803, the output of the comparator 201, and the output 242 of the area specification register 193 of the register group 19 and mode register 1
The output 243 of 95 is controlled to satisfy the combination of the area shown in FIG. 3 and the accessible GM operation mode. Further, along with the access request signal 281, a signal 282 indicating whether this request is for a duplex area or not is output. Since this signal 282 is not duplicated unless the GM of the other system is on service or copying, this signal is not issued even if the address to be accessed is within the duplex area. It is also not output when reading in copy mode.
Note that the same signal as signal 282 is signal 80 indicating whether a response to the CPU is returned from both GMs.
Also used as 5.

The access request selection circuit 18 that has received the request signal 281 and the signal 282 sends a signal 283 indicating that the request reception circuit 20 has been selected. As a result, access function 251, address 2
52. At the time of writing, write data 253 is outputted to the common bus via gates 205, 206, and 207. Further, if the access request selected by the access request selection circuit 18 is an access request for a duplex area, the selection signal 28 of the request reception circuit 20
At the same time as outputting the signal 3, the slave GM 2 is also notified by a signal 26 that the duplex area access request from the circuit 20 has been accepted. During this time, the slave system access request selection circuit 18 selects only the access request for the single area and does not select the access request for the duplex area. Then, it is informed by the master system GM1 that a request to access the duplex area has been received, and selects the request receiving circuit. The reason why the master GM selects the selection when accessing the duplex area and transmits the result to the slave GM is to synchronize and access the same data. If you do not do this, if CPUs 3 to 5 request access to the duplex area with the same address, GM1 will process the access in the order of CPUs 3, 4, and 5, and GM2 will process the access in the order of CPUs 3, 5, and 4. This is because there is a risk of processing.

Next, the memory control circuit 17 or write control circuit 191 sends a signal 2 indicating the end of access.
54 is sent to the request reception circuit 20, it is further transmitted to the CPU 3 as a signal 806.

The CPU 3 receives the end signal 806 from the GM 1 and waits for the end signal 116 from the other GM 2. When a response is sent from both GMs, the end of access is communicated to the arithmetic processing unit 301 via the AND gate 309 and the OR gate 300. If,
Even if you only get a response from one GM,
Signal 80 indicating that only a response will be returned
If 5 or 115 is output, it is notified through AND gate 307 or 308 and OR gate 300, and the access is terminated. Further, in the case of read access, read data 807 or 117 is sent. As shown in Figure 2b, error information is also added to this read data, so the control circuit (CC) 305 determines which one to use based on this error information and the signals 805 and 115 that notify the response from the single GM. A signal for determining whether to select GM data is output, and the selector (SEL) 304 selects it.

This completes the processing for the access request from the CPU. Next, the copy operation will be explained with reference to FIGS. 4 to 8.

Copy control is also handled in the same way as access from the request reception circuit. The mode register 195 of the register group 19 can be changed by rewriting the mode register 195 or
New data is set when the fence register is rewritten. When setting the fence register 192, if the current mode is both systems on service, a new mode is generated in the write data conversion circuit 194 so that the mode of the slave system GM becomes copy, and it is set in the mode register 195. Ru.

When the copy mode is entered, the one-shot multivibrator (corresponding to 231 of GM1) of the copy control circuit (corresponding to 23 of GM1) in the slave system GM2 sets a flag indicating that copying is in progress (corresponding to 23 of GM1).
232) is set. At the same time, the counter that generates the copy address (corresponding to 233 in GM1) is cleared.

By setting the flag indicating that copying is in progress, the copy address (GM
1) is the gate (equivalent to 236 of GM1)
is output through.

In addition, the copy control circuit 23 of the master system GM1 is transferred from the PLA of the slave system GM2 (corresponding to 234 of GM1).
Outputs a read access request signal to.

The copy control circuit 23 of the master GM 1 receives this request signal 273 and outputs an access request signal 311 to the access request selection circuit 18.
At this time, a signal 312 indicating which area is being accessed is also output at the same time. This signal has the same meaning as the signal 282 of the request reception circuit 20.

Next, when a signal 313 indicating that the copy control circuit 23 has been selected is sent, the address 252 and access function 2 indicating that the memory read is to be sent are sent via gates 237 and 238.
51 is output. When the data in the memory 6 is read, a response signal 254 and read data 255 are returned from the memory control unit 17 to notify the end. This read data 255 is slave system
This is the write data (corresponding to 276 of GM1) for the GM copy control circuit (corresponding to 23 of GM1).
Further, the response signal 254 is a write access request signal 2 for the copy control circuit of the slave GM 2.
It will be 71.

As a result, the copy control circuit of slave GM2 sends an access request signal (corresponding to 311 of GM1) to the access request selection circuit (corresponding to 18 of GM1).
convey.

Then, when the copy control circuit of the slave system GM2 is selected, the read data from the master system GM1 is used as write data and the slave system memory (GM
(equivalent to 6 in 1). When the response signal (corresponding to 254 of GM1) returns to the copy control circuit,
A signal that counts up the copy address using PLA (equivalent to 234 on GM1) (equivalent to 421 on GM1)
is output and the address for the next access is the copy address counter (corresponding to 233 of GM1)
is generated. The above-described process is repeated based on this address. Here, the contents of the copy address counter (corresponding to 233 of GM1) are copied from the address (corresponding to 192 of GM1) from the fence register (corresponding to 192 of GM1).
241), the flag indicating that copying is in progress (corresponding to 232 of GM1) is reset, and the copying ends.

As can be seen from the embodiments described above, according to the present invention, a memory device in which only particularly important parts are duplicated can be obtained, so that the memory can be used effectively and there is no need to have extra memory.

In addition, the partially duplexed memory device makes it possible to access the control information of the input/output devices used online even when debugging a program, allowing the input/output devices to be shared, Reliability can be improved by making only one area a single area and the other areas a duplicate area.

[Brief explanation of the drawing]

Figure 1 is a diagram showing an overview of the memory system according to the present invention, Figure 2 is a diagram showing the configuration of the interface signals in Figure 1, and Figure 3 is a diagram showing the GM operation mode in Figure 1.
Diagram showing the relationship with the CPU access mode, 4th
The figure is a block diagram of one embodiment of the memory system according to the present invention, and FIGS. 5, 6, 7, and 8 show specific details of the register group, request reception circuit, CPU, and copy control circuit shown in FIG. It is a figure showing an example of composition. 1, 2...GM, 3~5...CPU, 6,7...
Memory, 15, 16...Fence register.

Claims (1)

[Claims] 1. It has two memory devices in which at least some of the memory areas are duplicated, and a plurality of computers are connected to the two memory devices, and each computer can simultaneously use two memory devices. In a memory system configured to perform memory access to a device, register means holds, in each memory device, the same address that divides the memory area of the memory device into two areas, a duplex area and a single area;
It has a determination means that compares the address from the computer and the address of the register to determine which area is being accessed, and each computer selects one of the two memory devices when accessing a single area. It has means for outputting an access mode that specifies which memory device the memory access is to be made, and in each memory device, when accessing a single area as a result of address comparison, the access mode is determined by the specified access mode. 1. A memory system characterized in that only one memory device processes access, and when an access to a duplex area is accessed, two memory devices process the access. 2. The memory device according to claim 1 includes:
When accessing memory to a duplex area, one of the memory devices performs the access process first, and the memory device that performed the access process transfers this result to the other memory device, thereby duplicating the two memory devices. A memory system characterized by comprising a copying means for matching contents of areas.