JPH05120060A - Fault data extraction system - Google Patents

Abstract

PURPOSE:To extract fault data from a memory without using a processor. CONSTITUTION:A system consists of the memory 150 storing fault data, the processor 110 reading the memory 150, an address counter 120 addressing the memory 150, a diagnosis processor 200, a driver 130 transmitting the output of the memory 150 to the diagnosis processor 200 and a selector 140 switching the reading of the memory 150 to the processor 110, the address counter 120 and the driver 130 by an instruction from the diagnosis processor 200. Thus, fault data can be extracted even if there is the fault of the processor and data transfer does not normally operate owing to the bug and the bug of firmware.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a fault data collection system.

[0002]

2. Description of the Related Art In a conventional fault data collection method, a processor reads fault data from a memory and transfers the fault data to a main storage device through a data transfer control circuit.

[0003]

In this conventional fault data collection method, since the memory in which fault data is stored can only be read by the processor, there is a bug in the firmware fault process or data transfer process. However, there is a problem that the fault data stored in the memory cannot be collected when the processor is defective or defective.

[0004]

The system of the present invention is a fault data collection system in an information processing apparatus having a diagnostic processing unit and a control unit for performing various controls, and a processor controlled by firmware in the control unit. And a memory storing fault data, an address counter for designating an address of the memory by starting a dump from the diagnostic processing device, and enabling a fault data by the dump starting from the diagnostic processing device to diagnose the fault data. A dump output from the diagnostic processing unit determines whether the driver outputs to the processing unit and whether to output the memory from the processor to the processor or whether to output the memory from the address counter to the driver. It is characterized in that a selector for switching is provided.

[0005]

The present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of an information processing apparatus according to an embodiment of the present invention.

In FIG. 1, 100 is a control device for performing various controls, 110 is a processor, 120 is an address counter, 130 is a driver, 140 is a selector, 150 is a memory, 160 is a data transfer control circuit, and 200 is a diagnostic processing device ( Hereinafter, referred to as DGU), 300 is a main memory (hereinafter referred to as MMU), 111 is an address signal line of the memory 150 output from the processor 100, 121 is an address signal line of the memory 150 output from the address counter 120, 131 From driver 130 to DGU2
00 is a signal line for outputting data, 141 is an address signal line for the selector 140 to output the address data of the signal line 121 or the signal line 111, and 142 is a memory 150 of the address output to the signal line 121.
Signal line for outputting the data of the above from the selector 140 to the buffer 130, 143 indicates that the processor 110 stores in the memory 15
0 and a data signal line for transferring data to be accessed,
151 is a data signal line of the memory 150 of the address output to the signal line 141, 201 is a dump start signal of the memory 150 output from the DGU 200, and 112 is a signal for the processor 110 to set the data of the memory 150 to the data transfer control circuit. A line, 161 is a signal line for transferring data from the data transfer control circuit to the MMU 300, and 202 is an interface signal line between the DGU 200 and the MMU 300.

Next, the operation of this embodiment will be described.

First, when a failure occurs in the control device 100, the selector 140 normally operates on the address signal line 141.
Since the signal line 111 is selected for the processor 11 and the signal line 143 is selected for the data signal line 151, the processor 11
0 outputs the target address of the memory 150 to the address signal line 111, and reads the fault data of the memory 150 from the data signal line 143.

Next, the processor 110 sets the read fault data transfer control circuit 160, and the data transfer control circuit 160 outputs the fault data to the signal line 161 and writes it to the MMU 300.

The DGU 200 determines whether the fault data from the controller 100 has been normally transferred to the MMU 300 through the interface signal line 202. DGU
200 is a dump start signal 201 when failure data transfer from the control device 100 to the MMU 300 is not successful.
To activate.

When the dump start signal 201 becomes active, the selector 140 selects the address signal line 121 and the data signal line 142.
Cannot access the memory 150. The address counter 120 outputs the address information to the address signal line 121 while sequentially counting up the address information.

The memory 150 has address signal lines 141.
The data of the address output to the data signal line 15
Output to 1. The selector 140 uses the data signal line 15
The fault data of 1 is output to the data signal line 142.
The driver 130 outputs the fault data of the data signal line 142 to the signal line 131 because it is enabled when the dump start signal line 201 is active. D
The GU 200 takes in the fault data stored in the memory 150 from the signal line 131.

[0014]

As described above, the present invention has the effect that the fault data can be collected regardless of the malfunction of the firmware or the processor because the processor can not be used to read the fault data from the memory.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

[Explanation of symbols]

 100 control device 110 processor 120 address counter 130 driver 140 selector 150 memory 160 data transfer control circuit 200 diagnostic processing device

Claims (1)

[Claims] 1. A fault data collection method in an information processing device comprising a diagnostic processing device and a control device for performing various controls, wherein a processor controlled by firmware and a memory storing fault data in the control device. An address counter for designating an address of the memory by a dump start from the diagnostic processing device, a driver which is enabled by the dump start from the diagnostic processing device and outputs fault data to the diagnostic processing device, and the memory Is provided from the processor to be output to the processor or the memory is addressed from the address counter to be output to the driver by a dump start from the diagnostic processing device. Failure data collection method