JPH04373047A - Memory diagnostic system - Google Patents

Abstract

PURPOSE:To shorten memory diagnostic time by successively transferring data first written in a memory block to the final memory block. CONSTITUTION:A storing means is provided with an N pieces of memory blocks 3, 4... 5, a processor 1 is provided to enable write and read to the storing means, a diagnosis instruction register 6 is provided to be written by the processor, a data bus 2 is provided to connect the N pieces of memory blocks and the processor, a data bus disconnecting means 7 is provided to suppress outputs from the processor to the data bus in the case of writing from the processor to the memory blocks when the diagnosis instruction register is set, and a memory block output control means 8 is provided to instruct it to the memory block to output data to the data bus.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory diagnostic method, and more particularly to a method for diagnosing a memory distributed over a plurality of storage blocks.

0002

2. Description of the Related Art Conventionally, this type of memory diagnostic method requires a processor to write to all blocks in a storage section, and then read and compare all blocks.

0003

SUMMARY OF THE INVENTION The conventional memory diagnosis method described above has a problem in that the diagnosis time is long.

0004

[Means for Solving the Problems] A memory diagnostic method of the present invention includes: a storage means having N storage blocks; a processor capable of writing to and reading from the storage means;
a diagnostic instruction register writable by the processor;
a data bus connecting the memory blocks and the processor; and data bus disconnection means for suppressing output of the processor from being output to the data bus during a memory block write operation of the processor when the diagnostic instruction register is in a set state; The apparatus is characterized by comprising a memory block output control means for instructing the memory block to output data to the data bus.

[0005]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention, which includes a processor 1 and a plurality of storage blocks 3 and 4.
...5, the data bus 2, the diagnostic instruction register 6, the data bus disconnection means 7, and the memory block output control means 8.
It is composed of. When diagnosing memory blocks 3, 4, . . . , processor 1 first writes data to memory block 3. Then, when the diagnostic instruction register 6 is set, the processor 1 is disconnected from the data bus 2 by the data bus disconnection means 7. In this state, when the processor 1 instructs the memory block 4 to perform a write operation,
An output control signal 9 is set in the memory block 3 by the memory block output control means 8, and the contents of the corresponding address of the memory block 3 are output onto the data bus 2. Only the data output to the data bus 2 has changed from the data of the processor 1 to the data of the memory block 3, and the other operations are the same as when the diagnostic register 6 is not set. The data already written in block 3 is written.

With the diagnostic instruction register 6 set in this way, when an instruction is given to write data into the memory block M, since the data of the memory block (M-1) is output on the data bus 2, the memory block Data (M-1) is written to storage block M.

[0008] Therefore, processor 1 stores memory blocks 3 and 4.
. . . When the write operation instruction is repeated up to 5, the contents of memory block 3 are transferred to memory block 5 one after another.

After resetting the diagnostic instruction register 6, the processor 1 reads the value in the memory block 5 and compares it with the value written in the memory block 3. If they all match, it means that there is no failure in all the memory blocks.

0010

Effects of the Invention As explained above, the present invention has a structure in which the data in the first memory block written is sequentially transferred to the last memory block, so that the contents of the last memory block are the same as those in the first memory block. Since the entire area of the memory block has been diagnosed just by confirming that the content matches the content written in the block, the time required for diagnosing the memory unit can be halved compared to conventional technology if the number of partitions of the memory block is large. There is.

[Brief explanation of drawings]

FIG. 1 is a block diagram of one embodiment of the present invention.

[Explanation of symbols]

1 Processor 2 Data bus 3, 4, 5 Memory block 6 Diagnosis instruction register 7 Data bus disconnection means 8. Memory block output control means 9,10 Output control signal 11 Address signal

Claims (1)

[Claims] 1. A storage unit having N storage blocks, a processor capable of writing to and reading from the storage unit, a diagnostic instruction register writable by the processor, and connecting the N storage blocks and the processor. a data bus for controlling the memory block; a data bus disconnection means for suppressing output of the processor from being output to the data bus during a memory block write operation of the processor when the diagnostic instruction register is in the set state; 1. A memory diagnostic method comprising: storage block output control means for instructing to output data.