JP2888062B2 - Information processing device - Google Patents
Information processing deviceInfo
- Publication number
- JP2888062B2 JP2888062B2 JP4297548A JP29754892A JP2888062B2 JP 2888062 B2 JP2888062 B2 JP 2888062B2 JP 4297548 A JP4297548 A JP 4297548A JP 29754892 A JP29754892 A JP 29754892A JP 2888062 B2 JP2888062 B2 JP 2888062B2
- Authority
- JP
- Japan
- Prior art keywords
- main storage
- storage device
- bus
- write operation
- central control
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Landscapes
- Hardware Redundancy (AREA)
- Multi Processors (AREA)
Description
【0001】[0001]
【産業上の利用分野】本発明は中央制御処理装置と主記
憶装置とが2重化構成された情報処理装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing apparatus in which a central processing unit and a main storage unit are duplicated.
【0002】[0002]
【従来の技術】図1は一般的な情報処理装置の一例を示
すブロック図である。図1に示すように本例の情報処理
装置は、自系中央制御処理装置10と、自系主記憶装置
20と、自系中央制御処理装置10と自系主記憶装置2
0とを接続してデータの読出し動作/書込み動作を行う
バス30と、自系中央制御処理装置10と他系主記憶装
置21とを接続してデータの読出し動作/書込み動作を
行うバス40と、自系中央制御処理装置10から他系主
記憶装置21への書込み時にのみ使用する書込み専用バ
ス50と、他系中央制御処理装置11と、他系主記憶装
置21と、他系中央制御処理装置11と他系主記憶装置
21とを接続してデータの読出し動作/書込み動作を行
うバス31と、他系中央制御処理装置11と自系主記憶
装置20とを接続してデータの読出し/書込み動作を行
うバス41と、他系中央制御処理装置11から自系主記
憶装置20への書込み時にのみ使用する書込み専用バス
51とで構成されている。2. Description of the Related Art FIG. 1 is a block diagram showing an example of a general information processing apparatus. As shown in FIG. 1, the information processing apparatus of the present embodiment includes an own system central control processing device 10, an own system main storage device 20, an own system central control processing device 10, and an own system main storage device 2.
0, which performs data read / write operation by connecting data to 0, and bus 40, which performs data read / write operation by connecting the own system central control processor 10 and the other system main storage device 21. A write-only bus 50 used only when writing from the own system central control processing device 10 to the other system main storage device 21; the other system central control processing device 11; the other system main storage device 21; A bus 31 for performing a data read / write operation by connecting the device 11 and the other system main storage device 21 and a data read / write operation by connecting the other system central control processing device 11 and the own system main storage device 20 It is composed of a bus 41 for performing a write operation, and a write-only bus 51 used only when writing from the other-system central control processing device 11 to the own-system main storage device 20.
【0003】図3は図1における従来の動作手順を説明
するための図である。図1に示す構成において、自系主
記憶装置20と他系主記憶装置21のデータが異なる非
同期モード時に、自系中央制御処理装置10と他系主記
憶装置21とのデータの読出し動作/書込み動作手順が
「読出し動作61→初めの書込み動作71→次の書込み
動作72」の順序で行われるときに、自系中央制御処理
装置10と他系主記憶装置21間のデータの読出し動作
/書込み動作を行うバス40を読出し動作専用のバスと
して使用し、自系中央制御処理装置10から他系主記憶
装置21への書込み時にのみ使用する書込み専用バス5
0を書込み動作専用のバスとして使用していた。FIG. 3 is a diagram for explaining a conventional operation procedure in FIG. In the configuration shown in FIG. 1, in the asynchronous mode in which the data of the own system main storage device 20 and the data of the other system main storage device 21 are different, the data read operation / write operation between the own system central control processing device 10 and the other system main storage device 21 is performed. When the operation procedure is performed in the order of “read operation 61 → first write operation 71 → next write operation 72”, data read operation / write between the own system central control processing device 10 and the other system main storage device 21 is performed. An operation bus 40 is used as a bus dedicated to a read operation, and a write-only bus 5 used only when writing from the own system central control processing device 10 to the other system main storage device 21.
0 was used as a bus dedicated to a write operation.
【0004】そのため、図3に示すように、初めの書込
み動作71→次の書込み動作72の動作順序の時に、初
めの書込み動作71が終了しないと次の書込み動作72
に移ることができなかった。Therefore, as shown in FIG. 3, in the order of the first write operation 71 → the next write operation 72, if the first write operation 71 is not completed, the next write operation 72 is performed.
Could not move to.
【0005】[0005]
【発明が解決しようとする課題】この従来の2重化構成
された情報処理装置では、自系主記憶装置と他系主記憶
装置のデータが異なる非同期モード時の自系中央制御処
理装置から他系主記憶装置への連続書込み動作において
は、初めの書込み動作が終了しないと次の書込み動作に
移ることができないので、処理能力が低下するという問
題点があった。In this conventional information processing apparatus having a duplex configuration, the data of the own main memory and the data of the other main memory are different from each other in the asynchronous mode in the asynchronous mode. In the continuous write operation to the system main storage device, it is not possible to proceed to the next write operation unless the first write operation is completed.
【0006】[0006]
【課題を解決するための手段】本発明の情報処理装置
は、2重化構成になっている自系,他系中央制御処理装
置および自系,他系主記憶装置と、前記自系中央制御処
理装置が前記自系主記憶装置と接続されてデータの読出
し動作/書込み動作を行う第1のバスと、前記自系中央
制御処理装置が前記他系主記憶装置とデータ読出し動作
/書込み動作を行う第2のバスと、前記自系中央制御処
理装置から前記他系主記憶装置へのデータの書込み動作
時にのみ使用する書込み専用バスとを有する情報処理装
置において、両系の前記主記憶装置の一致しない非同期
モード時に前記自系中央制御処理装置と前記他系主記憶
装置との間の動作手順が読出し動作→書込み動作→書込
み動作の順に行われたとき、前記第2のバス→前記書込
み専用バス→前記第2のバスの順序で使用することを特
徴とする。An information processing apparatus according to the present invention comprises: a self-system, another-system central control processor and a self-system, other-system main storage device having a duplex configuration; A first bus which is connected to the own main memory to perform a data read / write operation, and wherein the own central control processor performs a data read / write operation with the other main memory; An information processing apparatus having a second bus to be performed and a write-only bus used only when data is written from the self-system central control processing device to the other-system main storage device. When the operation procedure between the self-system central control processing device and the other-system main storage device is performed in the order of read operation → write operation → write operation in the asynchronous mode in which they do not match, the second bus → the write only Bus → No. Characterized by the use in sequence of the bus.
【0007】[0007]
【実施例】次に、本発明について図面を参照して説明す
る。図1において、本発明の実施例の2重化構成された
情報処理装置では、自系中央制御処理装置10は自系主
記憶装置20との間はデータの読出し動作/書込み動作
を行うバス30で接続されるとともに、クロック同期し
ていない他系主記憶装置21との間はデータの読出し動
作/書込み動作を行うバス40で接続され、また書込み
専用バス50は自系中央制御処理装置10から他系主記
憶装置21へのライト時にのみ使用される。Next, the present invention will be described with reference to the drawings. Referring to FIG. 1, in an information processing apparatus having a duplex configuration according to an embodiment of the present invention, a local central processing unit 10 performs a data read / write operation between itself and a local main storage device 20 via a bus 30. And a bus 40 for performing a data read / write operation with the other system main storage device 21 which is not clock-synchronized. It is used only when writing to the other system main storage device 21.
【0008】続いて本実施例の動作について図2を併用
して説明する。図2は図1における本発明の一実施例の
動作手順を説明するための図である。Next, the operation of this embodiment will be described with reference to FIG. FIG. 2 is a diagram for explaining the operation procedure of one embodiment of the present invention in FIG.
【0009】図1に示す構成において、自系主記憶装置
20と他系主記憶装置21のデータが異なる非同期モー
ド時に、自系中央制御処理装置10と他系主記憶装置2
1を接続してデータの読出し動作/書込み動作を行うバ
ス40を読出し動作専用ではなく書込み動作も行うバス
として使用する。In the configuration shown in FIG. 1, in the asynchronous mode in which the data of the main system main storage device 20 and the data of the other system main storage device 21 are different, the main system central control processing device 10 and the other system main storage device 2
1 is used as a bus for performing a data read / write operation and a write operation as well as a read operation.
【0010】そして、自系中央制御処理装置10と他系
主記憶装置21間のデータ読出し動作/書込み動作を
「読出し動作62→初めの書込み動作73→次の書込み
動作74」の順序で行うときに、自系中央制御処理装置
10と他系主記憶装置21とを接続してデータの読出し
動作/書込み動作を行うバス40→自系中央制御処理装
置10から他系主記憶装置21への書込み時にのみ使用
する書込み専用バス50→自系中央制御処理装置10と
他系主記憶装置21とを接続してデータの読出し動作/
書込み動作を行うバス40の順序で使用する。When the data read operation / write operation between the own system central control processor 10 and the other system main storage device 21 is performed in the order of "read operation 62 → first write operation 73 → next write operation 74". A bus 40 for connecting the own system central control processing device 10 and the other system main storage device 21 to perform a data read / write operation → writing from the own system central control processing device 10 to the other system main storage device 21 Write-only bus 50 used only at the time → connection of the own system central control processor 10 and the other system main storage device 21 to read / read data.
They are used in the order of the bus 40 for performing the write operation.
【0011】なお、他系中央制御処理装置11と自系主
記憶装置20との間でデータ読出し動作/書込み動作を
行う際も、同様に他系中央制御処理装置11と自系主記
憶装置20とを接続してデータの読出し動作/書込み動
作を行うバス41→他系中央制御処理装置11から自系
主記憶装置20への書込み時にのみ使用する書込み専用
バス51→他系中央制御処理装置11と自系主記憶装置
20とを接続してデータの読出し動作/書込み動作を行
うバス41の順序で使用する。When a data read operation / write operation is performed between the other system central control processing device 11 and the own system main storage device 20, the other system central control processing device 11 and the own system main storage device 20 are similarly operated. Bus 41 for performing a data read / write operation by connecting to the bus → a write-only bus 51 used only when writing from the other system central control processor 11 to the main system main storage device 20 → the other system central control processor 11 And the local main storage device 20 are used in the order of the bus 41 for performing the data read / write operation by connecting.
【0012】本実施例の動作によれば、図2に示すよう
に初めの書込み動作が終了しなくても、もう片方の空い
ているバスを使用することで次の書込み動作に移ること
ができるので、データの読出し動作/書込み動作の時間
T2が従来例における時間T1(図3に図示)よりも時
間T3だけ短くなり早く終了する。According to the operation of this embodiment, as shown in FIG. 2, even if the first write operation is not completed, the next write operation can be started by using the other free bus. Therefore, the time T2 of the data read / write operation is shorter by the time T3 than the time T1 (shown in FIG. 3) in the conventional example, and the operation ends earlier.
【0013】[0013]
【発明の効果】以上説明したように本発明は、自系主記
憶装置と他系主記憶装置のデータが異なる非同期モード
時における自系中央制御処理装置と他系主記憶装置との
間のデータの読出し動作/書込み動作を「読出し動作→
初めの書込み動作→次の書込み動作」の順番で行うとき
に、初めの書込み動作に影響されずに、次の書込み動作
に移ることができるので、処理能力の向上を図れるとい
う効果を有する。As described above, according to the present invention, the data between the self-system central control processing device and the other-system main storage device in the asynchronous mode in which the data of the main-system main storage device and the data of the other-system main storage device are different from each other. Read / write operation is changed to “read operation →
When performing in the order of “first write operation → next write operation”, it is possible to shift to the next write operation without being affected by the first write operation, so that there is an effect that the processing capability can be improved.
【図1】一般的な情報処理装置の一例を示すブロック図
である。FIG. 1 is a block diagram illustrating an example of a general information processing apparatus.
【図2】図1における本発明の一実施例の動作手順を説
明するための図である。FIG. 2 is a diagram for explaining an operation procedure of one embodiment of the present invention in FIG. 1;
【図3】図1における従来の動作手順を説明するための
図である。FIG. 3 is a diagram for explaining a conventional operation procedure in FIG. 1;
10 自系中央制御処理装置 11 他系中央制御処理装置 20 自系主記憶装置 21 他系主記憶装置 30 自系中央制御処理装置と自系主記憶装置とのデ
ータの読出し動作/書込み動作を行うバス 31 他系中央制御処理装置と他系主記憶装置とのデ
ータの読出し動作/書込み動作を行うバス 40 自系中央制御処理装置と他系主記憶装置とのデ
ータの読出し動作/書込み動作を行うバス 31 他系中央制御処理装置と自系主記憶装置とのデ
ータの読出し動作/書込み動作を行うバス 50 自系中央制御処理装置から他系主記憶装置への
ライト動作時にのみ使用する書込み専用バス 51 他系中央制御処理装置から自系主記憶装置への
ライト動作時にのみ使用する書込み専用バス 61,62 読出し動作 71,73 初めの書込み動作 72,74 次の書込み動作10 Self-system central control processor 11 Other-system central control processor 20 Self-system main storage device 21 Other-system main memory device 30 Reads / writes data between own-system central control processor and self-system main storage device Bus 31 for performing a data read / write operation between the other-system central control processing device and the other-system main storage device Bus 40 for performing a data read / write operation for the own-system central control processing device and the other-system main storage device Bus 31 A bus for reading / writing data between the other system central control processing device and the own system main storage device 50 A write-only bus used only at the time of a write operation from the own system central control processing device to the other system main storage device 51 Write-only bus 61, 62 Read operation 71, 73 First write operation 72, 74 Next, write-only bus used only at the time of write operation from other system central control processing device to own system main storage device Write operation of
Claims (1)
制御処理装置および自系,他系主記憶装置と、前記自系
中央制御処理装置が前記自系主記憶装置と接続されてデ
ータの読出し動作/書込み動作を行う第1のバスと、前
記自系中央制御処理装置が前記他系主記憶装置とデータ
読出し動作/書込み動作を行う第2のバスと、前記自系
中央制御処理装置から前記他系主記憶装置へのデータの
書込み動作時にのみ使用する書込み専用バスとを有する
情報処理装置において、両系の前記主記憶装置の一致し
ない非同期モード時に前記自系中央制御処理装置と前記
他系主記憶装置との間の動作手順が読出し動作→書込み
動作→書込み動作の順に行われたとき、前記第2のバス
→前記書込み専用バス→前記第2のバスの順序で使用す
ることを特徴とする情報処理装置。A self-system / other-system central control processor and a main-system / other-system main storage device having a duplex configuration; and the self-system central control processor is connected to the self-system main storage device. A first bus for performing a data read / write operation on the second system, a second bus for performing the data read / write operation of the own system central control processor with the other system main storage device, An information processing device having a write-only bus used only when data is written from the processing device to the other system main storage device, wherein the own system central control processing device is used in an asynchronous mode in which the main storage devices of both systems do not match. When the operation procedure between the main system and the other system main storage device is performed in the order of read operation → write operation → write operation, the second bus is used in the order of the write-only bus → the second bus. Characterized by Information processing device.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4297548A JP2888062B2 (en) | 1992-11-09 | 1992-11-09 | Information processing device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4297548A JP2888062B2 (en) | 1992-11-09 | 1992-11-09 | Information processing device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH06149764A JPH06149764A (en) | 1994-05-31 |
JP2888062B2 true JP2888062B2 (en) | 1999-05-10 |
Family
ID=17847971
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP4297548A Expired - Lifetime JP2888062B2 (en) | 1992-11-09 | 1992-11-09 | Information processing device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP2888062B2 (en) |
-
1992
- 1992-11-09 JP JP4297548A patent/JP2888062B2/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
JPH06149764A (en) | 1994-05-31 |
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