JPS6394786A - Video signal processor - Google Patents

Abstract

PURPOSE:To simply execute memory control without the need for a delay circuit and a changeover means by providing a serial input/serial output multi-port memory and a memory control circuit to allow the memory to execute input/ output operation. CONSTITUTION:An input data register 3a of the serial input/serial output multi- port memory 3 and an output data register 3c transfer a digital signal for one line of the memory cell array 3b with the memory cell array 3b altogether, and the memory control circuit 6 outputs a memory control signal to transfer the content of the input data register 3a storing a signal for one line of the memory cell array 3b by an input request signal to the memory cell array 3b or to transfer the signal for one line of the memory cell array 3b by an output request signal to the output data register 3c and outputs a clock or the like for input/output to the multi-port memory 3. Thus, no delay circuit nor changeover means is required.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an apparatus for processing a video signal using a memory.

[Conventional technology]

FIG. 3 shows a conventional video signal processing device using a memory that can perform random input and serial output asynchronously and simultaneously. In this conventional example, a playback signal from a video tape recorder 1 is displayed on a display device 2. The above-mentioned video signal processing device is used as a device for this purpose. In the figure, an input signal processing circuit 4 is connected to a video tape recorder 1.
converts the reproduced signal into a signal suitable for storing in the memory 7, and sends the signal to the input terminal of a delay circuit 90 connected to one of the movable contacts 8b and the other movable contact 8c of the switching means 8. At the same time, an input request signal is output to the read/write control circuit 10. Switching means 8
The output signal from the fixed contact 8a is stored in the memory cell array 7b in the memory 7. The stored information is transferred to the output data register 7c in one row of the memory cell array 7b, and is output to the output signal processing circuit 5. The output signal processing circuit 5 converts this output signal into a signal suitable for the display device 2 and outputs it to the display device 2.
An output request signal is output to the read/write control circuit 10. On the other hand, the read/write control circuit 10 controls a delay circuit control circuit 11 that controls the switching means 8 and the delay circuit 9, and a memory control circuit 6 that controls the memory 7.

Next, the operation will be explained. The memory 7 is a random input serial output memory that can perform random writing to the memory cell array 7b and serial reading via the output data register 7c asynchronously and simultaneously. However, the memory cell array 7
In order to transfer the information for one line of b, a period during which input is not possible occurs.

FIG. 4 shows the operation of the random input serial output memory in such a case.

Note that in the memory cell array 7b, one row of information is composed of eight pieces of information, one column of information is composed of N pieces of information (N is a natural number), and the (k+1) row of the memory cell array 7b is made up of eight pieces of information. (f+1) column (k=0. 1. 2...
, N-1; β-0, 1, 2°..., 7) is expressed as DI (k, n). In the switching means 8, the movable contact 8b is connected to the fixed contact 8a when the control signal from the delay circuit control circuit 11 is at a low level, and the movable contact 8C is connected to the fixed contact 8a when the control signal is at a high level. shall be.

Now, consider the case where information is stored in the second row of the memory cell array 7b. In FIG. 4, IVa is an input request signal, and in response to this signal, the delay circuit control circuit 11 first sets the control signal to the switching means 8 at a low level as shown at IVe, and the movable contact 8b as shown at IVf. The signal at is output to the fixed contact 8a. At the same time, the memory control circuit 6 outputs a control signal as shown at rVc to the memory 7 in response to the input request signal. Here, R(k) shown in IVc is a control signal for setting the (k+1)th row of the memory cell array 7b, and Cn is a control signal for setting the (n+1)th column of the memory cell array 7b. It is.

During such a write operation, when an output request signal indicated by IVb is output, the memory control circuit 6 interrupts the write operation and writes the requested information (memory cell array 7b).
output a control signal To (m) in order to transfer the (m+1)th row information) to the output data register 7c;
After the transfer is completed, a memory control signal is output to restart the write operation.

On the other hand, when the write operation is resumed, the delay circuit control circuit 11 changes the control signal for the cutting means 8 from a low level to a high level as shown by IVe, and receives the signal at the movable contact 8c shown by TVg, that is, the delay signal. The output signal is output to the fixed contact 8a.

As a result of the above operation, the signal at the fixed end 8a becomes as shown in IV d, and by repeating this, the input video information can be stored in the memory without loss or duplication.

[Problem that the invention seeks to solve]

Since conventional video signal processing devices using memory are configured as described above, delay circuits and switching means are required in order to store input video information in memory without loss or duplication, and memory There was also a problem that control was complicated.

The present invention has been made in view of the above, and an object of the present invention is to provide a video signal processing device using a memory that does not require a delay circuit or a switching means and can easily control the memory.

[Means for solving the problem] A video signal processing device according to the present invention includes a serial input serial output multi-port memory and input and output request signals generated from input and output video signals to the multi-port memory. A memory control circuit that generates a control signal for executing an output operation is provided.

[Effect]

In this invention, input and output are executed asynchronously and simultaneously in a multi-port memory, and an input data register and an output data register in the multi-port memory are connected to a memory cell array, for example, for one row of the memory cell array. Since this information can be transferred, video signal processing with asynchronous output can be performed using a simple circuit, and memory control at that time can be simplified.

〔Example〕

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 shows a video signal processing device according to an embodiment of the present invention. In this embodiment, the video signal processing device according to the present invention is used to display a reproduced signal from a video tape recorder 1 on a display device 2.

In the figure, 3 is a serial input serial output multi-port memory, which includes an input data register 3a to which serial digital signals are temporarily input, an output data register 3C used to serially output digital signals, The input data register 3a and the output data register 3C have a memory cell array 3b that stores digital signals, and the input data register 3a and the output data register 3C are configured so that digital signals for one row of the memory cell array 3b can be transferred to each other at once between the input data register 3a and the output data register 3C. It has become. 4 is an input signal processing circuit which converts the reproduced video signal from the video tape recorder 1 into an input digital video signal suitable for storage in the multi-port memory 3 and outputs it to the input data register 3a, and also outputs the input digital video signal to the input data register 3a. It outputs an input request signal to the Reference numeral 5 denotes an output signal processing circuit, which converts the output digital video signal from the output data register 3c into a video signal passed through the display device 2 and outputs it, and also outputs an output request signal to the memory control circuit 6.

Reference numeral 6 denotes a memory control circuit, which transfers the contents of the input data register 3a storing signals for one row of the memory cell array 3b to the memory cell array 3b by the input request signal, and transfers the contents of the input data register 3a storing signals for one row of the memory cell array 3b to the memory cell array 3b by the output request signal. A memory control signal for transferring one row of signals to the output data register 3C, a clock for input/output, etc. are output to the multiport memory 3.

Next, the operation will be explained using FIG. 2. Now, assume that one row of information in the memory cell array 3b is composed of eight pieces of information, and one column of information is composed of N pieces of information (N is a natural number).

In FIG. 2, Ila is an input request signal, and in response to this signal, the memory control circuit 6 outputs the write clock of the input data register 3a shown as Hc to the serial input serial output multiport memory 3, and by this operation,
As shown in ld, row 1 column (k
=0.1,2. ....

N-1; A'=O+ 1+ 2. ..., 7), the input digital video signal DI (k,
1) is written to the input data register 3a, and after one row of input digital video signals is written to the input data register 3a, the one row of input digital video signals is transferred from the input data register 3a to the memory cell array 3b. Transfer to line 1. This transfer period is nd as TI(
k).

On the other hand, nb is an output request signal, and this signal causes the memory control circuit 6 to control the (m+1)th row of the memory cell array 3b (m=o, 1, 2, .
-, N-1) to the output data register 3C, and the read clock of the output data register 3C shown in Ile created by the memory control circuit 6 is input to the serial input serial output multiport memory 3. , Ilf of the memory cell array 3b (m+1
) row (n+1) column (n=0.1, 2, . . . , 7) output digital video signal Do (m, n) is output from the output data register 3C.

In this way, in this embodiment, the transfer period TI(k) from the input data register 3a to the memory cell array 3b and the transfer period To(m) from the memory cell array 3b to the output data register 3c should not overlap. Accordingly, input video signal information can be easily stored in a memory without missing or duplicating information without using a delay circuit or switching means as in conventional devices.

Although the above embodiment describes the case where a playback signal from a video tape recorder is displayed, the present invention is not limited to the above embodiment, but can be applied to any system that performs video processing, and can be applied to any system that performs video processing in the same way as the above embodiment. It has the effect of

〔Effect of the invention〕

As described above, according to the present invention, a serial input serial output multiport memory and a memory control circuit for causing this memory to perform an output operation are provided, and information input and output are executed asynchronously and simultaneously. Since the input data register and output data register in the memory can transfer information for one row of the memory cell array between the memory cell array and the memory cell array, there is no need for any delay circuit or switching means in the conventional device. Further, there is an effect that a video signal processing device with easy memory control can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a video signal processing device according to an embodiment of the present invention, FIG. 2 is a diagram for explaining the operation of the embodiment of FIG. 1, and FIG. 3 is a diagram showing a video signal processing device using a conventional memory. FIG. 4 is a block diagram showing a conventional example of a signal processing device. FIG. 4 is a diagram for explaining the operation of the conventional example of FIG. 3... Serial input serial output multi-port memory, 6... Memory control circuit. Note that the same reference numerals in the figures indicate the same or equivalent parts.

Claims (1)

[Claims] (1) A video signal processing device that can perform input and output operations asynchronously and simultaneously, which is connected to a memory cell array for storing image information, an input data register connected to a serial input port, and a serial output port. A serial input/serial output multi-port memory that has a serial output data register and can execute serial information writing operations and serial information reading operations asynchronously and simultaneously; A video signal is input to the input data register, and after inputting the input video signal for the predetermined period, the information in the input data register is transferred to and stored in the memory cell array, and upon receiving the output request signal, the write is performed. A video signal processing device comprising: a memory control circuit that transfers a predetermined period of output video signals from the memory cell array to the output data register in parallel with the operation.