JPS63136884A - Video signal processor - Google Patents

Abstract

PURPOSE:To perform the write-in and the read-out of data in and from a memory asynchronously and, besides, simultaneously, to store and input video information without an overlapping and without an omission as well, and moreover, to output an output video signal without the turbulence of a synchronism and without the omission in a continuity by providing a serial input and serial output multiport memory and a memory controlling means to generate a timing to be transferred to an output data register. CONSTITUTION:The device is provided with the serial input and serial output multiport memory (SISO memory) 3, and with a memory controlling means 6, and an output digital video signal is transferred from a memory cell array, built in the SISO memory 3, to an output data register, on the standard of the operating state of the output side of the SISO memory 3, and at the same time, in a period, which is other than this transferring period and besides, is not carrying the video information of an input video signal, an input registered video signal is transferred from an input data register, built in the SISO memory 3, to the memory cell array. Thus, the input video information can be stored without the omission and without the overlapping as well, and the output video information can be outputted without the turbulence of the synchronism and continuously without omission.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to an apparatus for processing a video signal using a memory.

[Conventional technology]

Figure 3 shows conventional random input and serial
' A video signal processing device using a random input serial output multi-port memory (hereinafter abbreviated as R130 memory) that can be executed asynchronously and simultaneously with a video tape recorder 1 is shown. The above video signal processing device is used as a device for displaying on device 2. In the figure, an input signal processing circuit 4 converts a playback signal from a video tape recorder l into a digital signal suitable for storage in a RISO memory 7,
The signal is outputted to the input terminal of the second storage element 9 connected to one movable contact 8b and the other movable contact 8C of the switching means 8, and an input request signal created from the reproduced signal is read and written. Output to the control circuit 10. The digital signal output from the fixed contact 8a of the switching means 8 is R
RI via random input port d of ISO memory 7
It is stored in a memory cell array (MCA) 7b in the SO memory 7. The stored information is transferred to the output data register (DRO) 7c in the RISO memory 7 in one row of information in the MCA 7b, and then output from the serial port 7e to the output signal processing circuit 5 using the output clock. . The output signal processing circuit 5 converts this signal into a signal passed through the display device 2 and outputs it to the display device 2, and also outputs an output request signal created from the timing on the output side to the read/write control circuit 10. On the other hand, the read/write control circuit io includes an input signal control circuit 11 that outputs a control signal for the switching means 8 and a control signal for the second storage element 9;
The memory control circuit 6 controls the RISO memory 7.

Next, the operation will be explained.

Suppose now that the video information is composed of two-dimensional information of N rows and 8 columns (N is a natural number), and that the MCA 7b in FIG. 3 is also composed of N rows and 8 columns. Also, this MCA7b (m
+1) row (n+1) column (town-〇, 1, 2.-, N-I
Hn=0.1, 2. ....

7) input video information to be stored in DI(m.

n), conversely, the output video information output from the (m+1) row and (n+1) column of the MCA 7b is expressed as l)Q (m, n).

The operation of the conventional example shown in FIG. 3 will be explained using FIG. 4.

(al is an output video signal requested by the display device 2, and based on the horizontal synchronization signal H of this signal, the output request signal A shown in (b) is output from the output signal processing circuit 5 to the read/write control circuit 10. In response to the output request signal A, the read/write control circuit lO causes the memory control circuit 6 to
The line information requested by the display device 2 is sent from the MCA 7b to DR0.
The RISO memory 7 is made to output a control signal so as to be transferred to 7C, and the output digital video signal in the DROTC is read out via the serial output port e using the output clock shown in (C). Here, the information on the (m+1)th line (m=0.1, 2.-, N-1) of the MCA7b is transferred to the DRO7c.
The memory control circuit 6 transfers data to the RISO memory 7.
The period during which the control signal is output is shown as T ((2) in (d). Also, the playback signal from the video tape recorder 1 shown in (phantom) is input to one of the switching means 8 by the input signal processing circuit 4. The input digital video signal (see (h)) transmitted to the movable contact 8b and the second storage element 9, and the input request signal Bl output to the read/write control circuit 10)
is converted into In response to the input request signal B, the read/write control circuit 10 causes the memory control circuit 6 to output a memory control signal so as to write the input digital video signal to the MCA 7b during a period excluding the period of information transfer from the MCA 7b to the DRO 7C.

During the period from when the input request signal B is generated until the start of the transfer period, that is, during the period shown by G in (d), the input signal control circuit 11 causes the switching means 8 to reach the movable contact 8b shown in (h). The input digital video signal is controlled to be transferred to the fixed contact 8a. On the other hand, in the period from the end of the transfer period until the next input request signal B is generated, that is, in (d)
During the period indicated by , the input signal control circuit 11 controls the switching means 8 and the second storage element 9 to control the input digital video signal (signal (h) in the figure) arriving at the movable contact 8C indicated by (1). control is performed so that a signal delayed by two signals) is transmitted to the fixed contact 8a. By controlling in this way, the input digital video signal is processed without duplication or missing (M
Can be written to CA7b.

In addition, in (d), R(k) (k=o, 1, 2.
....

N-1) is a period during which the memory control circuit 6 sets the (k+1)th row of the MCA 7b to the RISO memory 7, and CC1l> (f=0.1.2°...,
7), the memory control circuit 6 controls the RISO memory 7
Let it represent the period for setting the (6+1)th column of CA7b.

[Problem that the invention seeks to solve]

Since the conventional video signal processing device using RISO memory is configured as described above, the output video information is outputted from the RISO memory continuously without any synchronization disturbance, and the input video information is outputted without any loss or duplication. In order to store the video signal in the memory without any problem, it was necessary to use a second storage element or switching means and to control the input video signal.

The present invention has been made to solve the above-mentioned problems, and without controlling the input video signal, it eliminates missing and redundant input video information, stores it, and outputs the output video information without disrupting synchronization. An object of the present invention is to obtain a video signal processing device that can output data continuously without any loss.

[Means for solving problems]

The video signal processing device according to the present invention has a serial input serial output multi-port memory having a serial input port and a serial output port, and consisting of an input data register, a memory cell array, and an output data register.
(SISO memory) and input and output request signals generated from input and output video signals to issue control signals that cause this 5ISO memory to execute input and output operations, and at this time, control the operating state of the output side of the 5ISO memory. The memory control means generates a control signal for transferring the stored information in the memory cell array to the output data register as a reference.

[Effect]

The video signal processing device according to the present invention is an srs.

The output digital video signal is transferred from the memory cell array built in the 5ISO memory to the output data register based on the operating state of the output side of the memory, and the 5ISO memory An input digital video signal is transferred from a built-in input data register to the memory cell array.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows a video signal processing device according to an embodiment of the present invention. This embodiment shows a video signal processing device according to the present invention used when displaying a playback signal from a video tape recorder 1 on a display device 2. It is.

In the figure, 3 is a serial input serial output multi-port memory (SISO memory), which is an input data register (DP) that temporarily stores digital signals serially input from a serial input port (SIP) 3d.
I) 3a and serial output jJ boat (SOP) 3e
It consists of an output data register (DRO) 3c that temporarily stores digital signals when outputting digital signals serially, and a memory cell array (MCA) 3b that stores digital signals. The DRI 3a and DR03C in the 5ISO memory 3 are configured to be able to collectively transfer digital signals for one row of the MCA 3b to each other between the DRI 3a and the DR03C. 4 is an input signal processing circuit which converts the reproduced video signal from the video tape recorder 1 into 5I.
It converts the input digital video signal stored in the SO memory 3 and outputs it to the 5IP 3d, and also outputs an input request signal to the memory control circuit 6. Reference numeral 5 denotes an output signal processing circuit, which converts the output digital video signal from 5OP3e into a video signal suitable for the display device 2 and outputs the same, and also outputs an output request signal to the memory control circuit 6. Further, 6 is a memory control circuit, and 5 ISO memory 3 is controlled by the above input request signal and output request signal.
A control signal for controlling the 5ISO memory 3 is output to the 5ISO memory 3.

Next, the operation will be explained using FIG. 2. It is now assumed that the video information is composed of two-dimensional information of N rows and 8 columns (N is a natural number), and that the MCA 3b in FIG. 1 is also composed of N rows and 8 columns. Also, (m+1) row (n
+1) column (m-0, 1, 2°..., N-1; n=01
l, 2. ..., 7) is the input video information to be stored in DI (m, n), and conversely, the input video information to be stored in MCA3b (m+1
) row (n+1) column is the output video information output from Do
Let it be expressed as (m, n).

In FIG. 2, (a) is an output video signal requested by the display device 2, and based on the horizontal synchronization signal H of this signal, the output signal processing circuit 5 makes an output request as shown in (b) to the memory control circuit 6. Signal A is output. Based on this output request signal A, the memory control circuit 6 transmits the row information requested by the display device 2 to the 5ISO memory 3 from the MC 3b to the DRO 3c.
A control signal is outputted to transfer the output digital video signal to the DRO3c (by the output clock shown in C1).
5OP3e. Here, MCA3b
(m+1)th line (m=o, 1.2.3.-, N
The period during which the memory control circuit 6 outputs a control signal to the 5ISO memory 3 in order to transfer the information of -1) to the DRO 3c is shown as T O (m) in (d). Furthermore, the playback signal from the video tape recorder 1 shown in (g) is processed by the input signal processing circuit 4 into the input digital video signal and the input request signal located at the end of each row of the input digital video signal shown in (f). B and are output to 31P3d and memory control circuit 6, respectively. The input digital video signal input via this 5IP3d is sent from the memory control circuit 6 to the 5IS.
It is written to the DRI 3a by the input clock 7 shown in (e) outputted to the O memory 3, and by the input request signal B,
A period other than the period in which the output digital video signal is transferred from the MCA 3b to the DRO 3c (period shown as E in (d)), and a period in which the input video signal does not carry video information ((
During the period indicated by F in g), the information of DRI3a is transferred to MCA3b.
Transfer to. Here, in order to transfer the information of the DRI 3a to the (k+1)th row (k=0.1°2, . . . , N-1) of the MCA 3b, the memory control circuit 6 sends a control signal to the 5ISO
The period of output to the memory 3 is indicated by (Tl in dl).

In this embodiment, input video information can be stored without duplication or loss without using a second storage element or switching means as in conventional devices, and output video signals can be stored without synchronization disturbance. It can be output continuously without any omissions.

Although the above embodiment describes the case where a playback signal of a video tape recorder is displayed, the present invention is not limited to the above embodiment, but can be applied to any system that performs video processing, and the present invention can be applied to any system that performs video processing. It has a similar effect.

Further, in the above embodiment, the video information is composed of two-dimensional information of N rows and eight columns (N is a natural number), but the present invention is not limited to the above embodiment, and general two-dimensional information It can be applied to

Further, in the above embodiment, the output request signal is set after the horizontal synchronization signal of the output video signal, and the input request signal is set at the end of one line of the input digital video signal, but the present invention is not limited to the above embodiment. (The output request signal only needs to be the period from outputting the output digital video signal of the previous row to the next output digital video signal requested by the output side, and the input request signal is the period from the output of the output digital video signal of the previous row to the next output digital video signal requested by the output side, and the input request signal is the period from the output of the output digital video signal of the previous row to the next output digital video signal requested by the output side.) It may be any period from the time the signal is input to the DRI until the arrival of the next input digital video signal.

〔Effect of the invention〕

As described above, according to the present invention, the memory control means generates the control signal for causing the SI ISO memory to perform input/output operations based on the input and output request signals created from the 5ISO memory and the input and output video signals. Since data can be written to and read from the memory asynchronously and simultaneously, the input video information can be read without using the second storage element or switching means in the conventional device, and without controlling the input video signal. The present invention has the effect of providing a video signal processing device that can store video signals without duplication or loss, and output video signals continuously without synchronization disturbance and without loss.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a video signal processing device according to an embodiment of the present invention, FIG. 2 is a diagram for explaining the operation of the embodiment of FIG. 1, and FIG. 3 is a diagram showing a conventional random input FIG. 4 is a block diagram of a video signal processing device using a serial output multi-board memory, and is a diagram for explaining the operation according to the third conventional example. 3... Serial input serial output multi-board memory, 6... Memory control circuit. Note that the same reference numerals in the figures indicate the same or equivalent parts.

Claims (1)

[Claims] (1) A video signal processing device that can perform input and output operations asynchronously and simultaneously, including an input data register connected to a serial input port;
output data register connected to serial output port,
and a memory cell array connected to the input data register and the output data register for storing image information, the operation of writing information to be stored from the serial input port to the input data register, and storing from the output data register. A serial input serial output multi-port memory capable of asynchronously and simultaneously executing an operation of reading information through the serial output port, and outputting the stored information in the memory molar array based on the operating state of the output side of the memory A video signal processing device comprising: memory control means for generating timing for transferring data to a data register.