JPH01262586A - Control circuit for dual port memory - Google Patents

Abstract

PURPOSE:To execute asynchronous write and read-out of data by latching write data and an address signal at the time of suspending write and executing a transfer of data from a dual port memory. CONSTITUTION:The title circuit is provided with a read-out circuit for requesting a data transfer at the time of read-out and for generating a read-out clock and an address signal, and a write circuit for latching write data and an address signal when a data transfer to a shift register from a serial output port and a write timing have been superposed and for sending out a data transfer pulse which has joined write and the timing and the address signal from the read-out circuit to a dual port memory. In such a way, an input and an output to and from the dual port memory of data can be controlled, and asynchronous write and read-out to and from the dual port memory can be executed.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a dual-port memory control circuit that allows asynchronous writing and reading of image signals and the like to and from a dual-port memory.

Conventional technology FIG. 3 shows the configuration of a dual port memory.

Memory cell 1 52 is a shift register for serial output. Since input and output are performed separately, one of them is performed from the serial port, but here we will explain the case where output is performed from the serial port. @Writing is performed by specifying the 9th row and 1st column address and using the address duder 3 for each bit. On the other hand, for reading, a row address is designated, and all data in that row is transferred to the shift register 2, and serially output starting from the data designated by the column address. Therefore, the output is line by line. shift register 2
Transfer to memory cell 1 can be performed in the same time as writing 1 bit to memory cell 1. in this way.

By using separate ports for input and output and performing transfer to the shift register 2 while data is not being written, simultaneous writing and reading can be performed.

Problems to be Solved by the Invention However, in the conventional method of writing and reading in the dual-port memory described above, when asynchronous input/output is performed, the input and the data transfer may overlap, and simultaneous input/output is not possible. It was possible.

SUMMARY OF THE INVENTION An object of the present invention is to solve these conventional problems and provide a dual-port memory control circuit that can perform asynchronous input/output at the same time.

Means for Solving the IS Problem In order to solve the above problem, the present invention provides the following steps at the time of reading.
A read circuit that requests data transfer and generates a read clock and address signal.

When the data transfer from the serial output port to the shift register and the write timing overlap, the write data and address signal are latched, and the data transfer pulse and the address signal from the read circuit are synchronized with the write timing. It is equipped with a write circuit that sends data to dual port memory.

Effect: The above configuration has the effect of controlling the input/output of data to the dual port memory and enabling asynchronous writing and reading from the dual port memory.

Example An embodiment of the present invention will be described below based on the drawings.

FIG. 1 is a block diagram showing a dual port memory control circuit according to an embodiment of the present invention.

In FIG. 1, 4 is a write circuit which receives write data a and clock b, and receives write clock C.
and address signal d, and write data a to the dual port memory 5. Reference numeral 6 denotes a reading circuit which receives the 5 clock e, generates a read clock f, an address signal g, and a data transfer request signal 11, and outputs the read data a'.
is read from the dual port memory 5. Here, the dual port memory 5 includes memory cells, a shift register, and an address duder as in FIG.

Next, the operation of the above configuration will be explained.

The data is image data, and writing and reading are performed asynchronously. This situation is shown in FIG. 2. FIG. 2(a) shows the timing of write data, and FIG. 3(b) shows the timing of read data.

When write data a and clock b in FIG. 2(a) are sent to the write-in circuit 4 in FIG.
and an address signal d to write data into the dual port memory 5. On the other hand, when a clock e is sent to the readout circuit 6 for asynchronous reading, a readout clock f and an address signal g are generated. Furthermore, a data transfer request signal is generated. The data transfer request signal is sent during a blanking period during a predetermined read data timing, as shown in FIG. 3(b). The write circuit 4 detects this data transfer request signal,
Pulse i for data transfer synchronized with writing
occurs. At the same time, write data a during data transfer
This data transfer pulse i and the address signal g sent from the reading circuit are sent to the dual port memory, and the data is transferred. After data transfer, subsequent writing is shifted one bit at a time and writing is restarted.

As described above, according to the above configuration, the data transfer request signal from the read circuit 6 is sent to the write circuit 4, the write is interrupted, and data is transferred from the dual port memory 5. Since the write data a and address signal d are latched, there is no break in the write data.

Asynchronous writing and reading to and from the dual port memory 5 becomes possible.

Effects of the Invention According to the present invention, when writing is interrupted and data is transferred from the dual port memory, the write data and address signal are latched, so that data can be written asynchronously using the dual port memory. , has the effect of making reading possible.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is a write and read timing diagram, and FIG. 3 is a block diagram of a dual port memory. 1...Memorial, 2...Shift register, 3...
・Address decoder, 4...Writing circuit, 5...
・Dual port memory, 6...reading circuit, a
...Write data, a'...Read data, b
...Clock, C...Written clock, d...
Address signal. e...clock, f...read clock, g...
Address signal, h...data transfer request signal, i...
Pulse for data transfer. Agent Yoshihiro MorimotoFigure 7Figure 2

Claims (1)

[Claims] 1. A control circuit that writes to the dual port memory and reads from the serial output port, which generates a read clock, an address signal, and a data transfer request signal when reading, and a read circuit that generates a read clock, an address signal, and a data transfer request signal, and the data transfer request. When the data transfer from the serial output port to the shift register by a signal coincides with the write timing, the write data and address signal are latched, and the data transfer pulse and the address signal from the read circuit are transferred to the dual port memory. A control circuit for dual port memory equipped with a write circuit to send data to.