JPS58154964A - Picture information processing system - Google Patents

Abstract

PURPOSE:To decrease the share of a load for a microcomputer and a bus, by providing a refresh control function and an access function for a buffer memory and controlling the functions directly not via a microcomputer bus. CONSTITUTION:Frequency division circuits 17, 19 distinguish an access period and a refresh period so as not to be overlapped and the transfer timing of a picture signal is adjusted with a serial/parallel converting circuit 20 and a latch circuit 23, then a reader 1 generates a serial reading picture signal (a) continuously without being effected with the refresh period. The reading picture signal (a) is transferred in high speed not through a bus 5 of a microcomputer 4 and written in a buffer memory 6 in parallel by 8-bit, then the microcomputer 4 executes other information processing jobs during this period.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an image information processing system, and in particular, it is capable of electrically storing image signals for one page by including a large-capacity Dyna-Dentsuta RAM (9 random access memory) as a buffer memory. The present invention relates to a visual information processing system that is similar to a facsimile construction system.

Ultra-high-speed 7-axle and high-performance 7-axle cameras use a large-capacity buffer memory that can store at least one page's worth of LIIGI signals, and a microcomputer can read, record, store, edit, and transmit information on both axes. It is necessary to carry out circular operations.

Dynamic RAM is suitable as a large-capacity buffer memory, but dynamic RAM requires refresh control, so K, which stores and reads image signals at high speed and at a constant speed, is not suitable, and it is not suitable for reading devices. Dynamic RA uses serial image signals obtained from
Transfer period and dynamic RAM for storing in M
Since the path of the microcomputer is monopolized during the period during which image signals are read out and transferred to the image processing device, the microcomputer is in an environment in which it is difficult to perform other information processing operations.

Figure 1 is a block diagram of a conventional facsimile of this type.
The information double-axis reading device 1 and the information recording device 2 are connected to the path 5 of the microcomputer 4 via the interface circuit 3.
A buffer memory 6 consisting of a zero dynamic FLAM is connected to the path 5 via a refresh control circuit 7. Operation [18 is connected to path 5 via interface circuit 9. A modem (demodem) 12 which inputs/outputs input/output to the transmission line 11 via the line connection unit 10 and communicates with the other party's facsimile machine passes the path 5Kfl! via the interface circuit 13! Continued. Therefore, when writing the serial image signal obtained from the reading register 111 to the buffer memory 6 and storing it, or when reading the image signal stored in the buffer memory 6 and recording and reproducing it with the image recorder 2, the pass is required. Since the buffer memory 6 cannot be accessed during the refresh period of the buffer memory 6, the microcomputer 4 must adjust the signal transfer timing. The computer 4 and the path 5 are in an environment where it is difficult to carry out other information processing tasks because of the heavy load sharing.

Therefore, an object of the present invention is to match the memory access for No. ii*1, which is continuously transferred serially at high speed, with the period during which buffer 7 can be accessed, and to lighten the load sharing between the microcomputer and the path. An object of the present invention is to provide an information processing system that enables computers to perform other information processing tasks.

In order to achieve this object, the present invention has a refresh control function and an access function for the buffer memory, a function of serial-to-parallel conversion and parallel-to-serial conversion of the #* signal, and a signal transfer timing adjustment function. The control circuit is connected to the microcomputer path.
The interface circuit connected to the mgN reading device and the image recording device is connected to the interface circuit of the microcomputer without intervening the microcomputer path, and the image signal transfer between the buffer memory and the reading device or the image recording device is performed by the microcomputer. The present invention is characterized in that the memory access for the iki* signal is matched with the buffer memory accessible period by being able to be executed without intervening paths, and the load sharing between the microcomputer and the path is reduced.

The present invention will be explained in detail below based on illustrated embodiments.

@2 Cause is a facsimile block diagram showing one embodiment of the present invention, in which a buffer memory 6 consisting of a dynamic RAM
is directly connected to the interface circuit 3 via the control circuit 14. As will be described later, this control circuit 14 has a refresh control function and an access function for the buffer memory 6, as well as a function of serial-to-parallel conversion of the Kllillll signal, a function of serial-to-parallel conversion, and a signal transfer timing adjustment function. Therefore, when writing and storing the image signal from the reading slowing device 1 in the buffer memory 6 according to an instruction from the operation unit 8, or when reading the image signal stored in the buffer memory 6 and recording and reproducing it in the image recording 11t2, When the microcomputer 4 gives a scanning command, the control circuit 14 handles image signal transfer timing adjustment and refresh control, so serial image signals can be transferred continuously at high speed.
Since the signal transfer does not go through the path 5, the load sharing between the microcomputer 4 and the path 5 is reduced, making it easier for the microcomputer 4 to perform other information processing tasks. Since the computer 4 can access the buffer memory 6 via the control circuit 14, the modem 12 and the enclosure connection section 10 are connected in a subordinate manner to the interface circuit 13. Transmission times fi! 11, it becomes possible to communicate with the other party's facsimile.

Figure 3 shows two buffer memories 6A and 6BK control circuit 1.
4A and 14B are connected, and the control circuits 14A and 14B are connected to the interface circuit 3 by the selection circuit 15, and the i** signal obtained from the reading device 1 is stored in the six buffer memories, while the microcomputer 4 backs up the i** signal. The memory 6B can be accessed to perform information processing operations such as editing, synthesizing, encoding, and transmitting image signals.

FIG. 4 is a block diagram of the control circuit 14 according to the present invention. The reference clock outputted from the reference clock generation circuit 16 is frequency-divided by the division circuit (1) 17 and inputted to the transfer lock generation circuit 18. The transfer lock generation circuit 18 outputs a transfer lock signal when a scanning command is given from the microcomputer 4 via the interface circuit 3. The transfer lock signal is divided by 1/N (in this example, 3( ), a serial-to-parallel converter circuit 2o consisting of a shift register that converts the read image signal a input serially into an 8-bit parallel write ii*signal dk&; 8-bit parallel readout iI read from port 6
A parallel-to-serial conversion circuit 21 consisting of a shift register that converts the salary signal d' into a serial recorded image signal 1'.
given to. The latch (■-do) signal e obtained by dividing the frequency of the four-channel signal S transferred by the frequency dividing circuit (2) 19 is sent to the address generation circuit 22, the latch circuit 23, and the parallel-to-serial conversion circuit 21. and access signal generation circuit 2
given to 4. The address generation circuit 22 uses latch signals and
The latch circuit 23 generates a read/write access address signal every time the latch signal e is input, and the latch circuit 23 latches the output of the serial-parallel conversion circuit 2° every time the latch signal e is input. P-do how it comes out. The refresh signal f obtained from the frequency divider circuit (In2) is used to distinguish between the accessible period and the refresher period for the buffer memory 6. The refresh signal f is input to the fresh address generation circuit 26, which generates a refresh address signal, and is also input to the discrimination circuit 27.The discrimination circuit 27 receives the refresh signal f and the output from the interface circuit 3. This system judges the input timing of the memory access signal and processes the one that was input first first.For example, if the refresh signal f becomes high level first, the signal is sent from the microcomputer 4 via the interface circuit 3. It waits for an applied memory access signal and performs memory access after the refresh period ends.The output of the determination circuit 21 is given to the access signal generation circuit 24 and the switching circuit (2) 28K.The switching circuit (υ29 is The access address signal g is generated by switching between the output signal of the address generation circuit 22 and the microcomputer address signal commanded from the microcomputer 4.
The switching circuit (2) 28 selects which of the address signal, fresh address signal, and access address signal gl to be applied to the pack memory 6. The switching signal output from the interface circuit 3 is for direct access to the micro combinator 4 (rough candy 6), and is for direct access to the micro combinator 4.
is input to control this and switch m1ll(
1) A read/write signal is further input to the access signal generation circuit 24, and the access signal generation circuit 11124 passes the microcomputer address signal input to the access signal generation circuit 24. RA8 signal g to buffer memory S based on the signal
l (hl), outputs the CAS signal g2 and the read/2 write signal R/W, and further outputs the RAS signal to the latch circuit 25.
0 outputs a latch signal synchronized with the rising edge of signal g□
The input/output signals of the nokura memory 6 are also input/output to the interface circuit 3 as microcomputer data bus signals.

The facsimile machine having the control circuit 14 as described above has the following three types.
Each function has four operating functions.
Selected by control signal from The operation of these three functions is shown in Figure 115 and Figure 6. 0 Operation function 1 This operation IflA*e is a function to store the serial read igI signal a obtained from the read r#Ic device 1 into the backup memory 6, and is a function of the type shown in FIG. The construction chart corresponds to this. The switching signal passes only the refresh signal f to the discrimination circuit 2T, and the switching circuit (υ2
9, only the address 4FI output from the address generation circuit 22 is passed through, and the access signal generation circuit 2
4, a command is given to issue a command to read in at the timing of the latch signal C. The input/output signals of the buffer memory 60 are separated from the bus 5 of the microcomputer 4. Next, when a scanning command is generated, the transfer lock generation circuit 18 outputs a transfer lock signal corresponding to the number of pixels in one scanning line. This transfer lock b is the reader device 1
The reading device 1 receives this transfer lock signal b
Vc is outputted in four cycles and the scattered image signal a is serially output. The serial cutout image * signal a inputted to the control circuit 14 via the interface circuit 3 is sent to the serial-parallel conversion circuit 2 (0 frequency division circuit (2) with NU large input) 19
counts the transfer lock signals and sends the launch signal e every 8 times.
The 8-bit parallel output of the serial-parallel conversion circuit 20 is latched by the latch circuit 23, and the access address signal gj from the address generation circuit 22 is output.
update. This latch signal e is also input to the access signal generation circuit 24, and the access signal generation circuit 24 uses RASg! for writing. i issue g1. Generate CA8 belief gs. Also, at this time, the refresh signal f output from the frequency divider circuit (1) 17 becomes low level, and the discrimination circuit 2
Since the output of 7 is set so that the switching circuit a and 2B passes the access address signal gs, the 8-bit write image signal d output in parallel from the latch circuit 23 becomes the 0-following fresh signal t written into the buffer storage 6. When the level reaches the high level, the refresh address generation circuit 26 updates the refresh address, and the output of the determination circuit 2T causes the access signal generation circuit 24 to generate the refresh RA8 signal hl and the switching circuit (
2) Allow refresh address signal h2 to pass through 28. With this, the buffer memory 6 is refreshed. This series of operations is performed by the transfer lock signal e.
This is executed within the generation period of the latch signal e obtained by dividing the frequency by 3AK. During this execution period, the serial-parallel conversion circuit 20 inputs the next 8-bit serial read image signal a to prepare for the next write. In this way, the frequency dividing circuits 17 and 19 distinguish the access period and the fresh period so that they do not overlap, and the serial-parallel conversion circuit 20 and the latch circuit 23 adjust the image signal transfer timing, so that the reading device 1 A serial read image signal a can be generated continuously without being affected by the refresh period. Then, the read image signal a is transferred at high speed without passing through the bus 5 of the microcomputer 4, and written into the buffer memory 6 in 8-bit parallel format, so the microcomputer 4 can perform other information processing during this period. It becomes possible to perform the work.

In addition, this operation function 1 is transmitted to the other party's 77 via the transmission line 11.
0 action function 2 which can also be used to temporarily store the facsimile tV** data sent at high speed from the fax machine Recorded with my recording device 2
In the reproducing function, the 0 switching signal corresponding to the tie setting signal shown in FIG. 96 is on the recording device side, and the access signal generating circuit 24 is made to generate a memory read signal at the timing of the latch signal e. The input/output signals of the buffer memory 60 are separated from the bus 5 of the microphone monitor. When a scanning command is generated, the transfer lock generation circuit 18 generates a transfer lock signal b'.

When the latch signal C is generated from the frequency divider circuit (2) 111, the address generation circuit 22 updates the access address signal g, and the access signal generation circuit 24 updates the access address signal g.
It generates the i, g, and CA8 signals.

Also, at this time, the refresh signal f becomes low level, so the switching circuit 28 outputs the access address signal ga, and the 8-bit parallel image signal d' is read out from the buffer memory 6. Then, the access signal generation circuit 24 supplies a latch signal to the latch circuit 25 in synchronization with the rise of the RAS signal g1, and inputs the read 8-bit image signal d' to the latch circuit 25 twice. After that, the refresh signal f becomes high level, so the buffer memory 6 is refreshed in the same way as described above.When the launch signal e is output from the zero-order frequency dividing circuit (19), the latch circuit
The 81 image signals d' are loaded into the parallel-to-serial conversion circuit 21. Parallel-serial conversion circuit 2
The image signal d' loaded into 1 is transferred and serially outputted as the recorded image signal a' by the lock signal S during the next division period. The image recording device 2 receives this recorded image signal a.
’ to record and play back images. Further, the latch signal e is inputted to the address generation circuit 22 and the access signal generation circuit 24 in order to read out the next 8-bit 1mgI signal d' during this recording/reproduction. In this way, the surrounding path 17.1S
Therefore, the access period and the fresh period are divided into 5 without overlapping, and the ms scratch signal transfer tie is adjusted by the parallel-serial converter 21 and the latch circuit 25, so the image recording device 2 can continuously The recorded image signal a' can be serially input and recorded and reproduced. Then, the recorded image signal field' is transferred to the microcomputer 4 without passing through the path 5, so the microcomputer 4 performs other information processing operations during this period. It can also be used for reading to transmit a 7-axis picture signal at high speed to the other party's 77-axis line via the 7-axis line.

Operating Function 3 This operating function is a function for directly accessing the backup memory 6 by the microcomputer 4. The tie-on chart for writing is shown in Fig. 5, and the tie-off chart for reading is shown in Fig. 6.
The conversion function will stop. ). The switching signal instructs the discrimination circuit 27 to process the fresh signal f and the memory access signal in the order of input, and the switching circuit (1
) 29 to pass the microcomputer address signal, and the access signal generation circuit 24 is instructed to pass the microcomputer address signal.
O and NO (rough memory 60 input/output signal d(
d') is transferred via the interface circuit 3 as a microcomputer data bus signal. The refresh signal f is periodically output from the frequency divider circuit (1), 17,
Refresh address generation circuit 26 updates its fK refresh address. The determining circuit 2T then determines the processing order by determining the input order of the refresh signal f and the memory access signal output from the microcomputer 4. Then, refreshing and accessing the backup memory 6 are repeated in the same way as the operations of the two operating functions described above. In this case, the input/output signals of the backup memory 6 are transferred to the microcomputer 4 as a data signal via the path 5 of the microcomputer 4, the editing and interface circuit 13, the modem 12, and the network connection. 10. Communication with the other party's facsimile machine via the transmission line 11.

As explained above, according to the present invention, the buffer memory has [a refresh control function and an access function, a function of serial-to-parallel conversion and a parallel-to-serial conversion of image signals, and a signal transfer tie construction adjustment function. A control circuit with a buffer memory is connected directly to the interface circuit connected to the path of the miter q; and read Wcl
Transfer the image signal of 11 or 111g1IIe Brass Ginokiseki! Since the access for the ili* signal, which is continuously transferred serially at high speed, can be executed without intervening the path of the ambiator, it is possible to align the access with the backup memory access period while avoiding the refresh period. You can do it! This has the effect of lightening the load sharing between the computer and the bus, allowing the microcomputer to perform other information processing tasks. Further, since the buffer memory access period is 1/N of the transfer lock signal, the access time can be lengthened, and a dynamic RAM having a slow response speed can be used.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a conventional facsimile, FIGS. 2 and 3 are block diagrams of a seven-axle system according to the present invention, FIG. 4 is a block diagram of its control circuit, and FIGS. This is an operational tie-building chart. 1...Reading device, 2...Image recording device, 3...Interface M, 4...
... Microcomputer, 5 ... Bus, 6
... Buffer memory, 14 ... Control circuit, 18 ... Transfer lock generation circuit, 19 ...
... Frequency divider circuit, 20 ... Serial-parallel conversion circuit, 21 ... Parallel-serial conversion circuit, 22 ... Address generation circuit, 24 ...
...atase signal generation circuit, 26...refresher address generation circuit, 2T...discrimination circuit,
28......To the switching circuit, ff1l'n Fig. 4, Fig. 5b'' b + Fig. 6, 10l

Claims (1)

[Claims] 1. Microcomputer bus K (buffer memory consisting of an i!11gl1 reader and an image recording device connected in cascade via an inter-7Ace circuit, and a Dynaelectric RAM for image signal storage connected in cascade to a control circuit) In the image information processing system, the control circuit is connected to the interface circuit, and the control circuit includes a frequency dividing circuit that divides the frequency of the image signal transfer lock signal to 1/N, and a frequency dividing circuit that divides the frequency of the image signal transfer lock signal into 1/N, and a serial-to-parallel conversion means for converting a serial image signal into an N-bit parallel image signal; and a serial-to-parallel conversion means for converting the N-bit parallel image signal read from the buffer memory into a serial image signal and inputting it to an interface circuit. a parallel-to-serial conversion means; a means for refreshing the buffer memory; and storing N-vira triparallel image signals outputted from the serial-to-parallel conversion means in the buffer memory; or)
an access means for generating an N-bit parallel image signal from the rough memory; and an access stage for enabling the refresh means during a part of the period between the 1/N division periods and providing the refresh means during other periods. An ijime axis information processing system characterized by comprising a switching means for enabling