JPS63123142A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To facilitate a window display by providing a mask transfer control means which outputs only data specified by a transfer starting column address and a transfer ending column address among data temporarily stored in a data register and which will not output data other than that data. CONSTITUTION:Address information inputted to registers 8 and 9 is inputted to the mask transfer control circuit 10 and this circuit generates a signal which controls a data transfer gate 12 when data is transferred. The transfer of data in areas except for the one specified by the registers 8 and 9 is stopped by turning off the gate. On the other hand, at the normal data transfer, the data of a whole row is transferred by only inactivating a WR (Bar), the column address is supplied to a serial read counter 11. The mask transfer control circuit 10 and the transfer gate 12 compose the mask transfer control means.

Description

[Detailed description of the invention] [Industrial application fields] The present invention relates to a semiconductor memory device.

[Prior Art] Conventionally, as this type of semiconductor memory device, the one shown in FIG. 3 is known. This semiconductor memory device includes a data register 102 in addition to a memory cell array 101.
It has a function to output image data, etc. from this data register 102 asynchronously with random access (a semiconductor memory device having such a function is called a dual portram, and is a μPD4 manufactured by NEC Corporation).
1264C etc. are known). The functions of the dual port ram shown in FIG. 3 will be explained below with reference to the timing chart shown in FIG. 4. first,
After a low level signal is supplied to the data transfer terminal TR (bar), the chip selection terminal CEI (bar) is shifted to a low level and a row address is taken in. As a result, one row of data in the memory cell array 101 specified by the row address is transferred to the data register 102 with the same storage capacity. Next, when a low level signal is supplied to the chip selection terminal CE2 (bar), the column address is fetched, and data is serially transmitted from the address specified by this column address through the register output dedicated terminal SO (bar). Output.

[Problems to be Solved by the Invention] As mentioned above, when trying to display a window using the conventional dual port RAM, there was a problem in that the timing became complicated. For example, as shown in FIG. 5, the memory cell array 101 has a storage capacity of 512 rows x 1024 columns, of which data for 400 rows x 640 columns is displayed, and the data is indicated by diagonal lines. When displaying windowed data, although the actual window data is stored in the area shown by the solid line, the image is displayed as if it were stored in the area shown by the broken line. must be displayed. Therefore, in the conventional example, data is transferred during the horizontal synchronization period, and the control for the window described above is realized by transferring data to the display area by software, or by transferring data while displaying, or in the case of the μPD41264C mentioned above, real-time data transfer. This function can be realized in one of two ways. That is, in the example of FIG. 5, at timing C, n
The row data (1024 bits) is transferred to the register 102, the window data is transferred again at timing A, and the data for the original display (n
data) must be transferred in real time.

Moreover, the present invention provides a semiconductor memory device that can easily display the above-mentioned window display.

[Means, operations and effects for solving the problems] The present invention provides a memory cell array having a plurality of memory cells arranged in rows and columns, and a memory cell array having a plurality of memory cells arranged in rows and columns, and a memory cell array having a plurality of memory cells arranged in rows and columns. In a semiconductor storage device that includes a data register that temporarily stores and serially outputs data of a memory cell belonging to a memory cell, a register that stores a transfer start column address and a transfer end column address, respectively, and a data register that temporarily stores data of a memory cell belonging to the data register and serially outputs the data, It is characterized by further comprising mask transfer control means that enables output of only data specified by a transfer start column address and a transfer end column address among the stored data and disables output of other data, When displaying a window or superimposing figures, among the data of each row read out sequentially,
Data to be excluded for window display is selectively output by mask transfer control means. As a result, the effect that window display, etc. can be obtained without setting complicated timing can be obtained.

[Embodiment FIG. 1 is a block diagram showing an embodiment of the present invention.
is a memory cell array having multiple bits of 128 rows x 128 columns. CEI (bar) is the chip activation main clock, which latches the row address to the address manual buffer 4 and transfers the command TR to the row address decoder 5 (
Activation of timing generator 1 and peripheral circuits such as a sense amplifier and the like for execution.

CF2 (bar) is input to the timing generator 2 after CEI (bar) is supplied, and the column address is latched. TR (bar) transfers one row of data from the memory cell array 7 to the data register 13 via the transfer gate 12.
This is the activation input of the timing generator 3 for transfer to the timing generator 3. This timing generator 3 is a register 8
．． 9. Activate the mask transfer control circuit 10 and execute the transfer. WR (bar) is also supplied to the timing generator 14, which generates a control signal for writing the column address into the register 8.9.

Upon receiving this activation signal, if CEI (bar) has already been activated and CF2 (bar) becomes active (if TR (bar) and WR (bar) are active), the column address is taken into register 8. It will be done. Further, the column address is taken into the register 9 at the timing when CF2 (bar) becomes inactive while CEI (bar) is active. The above operation timing is shown in FIG. After this, register 8.
The address information input to 9 is sent to mask transfer control circuit 10.
This circuit generates a signal that controls the data transfer gate 12 when data transfer is executed (actually, when TR (bar) is inactivated or CEI (bar) is inactivated). , transfer of areas other than those indicated by registers 8 and 9 is stopped by turning off the gates. On the other hand, during normal data transfer, WR
All data for one row is transferred only by inactivating the bar, and the column address is supplied to the serial read address counter 11. This counter 11 is incremented by the SC clock during serial reading, and the serial reading is repeated. During mask transfer, it is disconnected from the column address input.

The mask transfer control circuit 10 and transfer gate 12 constitute mask transfer control means.

As explained above, in this embodiment, a mask data transfer cycle is executed in advance using registers 8 and 9, and it becomes possible to rewrite part of the contents of the registers that have already been transferred. There is no need to transfer data during the period, and serial read operations can be performed.

Furthermore, more complicated window display or overlapping of figures can be performed during the same horizontal scanning period without complicated timing control.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a timing chart of an embodiment, FIG. 3 is a block diagram of a conventional example, FIG. 4 is a timing chart of a conventional example, and FIG. The figure is a block diagram showing the data storage state when a window is displayed. 7... Memory cell array, 8... Register, 9... Register, 10... Mask transfer control circuit, 12... Transfer gate, 13. ...Data register.

Claims (1)

[Claims] A memory cell array having a plurality of memory cells arranged in rows and columns, and a data register that temporarily stores and serially outputs data of memory cells belonging to a row designated by the row address signal in response to a row address signal. A semiconductor memory device comprising a register that stores a transfer start column address and a transfer end column address, respectively, and a transfer start column address and a transfer end column address among the data temporarily stored in the data register. 1. A semiconductor memory device, further comprising mask transfer control means that enables output of only data specified by and disables output of other data.