JPS63229685A - Method for controlling memory - Google Patents

Abstract

PURPOSE:To enable only a part of the data of a memory cell array to be rewrit ten when the data is inputted through a serial port by previously writing the prescribed lines of the data in the serial port before transferring the serial inputted data to the prescribed line of the memory cell array. CONSTITUTION:Before the data is serially inputted, the prescribed Rn lines of data on the memory cell array MS is transferred to the serial port SP and after the data is serially inputted to the serial part SP where the prescribed lines of data is written, the data of the serial port of which part associating with the serial inputted data is rewritten is transferred to the prescribed line Rn of the memory cell array MS. Thus, even when the one part of the data of which size is smaller than that of the serial port is rewritten by the serial input, the prescribed lines of data are preserved on the rest of it and only the one part of the data on the memory cell array can be rewritten.

Description

DETAILED DESCRIPTION OF THE INVENTION A. Field of Industrial Application The present invention relates to a memory control method, and more particularly to a memory control method for inputting data to a RAM with a serial access port.

B0 Summary of the Invention The present invention provides a memory control method for serially inputting data to a RAM with a serial port and transferring the serial input data to a predetermined row on a memory cell array. By transferring the data in the above specified line to the serial port,
This allows serial input while retaining the original data other than the rewritten portion.

C9 Conventional technology In recent years, the capacity of semiconductor memory has increased dramatically.
Many semiconductor memories are being used for various purposes. Correspondingly, the number of types of semiconductor memory is increasing.For example, RAM (random access memory) for image information processing is often dual-port type, which has a serial access port in addition to a random access port. This is becoming more and more common.

This RAM with a serial port allows input/output from a serial access port in addition to random access input/output (data writing and reading) to a memory cell array similar to a normal RAM. Data transfer from this serial port to the memory cell array is performed in units of the size of the serial port (for example, 512 bits). In such a RAM with a serial port, the random access port can be freely accessed even when data is being read or written to the serial port, so processing can be performed on the data while inputting and outputting data. Uses such as adding
For example, it is useful as an image memory.

D1 Problems to be Solved by the Invention By the way, in the dual port RAM as described above, when it is desired to rewrite only part of the contents of the serial port, the following inconvenience occurs.

That is, after serially inputting data to the serial port SP shown in FIG. 6 and writing the data only to a portion of the port S and Iw, the data of the serial port SP is transferred to the memory as shown in FIG. When data is transferred to a predetermined row Rn of the cell array MS (so-called write transfer), the data in the part of the memory cell array S that you do not want to rewrite will be lost. Even if S0 is rewritten, the contents of the remaining part S0 before data input remain unknown (see the shaded area in the figure), and the difference between serial port SP and memory cell array MS The data transfer between the memory cells is performed in units of serial port size, so all the recorded contents of the serial port size, including the content unknown portion SR6, are transferred and written as they are to the corresponding row Rn of the memory cell array MS. This is because it will be put away.

In this way, the preservation of data in areas other than the data rewritten area is not guaranteed, so image processing such as so-called multi-screen or picture-in-picture cannot be performed effectively, and if you try to rewrite only part of the screen, this rewriting There is a risk that the remaining part at the same horizontal position (same row) as the original image will be different from the original image.

The present invention was made in view of the above circumstances, and it is possible to input data through the serial port of a RAM with a serial port, even if only a part of the data smaller than the size of the serial port is rewritten, the remaining data cannot be written. The purpose is to provide a memory control method that allows the original data to be saved as is.

Means for Solving the E0 Problem In order to solve the above-mentioned problem, the memory control method according to the present invention inputs data through a serial port of a RAM equipped with a serial port, and inputs data to a predetermined point on a memory cell array. In the memory control method of transferring the input data to a row, prior to inputting the serial input data, the data of the predetermined row on the memory cell array is transferred to the serial port, and the data of the predetermined row is written. After inputting the serial input data to the serial port, the serial port data, in which only the portion corresponding to the serial input data has been rewritten, is transferred to the predetermined row on the memory cell array.

In the serial port before the F0 action serial input, the data of a predetermined row of the memory cell array, that is, the row to which the data in the serial port is transferred, is written in advance, so the serial input allows the data to be transferred to a size smaller than the serial port size. Even if a part of the data is rewritten, the data in the predetermined row is preserved as it was in the remaining part. Therefore, even by inputting data through the serial port,
Data rewriting of only a part of the memory cell array can be realized.

G. Embodiment The memory used in the memory control method according to the present invention is a so-called RAM with a serial port, which has a serial access port with a capacity of one row of the memory cell array in addition to a normal randomly accessible memory cell array. be.

Here, this serial port is capable of transferring memory contents to and from any one row of the memory cell array, and
Data can be input and output serially. A memory control method according to the present invention is a memory control method for inputting data through such a serial port and transferring the input data to a predetermined row on a memory cell array. An embodiment of the memory control method according to the present invention will be described below.
This will be explained with reference to FIGS. 1A to 1C.

First, in FIG. 1A, prior to the serial input operation of the data, the predetermined row Rn on the memory cell array MS is
data is transferred to the serial baud) SP. This predetermined row Rn is the row of the destination to which the next serially input data is transferred.

Next, desired data is serially input to the serial port SP into which the data of the predetermined row Rn has been written, and only a partial area S is rewritten as shown in FIG. In the remaining area 5ll11, the data of the predetermined row Rn is stored as is.

Finally, as shown in FIG. 1C, the data of the serial port SP, in which only the portions S and w corresponding to this serial input data have been rewritten, is transferred to the predetermined row Rn on the memory cell array MS.

Data transfer at this time is performed in units of serial port size, and all data in the serial baud) SP is transferred to the above-mentioned predetermined row Rn of the memory cell array MS, but the above rewriting in the serial baud) SP is not performed. part 5
Since the data of the original row Rn is stored in II6, substantially a part of the row Rn of the memory cell array MS (
Only the rewritten portion (corresponding to the rewritten portion SNw) is rewritten, and the original data of the other portions is preserved as is.

Here, when handling image data corresponding to a video signal of a normal rusk scan type display, when the above memory cell array is used as a so-called frame memory, 8
One row of the memory cell array corresponds to IH or one line (horizontal scanning line) of the screen. Now, the image data of the video signal is input/output from the serial port for each IH (one line), one frame is stored and displayed as a still image, and a new image is displayed at a desired part on the screen. FIG. 2 shows a time chart for controlling the memory with a serial port according to the procedure described above when realizing picture-in-picture, split-screen display, multi-screen display, etc.

At the time shown in Fig. 2, the serial baud) S
The serial input of image data of a predetermined line to P is completed, and time 1. to t3, data transfer (so-called write transfer, first
(corresponding to Figure C) is performed, and the series of input operations for the data of the predetermined line is completed.Next, a series of input operations for the data of the next line starts from time La, and from time t4 to t, Until then, the memory cell array M
The data of the next line of S is transferred to the serial port SP (so-called read transfer, corresponding to FIG. 1A),
Thereafter, from time t, input of the image data of the next line to the serial port SP (serial input, corresponding to FIG. 1B) is started. Similarly, after the serial input is completed, the above write transfer is executed, and the operations from A to C in FIG. 1 above are repeated as many times as necessary, starting with the above read transfer for the next line.
Here, in a normal RAM with a serial port, the serial port SP immediately after the above read transfer is in output mode (
Since the input/output common terminal is in a mode (in which it functions as an output terminal), for example, at time 1. from the end of the read transfer cycle to the start of serial input. Between t and t, there is a write transfer (
It is necessary to execute a so-called pseudo write transfer and switch the serial port to input mode.

As described above, the read transfer is performed between time t4 and time t prior to the serial input from , and the data of the line corresponding to the line to which data is to be input is transferred to the serial port SP. Then, perform serial input to the serial port SP to which this data has been transferred to rewrite only a portion of the data, and then transfer the data from the serial port SP to the memory cell array to rewrite the area other than the rewritten portion. By preserving the original data, so-called picture-in-picture, multi-screen, etc. can be easily realized.

By the way, the above-mentioned RAM with a serial port specifically has a configuration as shown in FIG. 3, for example. In FIG. 3, four memory cell arrays MS (64K x 4 bits) of 256 rows x 256 columns are provided, and each of these memory cell arrays MSO-M
Corresponding to S3, data registers 10 to 13 and serial input/output cover sofas 20 to 23 as serial ports are provided, respectively. Each serial input/output hippo sofa 2
Data input/output for 0 to 23 is via terminal 5D, respectively.
This is done via O-3D3. Also, memory cell array M
The SO-MS 3 includes a row decoder 30 and each column decoder 40.
43 enable random access, and data is input and output via terminals DDO to DD3 of input/output buffers 50 to 53 provided for each column decoder 40 to 43, respectively. Next, for example, for 8-bit address inputs A0 to A, row addresses and column addresses appear in a time-division manner, and these row addresses and column addresses are separated by the address buffer 31. The row address from address buffer 31 is sent to row decoder 30, while the column address is sent to each column decoder 40-43 and each data register 10-13, respectively.

Furthermore, so-called RAS (row address strobe) and CAS (column address strobe) signals are supplied to the clock generator 32 .
A clock generated from - is sent to the refresh address counter 33, and its count output is sent to the address buffer 31, and a so-called SAS (serial address strobe) signal is sent to each of the data registers 10 to 13. ing. Further, a ME/WE (memory enable/write enable) signal is sent to the write clock generator 34 and the transfer control circuit 35, and a TR10B (transfer enable/output enable) signal is sent to each of the buffers 50 to 53 and the transfer control circuit 35. ■ (serial port enable)
The signal is transferred to the transfer control circuit 35 and each of the buffers 2 mentioned above.
It is sent to 0-23.

Refer to FIGS. 4 and 5 for specific examples of timing generation circuits and time charts for various signals for causing such a RAM with a serial port to perform the operations of the embodiments of the present invention as described above. I will explain while doing so.

In FIG. 4, the horizontal pulse HP supplied to the timing generation circuit section is output periodically corresponding to one line scanning of the screen, and the vertical pulse VP is similarly outputted corresponding to one line scanning of the screen (
1 field). The counter 61 is supplied with the clock signal CLK as a count input and the horizontal pulse HP as a clear pulse, and the count output of the counter 61 is sent to the timing pattern ROM 62. The read/write control signal R/W is sent to the flip-flop 63, and the flip-flop 6 is clocked by the vertical pulse VP.
The 0-row address counter 64, which is configured to switch read/write to the memory at the cycle 3 by supplying the voltage to the clock 3, uses the horizontal pulse HP as a clock and is reset by the vertical pulse vP, and is reset by the vertical pulse vP. From the counter 64, for example, 8-bit addresses A0 to A
7 is taken out as the row address. Next, from the timing pattern ROM 62, the signals RAS, CAS,
TR10E, ME/WE, SE, etc. are output at predetermined timings, an example of which is shown in FIG. Each time 1++, Llffisulff in this FIG.
etc. are shown in units of clock periods, and RAM
Taking into account the access speed of , the scanning time of one line of the screen, the number of RAMs used in time division, etc., one clock period is, for example, about several hundred ns (nanoseconds).

In FIG. 5, time tl+""t12, time LIz~
t13 and time t+i to t14 are time L2 to L3, time t4 to t, and time t in FIG. 2, respectively.

This corresponds to each transfer cycle from t6 to t6. That is, time tl+””tl! In this case, the data in the serial port to which serial input was performed before the time is transferred to a predetermined row of the memory cell array (so-called write transfer), and the timing of the falling edge of the RAS signal is The row address is taken in at the timing of the fall of the CAS signal, and the column address is taken in at the falling edge of the CAS signal. The horizontal pulse HP is assumed to occur near the end of this write transfer cycle, and the row address counter 64 is counted up by this pulse HP, and the next row is designated from time t1□ to time t1. ,.

In the above, the data of the next row of the memory cell array is transferred (read transfer) to the serial port.

Here, the row address taken in at the timing of the falling edge of the RAS signal is determined by counting up the row address by the horizontal pulse HP, from time tll to t1.
Next, from time t13 to t14, a write transfer (so-called pseudo write transfer) that does not involve actual data transfer is executed. to switch the serial port to input mode. After that, from time t14, SA
Output of the S (serial address strobe) signal is started, and input (serial input) of image data of the rewritten portion regarding the next row to the serial port is started.

Next, after the above serial input is completed, if data is transferred to the predetermined row of the memory cell array (the next row above), in the predetermined row of the memory cell array, the part other than the part corresponding to the rewritten part is the original predetermined row. Data is written again, and only a portion of the memory cell array corresponding to the rewritten portion is rewritten. Therefore, even if only a part of the data in the memory cell array is rewritten by inputting data through the serial port, the remaining data can be saved, so that so-called picture-in-picture, multi-screen, etc. can be easily realized.

Note that the present invention is not limited to the above-mentioned embodiments; for example, the capacity of the memory cell array can be set arbitrarily, and the application of the RAM with a serial port is also limited to frame memories in the image processing field. Moreover, it can be easily applied to use as a memory for measurement and other general digital signal processing. In addition, various modifications can be made without departing from the gist of the present invention.

H0 Effects of the Invention According to the memory control method of the present invention, before serial input when serially input data is transferred to a predetermined row of the memory cell array, the data of the predetermined row of the memory cell array is written in advance into the serial port. By storing the data in the serial port, even if a part of the serial port is rewritten, the data in the above specified line will be saved in the remaining part as it was, and even when inputting data via the serial port, the memory Only part of the data in the cell array can be rewritten. Therefore, when used as an image memory, for example, functions such as so-called picture-in-picture and multi-screen display can be easily realized.

[Brief explanation of drawings]

1A to 1C are schematic diagrams for explaining one embodiment of the memory control method according to the present invention, FIG. 2 is a time chart for explaining the general operation, and FIG. 3 is a RAM with a serial port.
FIG. 4 is a block diagram showing the configuration for generating the timing of each control signal in FIG. 3. FIG. 5 is a block diagram showing the configuration for generating the timing of each control signal in FIG.
Signal timing charts, FIGS. 6 and 7, are schematic diagrams for explaining the conventional example. MS...Memory cell array SP...Serial ports 10-13...Data registers 20-23.50-53...Buffer 30...Row decoder 31...Address buffer 40-43...Column decoder

Claims (1)

[Scope of Claim] A memory control method for inputting data through a serial port of a RAM equipped with a serial port and transferring the input data to a predetermined row on a memory cell array, First, the data of the predetermined row on the memory cell array is transferred to the serial port, then the serial input data is input to the serial port to which the data of the predetermined row has been written, and finally the data corresponding to this serial input data is transferred. A memory control method characterized in that data of a serial port whose only part has been rewritten is transferred to the predetermined row on the memory cell array.