JP2605058B2 - Video processing system - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a video having a first dual-port memory for storing an image before processing and a second dual-port memory for storing an image after processing. Regarding the processing system.

[Background of the invention and its problems]

Dual port memory is high-speed serial access memory
With SAM, transfer between RAM and SAM, and input / output in SAM in a predetermined bit unit can be performed in one clock,
It is suitable for real-time display and processing of images.

However, when an image before processing and an image after processing are stored in the dual port memory, a delay time due to a delay element occurs in the processing system, and the first dual port memory for storing the image before processing is generated. The transfer and refresh cycle must be set separately from the transfer and refresh cycle for the second dual-port memory holding the processed image. Therefore, separate transfer and refresh circuits are required for each of the plurality of memories, which complicates the circuit configuration and hinders reduction in manufacturing cost. In general, separate circuits are also required for addressing the SAMs of the first and second dual-port memories. However, in this case, the addresses to be specified at the same time are the first and second addresses only for one processing data. Therefore, it is difficult to shape up the entire configuration.

[Object of the invention]

SUMMARY OF THE INVENTION The present invention has been made in order to solve such a conventional problem. A video processing system capable of simplifying a circuit for transferring, refreshing, and addressing a dual port memory for an image before and after processing is provided. The purpose is to provide.

[Summary of the Invention]

A video processing system according to the present invention transfers and refreshes both dual-port memories during a common period between a horizontal blank in displaying an image before processing and a horizontal blank in displaying an image after processing. In the addressing related to the SAM, the writing address designation to the SAM of the dual port memory for the image before processing is performed in the first half of the common period, and the writing from the SAM to the dual port memory for the image after processing is performed in the second half. The address is specified.

(Example of the invention)

Next, an embodiment of a video processing system according to the present invention will be described with reference to the drawings.

In FIG. 1, the image processing system has a plurality of dual port memories 1 to 4 (only four are shown in the figure).
And the I / O of SAM1S to 4S of each dual port memory is connected to the input side of the selector SEL1. The output of the selector SEL1 is sent to the processing system of the video processing system, and after being subjected to processing such as convolution processing, operation such as spatial filtering, and feature extraction, is returned to the SAM of one of the dual port memories. Data input from the processing system to the SAM of the dual-port memory is performed via bus buffers BF1 to BF4, and SA
M controls the bus buffer so that input data is not applied to the SAM I / O in the read mode. A status register SR (a status register is provided for each dual port memory in the figure) via a selector SEL2 at a WE (line enable) terminal of the dual port memory. Are connected to each other and are easily displayed.), And each selector SEL2 is connected to the MP.
Controlled by U. The bus buffer BF1
~ BF4 is controlled by the status register SR to protect the dual port memory, but the SOE (serial out enable) terminal (not shown) of the dual port memory is also controlled by the status register, and the data input / output terminal (shown) (Omitted) to protect the dual port memory with high impedance.

The dual-port memory 1 is provided for a total of 5 frames, for example, 3 frames for input (corresponding to each color of RGB), 1 frame for output, and 1 frame for work area, for a total of 5 frames. The use can be appropriately changed by switching.

Here, the description proceeds assuming that the dual-port memory 1 is used as a memory for input, that is, a memory for holding an image before processing, and the dual-port memory 4 is used for output, that is, a memory for holding an image after processing. .

Dual port memory 1 sequentially stores data for one raster
Transfer from RAM to SAM, data in SAM are sequentially selected by SEL
It is sent to the processing system via 1. On the other hand, the dual-port memory 4 sequentially writes the data processed by the processing system into the SAM, and transfers the data to the RAM when the data for one raster is accumulated in the SAM. And dual port memory 1
The address in the RAM of the data to be transferred to the SAM of the dual port memory 4 is ahead of the address in the RAM to be transferred from the SAM of the dual port memory 4 by one raster.

Further, the timing of writing data from the RAM of the dual port memory 1 to the SAM depends on the SA of the dual port memory 4.
From the timing of writing data from M to RAM, it will advance more than the delay time due to the delay element in the processing system,
The transfer timings also do not match.

On the other hand, video processing systems generally have the function of displaying images in memory, such as serial out from SAM and SAM.
Serial in is performed in synchronization with the display timing of the CRT. The timing signal for CRT display usually has a horizontal blank, and no display is performed during this period.
Therefore, during this period, even if the transfer and refresh of the dual port memory are performed, the display is not affected. This horizontal blank occurs for each raster and the dual port memory 1,
In No. 4, there is a time shift corresponding to the delay of the processing system.

FIG. 2 shows the horizontal blank HBR in the timing signal of the dual port memory 1 and the horizontal blank HBW in the timing signal of the dual port memory 4 in parallel.
And both have a common period c. If the transfer and refresh of all the dual port memories are performed during this common period c, the transfer and refresh can be performed at the same timing without affecting the display image at all. Therefore, all the dual port memories can be transferred and refreshed by a common circuit, so that the circuit configuration can be simplified and the manufacturing cost can be reduced.

FIG. 3 shows a waveform diagram similar to that of FIG. 2 with the common period extended for ease of understanding. In the first half of this common period, the transfer from the SAM of the dual port memory 2 to the RAM is performed. Specify the addresses CW255, CW0, CW1,..., And transfer addresses CR0, CR1, from the RAM of the dual port memory 1 to the SAM in the latter half.
CR2 ... is specified. In the dual port memory 1, the data of the raster before the raster to be originally read is transferred to the SAM by the address specification in the first half, but the data in the SAM is the data of the next raster, that is, the data to be read originally by the address specification in the second half. Rewritten.
In the dual-port memory 4, the data in the SAM is written to the normal RAM address in the first half, and the data is written to the next raster address in the second half. Will be corrected in the first half.

The address is specified by, for example, an address counter. If the data is advanced in the first half and the second half of the common period of the horizontal blank as described above, a common address counter can be used for the input / output dual port memory, and the circuit configuration Can be simplified and the manufacturing cost can be reduced.

[Effects of the Invention] As described above, the video processing system according to the present invention includes:
During the common period between the horizontal blank in the display of the image before processing and the horizontal blank in the display of the image after processing, transfer and refresh of both dual-port memories are performed, and addressing for SAM is performed in the first half of the common period. Specify the write address to the SAM of the dual port memory for the previous image, and specify the write address from the SAM of the dual port memory for the processed image in the second half. Transfer, refresh, and address designation circuits of the dual port memory can be simplified.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a partial configuration of a video processing system, FIG. 2 is a waveform diagram of a timing signal showing transfer and refresh cycles of a dual port memory, and FIG. FIG. 3 is a waveform diagram of a timing signal indicating a cycle. 1-4: Dual port memory, 1S-4S: SAM, SEL
1, SEL2 ... Selector, BF1 to BF4 ... Bus buffer, WE ...
... Write enable end, SR ... Status register, d
... delay, c ... common period, HBR ... horizontal blank of input dual port memory, HBW ... horizontal blank of output dual port memory.

Claims (2)

(57) [Claims] 1. An image processing system comprising a first dual-port memory for holding an image before processing and a second dual-port memory for holding an image after processing for displaying an image before processing. Wherein the dual port memory is transferred and refreshed during a common period between the horizontal blank in the timing signal and the horizontal blank in the processed timing signal. 2. An image processing system comprising a first dual-port memory for holding an image before processing and a second dual-port memory for holding an image after processing for displaying an image before processing. During the common period between the horizontal blank in the timing signal of FIG. 1 and the horizontal blank in the timing signal for displaying the processed image, the write address to the SAM of the first dual port memory is specified in the first half and the second A video processing system wherein a write address from a SAM of a dual port memory is specified.