JPH0197990A - Video processing system - Google Patents

Abstract

PURPOSE: To simplify a circuit by transferring and refreshing the contents of both dual port memories in common period between horizontal blanking in the display of an unprocessed picture and that in the display of a processed picture. CONSTITUTION: In the case of displaying the horizontal blanking HBR of a timing signal from a dual port memory 1 and the horizontal blanking HBW of a timing signal from a dual port memory 4 in parallel, the horizontal blanking period is longer than the delay (d) of a processing system and both the blanking parts have a common period (c). When the transfer and refreshing of all the dual port memories 1 to 4 in the common period (c), the transfer and refreshing can be executed at the same timing without exerting any influence upon a display picture. Consequently transfer and refreshing can be executed in the common period of all the dual port memories 1 to 4 and the circuit constitution can be simplified.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention provides an image processing system that includes a first dual port memory that holds an unprocessed image and a second dual port memory that holds an image that has been processed. Regarding processing systems.

[Background of the invention and its problems]

Dual port memory is high-speed serial access memory S
It has an AM, and transfer between the RAM and SAM, and input/output in units of predetermined bits in the SAM can be performed in one clock, which is suitable for real-time display and processing of images.

However, when holding both the unprocessed image and the processed image in the dual port memory, a delay time occurs due to delay elements in the processing system, and the first dual port memory holding the unprocessed image The transfer, refresh cycle and the transfer, refresh cycle for the second dual port memory that holds the processed image had to be set separately. Therefore, separate transfer and refresh circuits are required for each of the plurality of memories, which complicates the circuit configuration and becomes an obstacle to reducing manufacturing costs. Additionally, separate circuits were generally required to specify addresses for the SAMs of the first and second dual-port memories; Because of the differences in memory, shaving up the entire configuration was a difficult problem.

[Purpose of the invention]

The present invention was created and devised to solve these conventional problems, and is a video processing method that can simplify the dual-port memory transfer, refresh, and addressing circuits for pre-processed and post-processed images. The purpose is to provide a system.

[Summary of the invention]

The video processing system according to the present invention transfers and refreshes both dual port memories during a common period of horizontal blanking in the display of the unprocessed image and horizontal blanking in the display of the processed image. In addition, regarding the address specification regarding the SAM, in the first half of the common period, writing address to the dual port memory SAM for the image before processing is specified, and in the second half, writing address from the dual port memory SAM for the image after processing is specified. This is used to specify addresses.

[Embodiments of the invention]

Next, an embodiment of the video processing system according to the present invention will be described based on the drawings.

In FIG. 1, the video processing system includes a plurality of dual port memories 1 to 4 (only 41m is shown in the figure).
, and Ilo of SAMIS to 4S of each dual port memory is connected to the input side of selector 5ELI.

The output of the selector 5ELI is sent to the processing system of the video processing system, subjected to processing such as convolution processing, spatial filter calculation, feature extraction, etc., and then returned to the SAM of one of the dual port memories. Data input from the processing system to the dual port memory SAM is via the path buffer BF.
This is done via I to BF4, and the pass buffer is controlled so that input data cannot be applied to Ilo of the SAM when the SAM is in read mode. Selector 5 is attached to the WE (lined enable) terminal of the dual port memory.
Status register SR (in the figure, a status register is provided for each dual port memory, but this is an easy-to-understand representation of one status register branched and connected to each dual port memory. ) are connected, and each selector 5EL2 is connected to M
Controlled by PU. The path buffers BFI to BF4 are controlled by the status register SR and protect the dual port memory.
Furthermore, the SOE (serial out enable) #a (not shown) of the dual port memory can also be controlled by the status register, and the data input/output terminal (not shown) is set to high impedance at appropriate times to protect the dual port memory.

The dual port memory 1 is provided with a total of 5 frames, for example, 3 frames for input (corresponding to each ROB color), 1 frame for output, and 1 frame for work area. Pass buffer BFI~B
By switching F4, its use can be changed as appropriate.

Here, we will proceed with the explanation assuming that the dual port memory 1 is used for input, that is, as a memory that holds images before processing, and that the dual port memory 4 is used for output, that is, as a memory that holds images after processing. .

Dual port memory 1 sequentially stores data for one raster
The data is transferred from the AM to the SAM, and the data in the SAM is sequentially sent to the processing system via the selector 5ELL. On the other hand, the dual boat memory 4 sequentially SAs the data that has been processed by the processing system.
M is written, and when one raster worth of data is accumulated in the SAM, the data is transferred to the RAM. The address in the RAM of the data should be transferred from the SAM of dual port memory 4! ) is one raster ahead of the address in RAM.

Roughly speaking, the timing for writing data from the RAM of dual port memory 1 to SAM is as follows:
The timing of writing data from the SAM to the RAM is delayed by more than the delay time caused by delay requirements within the processing system, and the timing of the transfer also does not match.

On the other hand, video processing systems generally have a function to display images in memory, and serial out from SAM, S
Serial input to AM is performed in synchronization with the display timing of the CRT. The timing signal for CRT display usually has a horizontal blank, during which no display is performed. Therefore, even if the dual port memory is transferred or refreshed during this period, the display will not be affected. This horizontal blanking occurs for each raster, and in the dual port memory 1.4, there is a time lag corresponding to the delay of the processing system.

Figure 2 shows horizontal blank HBR in the timing signal of dual port memory 1 and horizontal blank HBW in the timing signal of dual port memory 4 in parallel. is also long, and both have a common period C. If all the dual port memories are transferred and refreshed during this common period C, the transfer and refresh can be performed at the same timing without affecting the displayed image at all. Therefore, all dual-port memories can be transferred and refreshed using a common circuit, simplifying the circuit configuration and reducing manufacturing costs.

Figure 3 shows a waveform diagram similar to Figure 2, with the common period expanded for ease of understanding. Specify addresses CW255, CWO, CWl, etc., and in the second half, write S from RAM of dual port memory 1.
Transfer addresses CRO, CRI, CR2, . . . to AM are specified. In dual port memory 1, by specifying the first half of the address, the data of the raster before the raster that should be read out can be transferred to the SAM, but by specifying the second half of the address, the data in the SAM can be transferred to the data of the next raster,
In other words, the data is rewritten to the data that should originally be read. In the dual port memory 4, the data in the SAM is written to the regular RAM address in the first half, and the data is written to the next raster address in the second half. Corrected in the first half of the horizontal blank.

For example, the address is specified by an address counter, and if the data is incremented in the first half and second half of the horizontal blank common period as described above, a common address counter can be used for the input/output dual port memory, and the circuit configuration It is possible to simplify the process and reduce manufacturing costs.

〔Effect of the invention〕

As described above, the video processing system according to the present invention transfers and refreshes both dual port memories during a common period between a horizontal blank in displaying an unprocessed image and a horizontal blank in displaying a processed image, and Addressing for the SAM is such that in the first half of the common period, writing addresses to the dual port memory SAM for images before processing are specified, and in the second half, writing addresses from the dual port memory SAM for images after processing are specified. Since write-in addressing is performed, it has the excellent effect of simplifying the circuits for transferring, refreshing, and addressing the dual port memory for holding the image of the urn before processing.

[Brief explanation of the drawing]

Figure 1 is a block diagram showing the configuration of a part of the video processing system, Figure 2 is a waveform diagram of timing signals showing transfer and refresh cycles of dual port memory, and Figure 3 is a diagram of addressing for SAM of dual port memory. FIG. 8 is a waveform diagram of Tying Gui No. 8 showing a cycle. 1 to 4...Dual port memory, IS to 4S...
SAM, 5ELL, 5EL2...Selector, BF1~
BF4...pass buffer, WE...write enable end, SR...status register, d...delay,
C...Common period, HBR...Horizontal blank of input side dual port memory, HBW...Horizontal blank of output side dual port memory.

Claims (2)

[Claims] (1) Timing for displaying an unprocessed image in a video processing system that includes a first dual port memory that holds an unprocessed image and a second dual port memory that holds an unprocessed image. A video processing system characterized in that both dual port memories are transferred and refreshed during a common period between a horizontal blank in the signal and a horizontal blank in a timing signal for display after processing. (2) Timing for displaying an unprocessed image in a video processing system that includes a first dual port memory that holds an unprocessed image and a second dual port memory that holds an unprocessed image. During the common period between the horizontal blank in the signal and the horizontal blank in the timing signal for displaying the processed image, the first half specifies the write address to the SAM of the first dual port memory, and the second half specifies the write address to the SAM of the first dual port memory. A video processing system characterized in that a write address from a SAM of a port memory is specified.