JPH04146483A - Display controller - Google Patents

Abstract

PURPOSE:To shorten time in which a CPU and a bus are occupied to rewrite a datum by providing a serial copying controlling means which controls in such a way that it fetches the datum for displaying read out from the serial port of one frame buffer from the serial port of the other frame buffer and writes it to a RAM. CONSTITUTION:The datum for displaying is outputted from the serial port of the frame buffer 8 in synchronism with a horizontal synchronizing signal H-SYNC, and is displayed on the screen of the CRT. A VRAM controller 4 executes a dummy write transmission DW to the frame buffer 11 with the datum transfer cycle next to the receiving of a copy command. Thus, the datum for displaying can be fetched from the serial port of the frame buffer 11. The VRAM controller 4 gives an address corresponding to the displayed datum to the frame buffer 11 when the frame buffer 11 reads the displayed datum. Therefore, all of one screen can be copied with one vertical synchronizing cycle of L3-L2 shown in figure.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a display control device, and more specifically, the present invention relates to a display control device, and more specifically, the display control device includes a pair of frame buffers.

The present invention relates to a display control device that uses one frame buffer for reading display data, uses the other frame buffer for rewriting data, and alternately switches these roles to control changes in one screen display.

[Prior Art] An example of a conventional display control device of this type is shown in FIG.

This display control device 51 includes a CPU 52, a VRAM controller 54 connected to the CPU 52 via a bus 3, and an address line A and a control line for the VRAM controller 54. A pair of frame buffers 8 and 11 are connected to the CPU 2 via a bus 3, and a synchronization signal 5YN.
The CRT controller 5 outputs C, and a changeover switch 12 selects one of a pair of frame buffers 8 and 11 to output display data to the CRT.

The frame buffer 8 is composed of a dual port memory for images, and has a RAM 6 and a SAM 7 inside.

Further, the frame buffer 11 is also constituted by a dual port memory for images, and has a RAM 9 and a SAMIO therein.

In the state shown in FIG. 3, the display data (2) read from the serial port of the frame buffer 8 is sent to the CRT via the changeover switch 12 and displayed on the screen.

During this time, the CPU 2 uses the RAM 6 of the frame buffer 8.
The data is read out, changes are made to necessary portions, and the data is written to the RAM 9 of the other frame buffer 11.

When the writing is finished, the CPU 2 switches the changeover switch 12
and sends the display data read from the serial port of the frame buffer 11 to the CRT. Therefore,
The contents of RAM9 are displayed on the screen.

Next, when it is desired to change the display on the screen, the CPU 2 reads out the contents of the RAM 9 of the frame buffer 11, makes changes, writes the contents to the RAM 6 of the frame buffer 8, and then switches the changeover switch 12.

In this way, by alternately switching the pair of frame buffers 8 and 11, data rewriting is prevented from appearing as flickering on the CRT screen.

[Problems to be Solved by the Invention] In the conventional display control device 51 described above, even when changing a part of the screen, it is necessary to write the contents of the RAM of the frame buffer for one screen.

However, since one screen's worth of data is extremely large, C
There is a problem that the PU 52 and bus 3 are occupied for a long time, resulting in a large system overhead.

SUMMARY OF THE INVENTION An object of the present invention is to provide a display control device in which unchanged data is transferred directly between a pair of frame buffers without going through a CPU or a bus, thereby reducing system overhead. It is in.

[Means for Solving the Problems] A display control device of the present invention has a pair of frame buffers using dual port memory for images, reads display data from the serial port of one of the frame buffers, and reads data for display from the serial port of one of the frame buffers. In a display control device that controls changes in screen display by rewriting data in the RAM of the other frame buffer and alternating the role of reading and rewriting, the data for display being read from the serial port of one frame buffer. The configuration is characterized in that it includes a serial copy control means for controlling the other frame buffer so as to take in data from the serial port of the other frame buffer and write it into its RAM.

[Function] The serial port of the dual port memory for images is
It is now possible to import serial video signals from cameras, etc. Therefore, by utilizing this, it becomes possible to directly import the display data outputted from one frame buffer into the other frame buffer.

That is, the serial copy control means controls the other frame buffer so that the display data output from the serial port of one frame buffer is fetched from the serial port of the other frame buffer and copied. This serial copy is completed in one vertical period of the CRT.

Therefore, the CPU only needs to rewrite the data in the changed portion.

As a result, the time that the CPU and bus are occupied for rewriting data is reduced, and system overhead is reduced.

[Example] Hereinafter, the present invention will be explained in more detail with reference to Examples shown in the drawings. Note that this invention is not limited to this.

FIG. 1 is a block diagram of a display control device 1 according to an embodiment of the present invention.

This display control device 1 includes a CPU 2 and its CPU.
A VRAM controller 4 is connected to U2 via a bus 3, and a VRAM controller 4 is connected to the VRAM controller 4 via an address line A and a control line C, and is connected via a bus 3 to a CPU 2.
Frame buffer 8.11 connected to 8.11 and synchronization signal 5
It is equipped with a CRT controller 5 that outputs YNC.

The CPU 2 issues a switching command, a copy command,
A write command is issued to the VRAM controller 4.

When the VRAM controller 4 receives a switching command from the CPU 2, if one frame buffer is outputting display data and the other frame buffer is not outputting display data, vice versa, the VRAM controller 4 outputs display data from one frame buffer. 9In order to output display data from the other frame buffer without outputting display data from the buffer,
Controls both frame buffers 8 and 11.

Furthermore, when a copy command is given from the CPU 2, the operation of the frame buffer that is outputting the display data continues as it is, and the other frame buffer is controlled to read the display data from its serial port. do. In other words, serial copying is performed.

Also, when a write command is given from CPU2, the R of the frame buffer that is not outputting display data is
The frame buffer is controlled so that the CPU 2 can write data to the AM.

Frame buffers 8, 11 and CRT controller 5
has the same configuration as the conventional one.

Next, the operation will be explained with reference to FIG. The operation shown here is to output display data from the frame buffer 8 and display it on the CRT, during which time the contents of the RAM of the frame buffer 11 are partially rewritten, and after the rewriting, the display data is output from the frame buffer 11. The screen display on the CRT is thereby changed.

First, as shown in FIG. 2, the horizontal synchronization signal H-SYNC
At the same time, display data is output from the serial port of the frame buffer 8, and is displayed on the CRT screen. The other frame buffer 11 is not doing anything.

The CPU 2 first issues a copy command to the VRAM controller 4.

The VRAM controller 4 performs a pseudo write transfer W to the frame buffer 11 in the next data transfer cycle after receiving the copy command.

This allows the display data to be taken in from the serial port of the frame buffer 11. VRA
The M controller 4 transfers the display data to the frame buffer 1.
1 gives an address corresponding to the display data to the frame buffer 11. In this way, one entire screen is copied in one vertical synchronization period from 3 to L2 in the figure.

When the CPU 2 finishes copying one entire screen from the frame buffer 8 to the frame buffer 11, it issues a write command to the VRAM controller 4.

The VRAM controller 4 writes C in response to the write command.
This allows the PU2 to access the RAM 9 of the frame buffer 11 and rewrite data. This results in
Some data is rewritten, as shown in L3 shown in FIG.

After rewriting the data, the CPU 2 issues a switching command to the VRAM controller 4.

In response, the VRAM controller 4 outputs display data from the serial port of the frame buffer 11 and controls the frame buffer 8 so that it does not output display data.

In this way, the CRT screen will be changed.

As can be understood by referring to FIG. 2, the period during which the CPU 2 and the bus 3 are occupied for rewriting data is only a period during which data that requires modification is written, that is, a short period after the write command is issued. Therefore, system overhead will be reduced.

[Effects of the Invention] According to the display control device of the present invention, since the display data output from one frame buffer is read from the other frame buffer or its serial port and written to the RAM, only the data to be changed is transferred from the parallel port. It is sufficient to write data to RAM, which reduces the time occupied by the CPU, bus, etc. for data modification, and reduces system overhead.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a display control device according to an embodiment of the present invention, FIG. 2 is a time chart for explaining the operation of the display control device shown in FIG. 1, and FIG. 3 is a diagram of a conventional display control device. It is a block diagram of an example. (Explanation of symbols) 1... Display control device 2... CPU 3... Bus 4... VRAM controller 5... CRT controller 6.9... RAM 7° 10... SAM 8° 11...Frame buffer.

Claims (1)

[Claims] 1. A pair of frame buffers using dual port memory for images is provided, and display data is read from the serial port of one of the frame buffers, while data in the RAM of the other frame buffer is read. In a display control device that controls changes in screen display by alternating the roles of reading and rewriting, the display data being read from the serial port of one frame buffer is transferred to the serial port of the other frame buffer. 1. A display control device comprising serial copy control means for controlling the other frame buffer so as to read data from the other frame buffer and write it to its RAM.