JPS58208845A - Overlap display system - Google Patents

Overlap display system

Info

Publication number
JPS58208845A
JPS58208845A JP9286382A JP9286382A JPS58208845A JP S58208845 A JPS58208845 A JP S58208845A JP 9286382 A JP9286382 A JP 9286382A JP 9286382 A JP9286382 A JP 9286382A JP S58208845 A JPS58208845 A JP S58208845A
Authority
JP
Japan
Prior art keywords
crtc
synchronism
crt
display
initialization
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9286382A
Other versions
JPH0373897B2 (en
Inventor
Kinya Maruko
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP57092863A priority Critical patent/JPH0373897B2/ja
Publication of JPS58208845A publication Critical patent/JPS58208845A/en
Publication of JPH0373897B2 publication Critical patent/JPH0373897B2/ja
Anticipated expiration legal-status Critical
Application status is Expired - Lifetime legal-status Critical

Links

Abstract

PURPOSE: To have an overlap display on the same display screen, by securing synchronism between CRT controllers of different specifications which are controlled by a proper CRT controller such as a character display and a graphic display respectively.
CONSTITUTION: A parameter is set to a master CRTC 12 to perform an initialization. Then a parameter is set to a slave CRTC 13 to perform an initialization. The CRTC 12 is actuated, and the synchronism is applied to the CRTC13 with an M-VSYNC signal of the 1st frame. Then the CRTC 13 is started after detecting the synchronism. In an interlace mode the operation is kept halt until the 2nd frame of the CRTC 13 overlaps the 1st frame of the CRTC 12, and then the CRT is started. In such a way, the synchronism is obtained between CRT controllers of different specifications and then displayed on the same display.
COPYRIGHT: (C)1983,JPO&Japio
JP57092863A 1982-05-31 1982-05-31 Expired - Lifetime JPH0373897B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57092863A JPH0373897B2 (en) 1982-05-31 1982-05-31

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57092863A JPH0373897B2 (en) 1982-05-31 1982-05-31

Publications (2)

Publication Number Publication Date
JPS58208845A true JPS58208845A (en) 1983-12-05
JPH0373897B2 JPH0373897B2 (en) 1991-11-25

Family

ID=14066260

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57092863A Expired - Lifetime JPH0373897B2 (en) 1982-05-31 1982-05-31

Country Status (1)

Country Link
JP (1) JPH0373897B2 (en)

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60135985A (en) * 1983-12-26 1985-07-19 Hitachi Ltd Display controller
USRE33922E (en) * 1984-10-05 1992-05-12 Hitachi, Ltd. Memory circuit for graphic images
US5175838A (en) * 1984-10-05 1992-12-29 Hitachi, Ltd. Memory circuit formed on integrated circuit device and having programmable function
JPH06161414A (en) * 1993-06-14 1994-06-07 Hitachi Ltd Display control system
US5424981A (en) * 1984-10-05 1995-06-13 Hitachi, Ltd. Memory device
US5448519A (en) * 1984-10-05 1995-09-05 Hitachi, Ltd. Memory device
US5592649A (en) * 1984-10-05 1997-01-07 Hitachi, Ltd. RAM control method and apparatus for presetting RAM access modes
US5923591A (en) * 1985-09-24 1999-07-13 Hitachi, Ltd. Memory circuit
US6028795A (en) * 1985-09-24 2000-02-22 Hitachi, Ltd. One chip semiconductor integrated circuit device having two modes of data write operation and bits setting operation

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5582362A (en) * 1978-12-18 1980-06-21 Hitachi Ltd Operation processing unit

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5582362A (en) * 1978-12-18 1980-06-21 Hitachi Ltd Operation processing unit

Cited By (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60135985A (en) * 1983-12-26 1985-07-19 Hitachi Ltd Display controller
US5610622A (en) * 1983-12-26 1997-03-11 Hitachi, Ltd. Display control device
US5606338A (en) * 1983-12-26 1997-02-25 Hitachi, Ltd. Display control device
US5523973A (en) * 1984-10-05 1996-06-04 Hitachi, Ltd. Memory device
US5424981A (en) * 1984-10-05 1995-06-13 Hitachi, Ltd. Memory device
US5448519A (en) * 1984-10-05 1995-09-05 Hitachi, Ltd. Memory device
US5450342A (en) * 1984-10-05 1995-09-12 Hitachi, Ltd. Memory device
US5475636A (en) * 1984-10-05 1995-12-12 Hitachi, Ltd. Memory device
US5493528A (en) * 1984-10-05 1996-02-20 Hitachi, Ltd. Memory device
US5499222A (en) * 1984-10-05 1996-03-12 Hitachi, Ltd. Memory device
US6359812B2 (en) 1984-10-05 2002-03-19 Hitachi, Ltd. Memory device
US5592649A (en) * 1984-10-05 1997-01-07 Hitachi, Ltd. RAM control method and apparatus for presetting RAM access modes
US5175838A (en) * 1984-10-05 1992-12-29 Hitachi, Ltd. Memory circuit formed on integrated circuit device and having programmable function
USRE33922E (en) * 1984-10-05 1992-05-12 Hitachi, Ltd. Memory circuit for graphic images
US5719809A (en) * 1984-10-05 1998-02-17 Hitachi, Ltd. Memory device
US5781479A (en) * 1984-10-05 1998-07-14 Hitachi, Ltd. Memory device
US5838337A (en) * 1984-10-05 1998-11-17 Hitachi, Ltd. Graphic system including a plurality of one chip semiconductor integrated circuit devices for displaying pixel data on a graphic display
US6643189B2 (en) 1984-10-05 2003-11-04 Hitachi, Ltd. Memory device
US5923591A (en) * 1985-09-24 1999-07-13 Hitachi, Ltd. Memory circuit
US6028795A (en) * 1985-09-24 2000-02-22 Hitachi, Ltd. One chip semiconductor integrated circuit device having two modes of data write operation and bits setting operation
JPH06161414A (en) * 1993-06-14 1994-06-07 Hitachi Ltd Display control system

Also Published As

Publication number Publication date
JPH0373897B2 (en) 1991-11-25

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