JPH0340057A - Data transfer device - Google Patents

Abstract

PURPOSE:To exactly execute the transfer processing of data even in the case of a data transfer device whose DMA processing is slow by generating a control signal for outputting the data to a data bus after ending a DMA transfer, in the case a DMA request signal is generated at the time of DMA transfer. CONSTITUTION:Data in a second memory is written in an input/output port at every one byte by synchronizing with a control signal of a prescribed period inputted from a memory control circuit 2. Subsequently, when all the data stored in a second memory are outputted, a request signal of a DMA transfer is sent out of the memory control circuit 2, and as a result, the DMA transfer of the number of designations and the data is executed to a second memory from a first memory. Also, after the request signal of the DMA transfer is sent out, the generation of the control signal outputted from the memory control circuit 2 is executed after the DMA transfer is ended. In such a way, a transfer processing of the data at the time of DMA transfer is executed exactly, and a correct data transfer can be executed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a data transfer device, and particularly to improving memory access timing during DMA transfer.

[Conventional technology]

As such a data transfer device, there is one shown in FIG. 3, for example. In the figure, 1 is the host microcomputer that controls the entire device, and 2 is the DMA between the host microcomputer 1.
Request signal (DREQ) and DMA permission signal (XDACK
) and the dual baud) DRA described later.
M (hereinafter referred to as DP-DRAM), a memory control circuit 3 is a DP-DRAM, and a RAM (random
It is assumed that the memory device is composed of a serial access memory (access memory) section 31 and a SAM (serial access memory) section 32, and a 2-by-1 data register on the SAM section 3. 4
1 is the data bus on the RAM section 3, and 5 is the data bus on the SAM section 3.
It is a data bus for the upper part 2 of the RAM part, and 1 AM for the upper part of the RAM part 3.
It has three ports and two ports, each of which is configured so that they can be accessed asynchronously.

Further, although the data transfer rate on the data bus 4 is not particularly specified, the data transfer rate on the data bus 5 is specified to a certain value, and the data transfer rate from the memory control circuit 2 to the SA
It is assumed that this is uniquely determined by the serial access memory strobe (hereinafter referred to as SAS) input to the M section 3.

The operation of the above configuration will be explained with reference to the time chart shown in FIG. Now, with the upper 2 bytes of data stored in SAM section 3, DP-DRAM3 is
When the conditions for permitting the input/output operation of the AM section 3 upper section 2 real access port are satisfied, the SAS of a certain period (to) is manually input from the memory control circuit 2 to the SAM section 3 upper section 2. . SAM section 3 upper 2 data bus 5
Data is output for each byte at the rising edge of SAS ((c) and (d) in FIG. 4).

Now, when the SAS is powered down m times, all 2-byte data on the SAM section 3 is output to the data bus 5 ((c) and (d) in FIG. 4). On the other hand, the next m bytes of data are R
1 on the AM section 3 2 on the SAM section 3 A DMA request signal for performing MA transfer is sent from the memory control circuit v42 to the host microcomputer 1 ((A) in FIG. 4. m bytes in (C)) Occurs at the falling edge of the eye's SAS.) When the host microcomputer 1 receives this signal, it sends a DMA permission signal to the memory control circuit 2, and m bytes of new data on the upper part of the SAM section 3 is transferred ((in Fig. 4)).
b) 1+). Thereafter, the signals are sequentially outputted to the data bus 5 by SAS at a constant period.

[Problem to be solved by the invention]

By the way, in the data transfer device described above, the SAM
After all the data in the bytes in part 3 and part 2 have been transferred, the RA
DMA transfer of data is performed between the M section 3 upper 1 AM section 3 upper section 2, but when the DMA request signal generated at the falling edge of the m-th byte SAS is sent to the host microcomputer 1, If the host microcomputer 1 is executing other processing, the processing for the DMA request signal will be delayed, and the sending of the DMA permission signal will also be delayed. SAS is input to the SAM unit 3. Therefore, data unrelated to the data that should be output is output to the data bus 5 (A in (d) in Figure 4), and the subsequent The problem was that there was always a 1-byte delay in the output data of This poses a problem in that it imposes restrictions and impedes cost reduction.

The present invention was made in order to solve the conventional problems as described above, and it is possible to accurately perform data transfer processing during DMA transfer in a host microcomputer with slow DMA processing, and to ensure correct data transfer. The purpose of the present invention is to provide a data transfer device that can perform the following steps.

[Means to solve the problem]

A data transfer device according to the present invention includes a first memory and a second memory that are capable of DMA transfer of memory contents to each other, and has a transfer rate for reading or writing data to a human output port of the second memory. is a data transfer device defined by a control signal, which generates the control signal so as to keep the transfer rate at a constant value during normal transfer, and which transfers data from the first memory to the second memory. D to perform DMA transfer to
A memory control circuit is provided which generates the control signal after the DMA transfer is completed when the MA transfer request signal is generated,
Furthermore, the first memory and the second memory are configured with dual-port DRAMs housed in the same package, and the first memory is a random access memory,
An even better effect is achieved if the second memory is a serial access memory and the control signal is a serial access memory strobe signal.

[For production]

In the data transfer device of the present invention, data in the second memory is written to the input/output port byte by byte in synchronization with a constant cycle control signal input from the memory control circuit. When all the data stored in the second memory has been output, a request signal for DMA transfer is sent from the memory control circuit, and as a result, the specified number of data is transferred from the first memory to the second memory. DMA transfer of data is performed.

Furthermore, after the DMA transfer request signal is sent, the control signal output from the memory control circuit is generated after the DMA transfer is completed, so that the correct data after the transfer is transferred to the second
memory is written to the input/output port.

〔Example〕

Hereinafter, one embodiment of the present invention will be described based on the drawings. FIGS. 1(a) and 6) are block diagrams showing the generation of SAS, which is a control signal, in the memory control circuit which is the main part of the present invention, and time charts showing its operation. Further, FIG. 2 is a time chart showing the operation of the device during data transfer.

Note that other components of the apparatus and their functions are the same as those shown in FIG. 3, so detailed explanation thereof will be omitted.

The operation of SAS generation will be explained with reference to FIGS. 1(a) and 1(b). In 2a, normal SAS generation is performed, and SAS is generated at the falling edge of the input signal FS4. However, FS4 means 4 times the frequency sampling, and DAT
(In the case of a digital audio tape recorder, a pulse of 192 kHz, which is four times 48 kHz, is used.)

2b is the SAS raw bottom when the DMA transfer process from the RAM section 31 to the SAM section 32 is delayed, and the specified number (m
During DMA transfer, which is performed every time a data transfer (byte) is completed, a DMA request signal is generated at the falling edge of the mth byte of SAS, but the processing of the host microcomputer 1 is delayed and the DM
If the return of the A permission signal is delayed, the (m+1)th byte SAS is generated at the rising edge of the DMA permission signal indicating the end of the DMA transfer process. Then, from the next (m+2)th byte, the SAS returns to the conventional cycle and is generated at a constant cycle. Also, the SA generated between 2a and 2b
S is output via the adder 2C.

The state of data transfer by the above-mentioned SAS will be explained with reference to FIG. Normally, one byte by byte is transferred at the rising edge of SAS. After m-th byte SAS input,
If the DMA request signal is sent, but the return of the DMA permission signal is delayed, the (m+1)th byte SAS occurs after the DMA transfer is completed, so the (m+1)th byte data output is the mth byte. Data D. are output correctly and consecutively. After the next data D742, the cycle is t. is retained and output. As a result of the above, only valid data can be continuously output even when DMA transfer is performed.

Although a dual baud (DRAM) DRAM has been described in the above embodiment, the RAM section and the SAM section may be independent memories configured in separate packages. In this case, SAM
The read signal or write signal of the memory corresponding to the section is DM.
The memory control circuit can also be configured to become active after the A transfer is completed.

〔Effect of the invention〕

As described above, according to the present invention, when a DMA request signal is generated during DMA transfer, the generation of a control signal for data output to the data bus is
Since this is done after the A transfer is completed, data transfer processing can be performed accurately even in a data transfer device with slow DMA processing, and correct data can be output continuously.

[Brief explanation of drawings]

FIG. 1(a) is a SAS generation diagram in the memory control circuit which is the main part of the data transfer device of the present invention, FIG. 1(b) is a time chart showing its operation, and FIG. 2 is the data transfer device of the present invention. 3 is a block diagram showing the configuration of a conventional data transfer device. FIG. 4 is a time chart diagram for explaining the operation during data transfer of the same. It is. ■...Host microcomputer, 2...Memory control circuit,
3・DP-DRAM, 31...RΔM132...S
A.M. 4.5...Data bus. ■ ■

Claims (3)

[Claims] (1) The first one that can mutually DMA transfer the memory contents.
A data transfer device is provided with a memory and a second memory, and a transfer rate of reading or writing data to an input/output port of the second memory is defined by a control signal, and the data transfer rate is defined by a control signal. The control signal is generated to keep the transfer rate at a constant value, and when a DMA transfer request signal for performing DMA transfer from the first memory to the second memory is generated, after the DMA transfer is completed. A data transfer device comprising: a memory control circuit configured to generate the control signal. (2) The first memory and the second memory are composed of dual port DRAMs housed in the same package, and the first memory is a random access memory, and the second memory is a serial memory. - The data transfer device according to claim 1, characterized in that an access memory is used. (3) The data transfer device according to claim 1, wherein the control signal is a serial access memory strobe signal.