JPS61112272A - Microcomputer applied device - Google Patents

Abstract

PURPOSE:To simplify the design of an I/O as well as the constitution of a microcomputer applied device by using a circuit which corrects the working of a direct memory addressing unit in response to each peripheral device. CONSTITUTION:A correction circuit 20 is provided to a DMAC (direct memory access controller) 2 to correct the working (bus cycle duration, control signal timing) of the DMAC 2 in response to I/O3 and 4 respectively. The circuit 20 is connected to a control bus connected to a CPU 1 and also supplies the DTACK signal given from a wait controller 7 together with signals ACK1 and K2 delivered to the I/O3 and 4 from the DMAC 2. Then the circuit 20 delays the signal DTACK for the insertion of a wait state. At the same time, the circuit 20 delays the data strobe signal DS to attain the proper action timing.

Description

Detailed Description of the Invention (Field of Industrial Application) The present invention provides a direct memory access controller ([
) rrect MemoryΔaccess Cont
The present invention relates to a microcomputer application device including a DMAC (hereinafter abbreviated as DMAC).

(Conventional Technique 1 also) In a microcomputer application device consisting of a microcomputer and 11 devices (Ilo) connected to it, some [710] have short response times and some have long response times. In order to achieve time alignment with the slow I, , , , /O, it is usually
A method of inserting (state) (adding an extra lock cycle to one instruction cycle to increase time) is adopted. Generally, the number of waits required for each of 1, -, and /O is different, so not only the control signal but also address information is used for determination.

Only the central processing unit (cpu) is I
If you want to access lo, there is no problem with this method. However, there is a DMAC on the same bus, and single address mode DMA (memory (-→
Data transfer between I and '0 takes one bus cycle (13L
The situation is different when the process is performed within the IS Cycle (without using the CPU).

In single address mode, it is the memory address that is output to the address bus, so it may not be possible to set the wait number corresponding to Ilo using this method.

FIG. 5 is a block diagram of a microcomputer application device including a conventional DMAC. In this figure, 1 is the CPU
, 2 is an I, DMACl 3.4 is I, and DMACl 10.5 is a memory, which are all coupled to each other via a data bus and an address bus. 6 is a decoder, which is coupled to an address bus and a control bus carrying control signals. 7
is a weight controller that inputs signals from the decoder 6 and control signals applied via the control bus, and controls the CPU.
DTACK signal is output to DMAC1 and DMAC2.

(Problems to be Solved by the Invention) In the conventional device having such a configuration, each of 1, . 103
, 4, a complicated external circuit 30, 40 was provided, and this required advance delivery of the Ill (it) signal to the I, /O, etc. This made the overall configuration complex! There was a problem.

The present invention has been made in view of the problems encountered in conventional devices, and its purpose is to realize a microcomputer-applied device including an OMΔC with a simple configuration.

(Means for Solving the Problems) The present invention solves the above problems by connecting a central processing unit, a direct memory access controller, peripheral devices and memory, which are coupled to each other via a data bus and an address bus. The device is characterized in that the direct memory addressing unit is provided with a correction circuit that corrects the operation of the direct memory addressing unit in accordance with each of the peripheral devices.

(Example) Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a configuration diagram of an embodiment of the present invention. The differences between this device and the conventional device shown in Fig. 5 (length of bus cycle, timing of otwg signal) are expressed as
A correction circuit 20 is provided to correct according to 3 and 4.
The point is that the control circuits 30 and 40 of each I, 103, and 4 have a bulky configuration and are small. The correction circuit 2'○ is connected to the control bus connected to CPtJl, and also inputs the DTACK signal from the weight controller 7, and also receives the signals ACK1. △CK2 is input. This correction circuit 20 is composed of several ICs including a PLA.

In a microcomputer application device including a DMAC configured in this way, there are accesses to each f, , 103, 4 and memory 5 (by the CPU 1 and access by the DMAC 2 (DMA)).

Access by CPU 1 and D! There is an essential difference between access by vl A C2. Beaten,
Taking the example of writing data into memory (WRITE> operation), when accessed by CPU1, the address, control signal, and data are all sent to the host (CPU1 or DMAC2).
In contrast, with the DMAC2, the address and iIIew signals come from the host side, and the data comes from the i'o side.
Output from @. For this reason, when accessing from DMAC2, the time relationship between the control signal and data is affected by the response speed of Ilo and cannot be unique.

In the device of the present invention, the correction circuit 20 includes the DMAC2
behavior, e.g. bus cycle length.

By correcting the timing of the control signals in accordance with 1.103.4, it is possible to define the time relationship between the fltlJ m signal and data even when accessing by DMAC2.

Hereinafter, the operation of the device of the present invention will be described with reference to FIGS. 2 to 4.
→ Data transfer of memory 5) will be explained using an example.

FIG. 2 is a waveform diagram of each signal showing the original DMA-write operation timing, and FIG.

At the time of DMA, the notification that I,.../03 has been selected is output from DMAC2 (number △CK1).
Therefore, the read (Rcad) signal of 1'03 must be created using this.

However, with the operation timing shown in FIG. 2, it is not possible to create a read signal that satisfies the standards shown in FIG. 3 from ACKI using only a simple Go1- circuit. Further, for normal operation, data must be determined at the rise of the write signal of the memory 5, but this is not satisfied with the operation timing shown in FIG.

In the apparatus shown in FIG.
By delaying as shown in FIG. 4, a wait state is inserted and the data strobe signal DS is delayed, resulting in the delay as shown in FIG. The timing of LJ production has been achieved. Here, the length of the wait state is changed every 1'O. Such operation timing satisfies the standard of 1'03 shown in Fig. 3, and i'03(1'03).
The control circuit 30 (40) of l! I has a simple configuration.

<Effects of the Invention> As explained above, according to the present invention, it is possible to simplify the configuration of the control circuit of each 5'O, simplify the design of 5'O, and improve the overall system configuration. can be done easily. Also, you can perform D to 1 eight movements suitable for each [710, (2
) Since there is no need for complicated control, problems such as interference between DMA channels can be solved.

[Brief explanation of drawings]

FIG. 1 is a combination diagram of an embodiment of the present invention, and FIGS. 2 to 4 are waveform diagrams showing its operation timing. FIG. 5 is a block diagram of a conventional device. 1...CPU 2...DMAC5,4
... ■, 10 5... Memory 6... Decoder 7... Weight controller 20... Correction circuit) t. Vessel diagram 2 (a)
To DTAC (b)
ADDRESS(A)
As (Address 5tro
be) (: ) C5-
memory (Chip 5 select) ° (
e) To AC to 1C)
O5 (Data 5trobe) (G)
RAM Wntef
! j% Figure 3 (b) D
ATA Figure 4

Claims (1)

[Claims] In an apparatus including a central processing unit, a direct memory access controller, peripheral devices and a memory, which are coupled to each other via a data bus and an address bus, the direct memory addressing unit is configured to operate the direct memory addressing unit. A microcomputer application device, comprising: a correction circuit that corrects the difference according to each of the peripheral devices.