JPS63168758A - Multi-bus control system - Google Patents

Abstract

PURPOSE:To ensure a bus during the read/modify/write cycle corresponding to each bus by controlling and separating a bus request to each bus depending on the access cycle of each bus. CONSTITUTION:When a main processor 1 is going to access a memory by means of the read/modify/write cycle (RMC), an address is outputted and a RMC signal is outputted. An access signal of a bus connecting to memory having its address area is generated by the decording signal of the address. A RMC control circuit 2 is activated by the RMC signal and the bus access signal and a bus request stored during the period of RMC is outputted to the bus only. In case of the usual of the usual read/write cycle not is the RMC, the bus request of the read/write cycle is outputted directly through an OR means 24 or 24'. In case of the RMC access, since the bus request is given only to the bus to be accessed, the use of other buses is attained and the processing efficiency is improved.

Description

[Detailed Description of the Invention] [Summary] Read/modify processor with multibus
In write cycle control, by controlling and separating the bus requests for each bus according to the access cycle of each bus, it is possible to secure a bus for each bus during the read/modify/write cycle.

[Industrial Field of Application] The present invention relates to a bus control method in a processor having a multi-bus, and particularly to bus requests based on read-modify-write cycle control.

[Conventional technology] FIG. 4 shows a conventional single-pass configuration diagram.

Traditionally, in a single pass, the processor
A modify write cycle (hereinafter abbreviated as RMC) signal was sent out as a bus request signal.

RMC is, for example, when one processor reads memory and attempts to write modified data to the same address, between a read cycle and a write cycle,
This refers to accessing memory in a single cycle, the read-modify-write cycle, to prevent writing from other access devices.

On the other hand, if a processor with multi-buses directly sends out the RMC signal as a bus request signal, the bus request signal will also be sent to unused buses, making it impossible for other access devices to use the bus.

[Problems to be solved by the invention] When a single processor executes read/modify/write cycles to multiple independent lotuses at different timings, this signal must be sent to each lotus. No.

Normally, a hash request is made using the RMC signal, and a read/write cycle is executed during the valid period of this signal.

At this time, if a bus request signal is issued by the address decode signal, the bus request will be interrupted between the read and write, and a read-modify-write cycle will not occur. In this cycle, read and write operations must be performed continuously while the bus is secured.

The present invention aims to provide a new multi-bus control method that solves the problems of the conventional method.

[Means for Solving the Problems] FIG. 1 shows a block diagram of the principle of the multi-bus control system of the present invention.

FIG. 1(a) is a diagram showing the overall configuration of the present invention, and in the figure, 1 is a main processor.

Reference numeral 2 denotes an RMC control circuit, which controls and separates path requests for each bus according to the access cycle of each bus, and controls to hold them during the RMC period.

3.3° is a bus control circuit, and 4.4° is a sub-processor and memory circuit.

FIG. 1(b) is a block diagram showing the internal configuration of the RMC control circuit.

In the figure, 21 is a differentiator, which generates a differentiated pulse at the rising edge of the RMC signal.

Reference numeral 22 denotes an AND means, which performs an AND operation between the output of the differentiating means 21 and an individual Hass (bus A) access signal.

Reference numeral 23 denotes a latch means, which is set by the output of the AND means 22.

Reference numeral 24 denotes an OR means, which takes the OR between the output of the latch means 23 and the access signal of the bus A, and outputs the result as a request signal to the bus.

22'' is also an AND means, and the output of the differentiating means 21 and
A logical product is performed with the access signal of another individual bus (bus B).

23'' is also a latch means and is set by the output of the AND means 22'.

24' is also an OR means, which takes the OR of the output of the latch means 23' and the bus access signal for bus B, and outputs the result as a bus request signal for bus B.

[Effect: When the main processor 1 attempts to access a certain memory using RMC, an address is output and an RMC signal is output. The address decode signal generates a bus access signal for a bus connected to the memory having the address area.

The RMC control circuit of the present invention operates according to this RMC signal and the bus access signal, and the RM
The lotus request held during period C is output.

In the case of a normal read/write cycle other than RMC, the read/write cycle is performed through the direct OR means 24 or 24゛.
A write cycle pass request is output.

[Example] The present invention will be described in more detail below with reference to Examples shown in FIGS. 2 and 3.

FIG. 2 is a circuit diagram of one embodiment of the present invention.

FIG. 3 is a timing chart showing the operation of one embodiment of the present invention.

Below, referring to the timing chart shown in Fig. 3, the second
The operation of the circuit shown in the figure will be explained.

(The RMC signal synchronized with the 11th clock is sent to the register (RE).
GI), the RMC signal is delayed by this register, and a differential pulse is created by the AND gate G1, as shown in FIG. 3 (3).

(2) Assume that bus A is now accessed. Bus A
The access cycle signal and the output signal of the AND gate G1 are input to the NAND gate 1-02, as shown in (2) in FIG.

The output ■ of the 431 N A N D gate G2 is input as a set signal to the register (REG2), and the J
=0. Since it is fixed to = 1, the register (REG
2) is set at the falling edge of the signal ■.

The ◇output signal ■ falls and is output to bus A as a request signal through the OR gate (G3).

(4) The clock terminal of the register (REG2) has RM
Since the C signal is input and J=O,=1,
When the RMC signal falls, it becomes "1" as shown in FIG. 3, contrary to the previous case, and the bus request is terminated through OR gate G3.

(5) For normal bus requests other than RM C, the access cycle of bus A is directly connected to inverter G4 and O
It is output as a bus A request through R game 1-G3.

The same goes for the bus, and the access cycle for bus A in FIG. 3 changes to bus B, register REG1, AND
Gate Gl, NAND gate G2', register REG
2", the bus B request is controlled through the OR gate G3".

[Effects of the Invention] As explained above, according to the present invention, when performing RMC access in a processor having multiple buses, a bus request is issued only to the bus to be accessed, so other buses can be used. The effect of improving processing efficiency is significant.

[Brief explanation of the drawing]

Fig. 1 is a principle block diagram of the present invention, Fig. 2 is a circuit diagram of an embodiment of the invention, Fig. 3 is a timing chart showing the operation of an embodiment of the invention, and Fig. 4 is a conventional single-path FIG. 2 is a block diagram showing the configuration at the time. In the drawing, l is the main processor, 2 is the RMC control circuit, and 3.
3° is a bus control circuit, 4.4 is a sub-processor, 21 is a differentiation means, 22 is an AND means, 23
is a latch means, 24 is an OR means, REG
l, RE G2. RE G2' is a register, G1 is an AND gate, G2. G2' is a NAND gate, G3. G3' is an OR gate, G4. G4' indicates an inverter, respectively. +a+ Overall configuration (bl) RMC control circuit configuration Principle block diagram of the present invention Timing chart showing the implementation of the present invention 4
figure

Claims (1)

[Claims] Read/modify processor with multibus
In the write cycle control, a differentiating means (21) for differentiating the rising edge of the read/modify/write cycle signal, and an AND means (22, 22') and the logical product means (22, 22')
latch means (23, 23') set by the output of
and logical sum means (24, 24') for logically ORing the output of the latch means (23, 23') and the individual bus access signal and outputting the result as an individual bus request signal, A multi-bus control method characterized in that a bus request that is held during a read/modify/write cycle is sent only to the bus.