JPH04319703A - Programmable controller - Google Patents

Abstract

PURPOSE:To shorten a data I/O tide and to synchronously start the execution of data I/O based upon a start command from a CPU module by executing the parallel operation of batch I/O modules when the CPU module executes data I/O in/from plural I/O units. CONSTITUTION:Each I/O unit 6 having plural I/O modules 5 is provided with a batch I/O module 1 consisting of a microprocessor(P) 1-1 for executing data I/O in/from the I/O modules 5, a dual port memory 1-5, two bus buffers 1-3, 1-4, and a bus right control circuit 1-2 and the CPU module 2 inputs/outputs data in/from the modules 5 through respective dual port memories 1-5.

Description

[Detailed description of the invention]

[Purpose of the invention]

0001

[Industrial Application Field] The present invention relates to a programmable controller that is widely used to control industrial systems such as steel and paper plants, public systems such as water and sewage plants, and the automobile industry, and in particular, to shorten the scan execution time. The present invention relates to a programmable controller provided with a module for batch input/output of I/O.

0002

[Prior art] Programmable controller (hereinafter referred to as P
C) uses a large number of I/Os. Especially large PC
The more the number of input/output points to be controlled increases,
The number of O units will also increase. These I/Os cannot fit into one I/O unit, but are distributed and implemented in multiple units. An I/O bus from the CPU module is connected to each unit, which is connected to a local I/O bus within each unit via a buffer module, etc.
/O is connected. Each I/O is given a unique I/O address, and the CPU module uses this I/O address to access each I/O. Now, when the PC scans and executes the control program, it must read data from all input modules for each scan and output the calculation results of the control program to all output modules. This is called batch input/output. The time required for this batch input/output increases as the number of I/Os increases, which has the drawback of lengthening the scan time of the PC.

FIG. 2 shows the hardware configuration of a conventional PC. In FIG. 2, 7 is an I/O bus buffer module. Conventionally, CPU 2 used bus buffer 7 during batch input/output.
The I/O 5 was read or written one by one according to its input/output type. Therefore, I/O
As the number of devices increased, the input/output time also increased.

0004

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and it is an object of the present invention to provide a module for batch input/output in an I/O unit of a PC, and to use the module for batch input/output to By sharing the bulk input/output of /O, the bulk input/output of I/O in multiple units can be executed in parallel, thereby shortening the overall bulk input/output time of the PC, and in turn shortening the scan execution time. The purpose is to [Structure of the invention]

[0005]

[Means and effects for solving the problems] The present invention provides an I/O
In a PC that uses multiple I/O units containing multiple I/O units, a microprocessor (hereinafter abbreviated as μP) for performing batch input/output of I/O in the I/O unit, and a PC
a dual port memory for receiving data from the CPU and passing read data from the I/O to the CPU;
A buffer for buffering direct input/output data and commands from the CPU, a buffer for buffering data and commands from the μP to the I/O, and a buffer in the I/O unit between the CPU and μP. A bulk input/output module consisting of a bus control circuit for arbitrating the bus right of the I/O bus is provided in each I/O unit, and a bulk input/output module is installed in each I/O unit according to a command from the CPU. By delegating the batch input/output of I/O in each I/O unit, the batch input/output in each I/O unit is executed in parallel, thereby shortening the batch input/output time. Data exchange between the CPU and I/O is performed via dual port memory and μP, but since memory access can be executed faster than I/O access, this method allows for high-speed batch input/output. becomes possible.

[0006] Also, the bulk input/output start command from the CPU is
By simultaneously receiving data from a plurality of batch input/output modules connected to the bus from the PU, the timing of batch input/output in each I/O unit is synchronized.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows an embodiment of the main structure of the present invention. In FIG. 1, 1 is a batch input/output module, 1-1 is a microprocessor, 1-2 is a bus control circuit, 1-3 is a μP bus buffer, 1-4 is a PC CPU bus buffer, 1-5 is dual port memory. 2 is PC
3 is a CPU bus, 4 is an I/O bus, 5 is an input/output module, and 6 is an I/O unit.

In this embodiment, the CPU 2 first writes data to be output into the dual port memory 1-5 of each batch input/output module 1. This writing is performed using memory addresses, so it can be executed at high speed. Further, the bus control circuit 1-2 includes an address decoder, and according to the address output by the CPU 2, the corresponding I/O
Writing is performed in a distributed manner across /O units.

Next, the CPU 2 outputs a start command to the entire batch input/output module 1. This activation output uses a common address for all batch input/output modules 1, and when the bus control circuit 1-2 decodes this command, it outputs an interrupt signal to μP 1-1. When this interrupt signal is input, μP1-1 starts batch input/output. μP1-1 accesses I/O5 via local I/O bus 4. At this time, the bus control circuit 1-2 performs bus control arbitration for the I/O bus 4, and μP1
-1 is given bus rights. The data written in the dual port memory 1-5 is output to the output module, and the data read from the input module is written to the dual port memory 1-5. When access to all modules is completed, a completion flag is set in the status register in the bus control circuit, and a read from the CPU 2 is waited for. The CPU 2 monitors the status of each batch input/output module 1, and reads input data from the dual port memory 1-5 when the completion flag is set. In this way, one batch input/output is completed. In general, I/O access takes longer than memory access, so even if batch input/output is performed via memory, multiple I/O units can perform parallel I/O.
If O input/output is performed, the entire batch input/output time can be sufficiently shortened.

[0010] When the CPU 2 wants to directly access the I/O 5, it does so using the I/O address. I
When the /O address is input, the bus control circuit 1-2 changes to μP.
Arbitrates for bus ownership of I/O bus 4 between C1-1 and C1-1.
Grant bus rights to PU2. At this time, bus buffer 1-4
is enabled, allowing the CPU to directly access I/O5.

[0011] In the above explanation, the configuration is such that the batch input/output module is an independent module, but it is also possible to adopt a configuration in which the circuit of this module is included in the motherboard of the I/O unit. It goes without saying that there is.

0012

[Effects of the Invention] As explained above, according to the programmable controller of the present invention, batch input/output of I/O of multiple I/O units can be executed in parallel, and batch input/output time can be reduced. It is possible to shorten it. Also,
Since the PC can output a startup command to all batch input/output modules at once, it is possible to synchronize batch input/output from all I/O units. Also, due to this, C
Compared to a method in which the PU inputs and outputs one I/O unit at a time, it is possible to further reduce the time difference between inputs and outputs for all I/Os.

[Brief explanation of the drawing]

FIG. 1 is an embodiment diagram showing the main part configuration of a programmable controller according to the present invention.

FIG. 2 is a block diagram showing the main part configuration of a conventional PC.

[Explanation of symbols]

1...Batch input/output module 1-1...Microprocessor 1-2...Bus control circuit 1-3...Bus buffer for microprocessor 1-4...P
C-CPU bus buffer 1-5...Dual ball memory 2...PC-CPU 3...CPU bus 4...I/O bus 5...I/O 6...I/O unit 7...Bus buffer module

Claims (2)

[Claims] Claim 1. A programmable controller comprising an input/output unit in which a plurality of input/output modules are connected via an I/O bus, and a CPU module that inputs/outputs data to/from the input/output module. a microprocessor that inputs and outputs data to and from an input/output module; a dual port memory that can be accessed by both the CPU module and the microprocessor; an address of the CPU module; a data bus and an address of the microprocessor; data bus
A collective input/output module is provided, consisting of each buffer circuit connected to the /O bus and a bus control circuit that arbitrates the bus right of the I/O bus, and the CPU module is connected to the input/output module of the input/output unit. When performing data input/output, the data is input/output in bulk to the dual port memory in the input/output unit, and the microprocessor in the input/output unit executes data input/output between the dual port memory and the input/output module. , A programmable controller characterized in that the CPU module inputs and outputs data at high speed to input/output modules of a plurality of input/output units. 2. The programmable controller according to claim 1, wherein the batch input/output module simultaneously starts data input/output based on a startup command from the CPU module, thereby synchronizing the batch input/output. .