JPH0333951A - Microcomputer system - Google Patents

Abstract

PURPOSE:To realize a very fast memory by pre-reading data corresponding to the next addresses of instruction codes or the data read out from an address counter and an output latch which read out and holds the data from a memory. CONSTITUTION:A bus request signal 15 which requests the start-up of the data read cycles of a ROM23 and a ROM42 in an LSI20 according to the execution of an instruction, and an address line 14 on which the address information of the access destinations of the ROM33 and the ROM42 are put are outputted from a processing execution part 11 to an execution control part 13. The control part 13 receives the start-up of the data read cycle, and outputs and acknowl edge signal 16 to the execution part 11. A microprocessor 10 performs data read from the ROM33 and the ROM42 via a AD bus 50 on which the address information and the data are multiplexed. The LSI20 is provided with a bus interface part 21 which receives output from the processor 10 to interface with the processor 10, and outputs control signals C1-C6.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a microcomputer system including a microprocessor and a memory.

[Conventional technology]

In recent years, microprocessors have reduced power consumption by adopting CMOS devices, and improved architecture has made it possible to process instructions at extremely high speeds. However, when reading programs and data from memory, the access speed has Due to the limitations, the access time is relatively long compared to the execution time of the microprocessor, which causes a decrease in the instruction execution time of the microprocessor.

In particular, when reading and inputting instruction codes stored in consecutive addresses like a program, most of the processing time of the entire microprocessor is spent waiting for the instruction code from memory, which speeds up the overall processing speed of the microcomputer system. is decreasing.

FIG. 8 is a block diagram of a conventional microcomputer system (hereinafter referred to as microcomputer).

This microcomputer includes a microprocessor 10a that controls data input/output processing and the entire microcomputer, multiplexed address information and instruction codes inputted from the microprocessor 10a, and a microprocessor 10a that demultiplexes input data. It is composed of an address latch 81 and a memory 80 that stores processing data and programs of the microprocessor 10a, and these units are connected to an address/data bus 50 (hereinafter referred to as 1'AD bus) and a read signal 51 (hereinafter referred to as RD double signal). ) and A, which is the latch signal of the address latch 81.
It is connected to the LE signal 55.

Next, the flow of address information on the microprocessor 10a and the AD bus 0 during continuous input of programs placed at consecutive addresses will be explained with reference to the timing chart of FIG.

Normally, programs are stored in consecutive memory areas in sequence, and the microprocessor 10a reads and executes these programs via the AD bus 0 in accordance with the order of addresses.The program input is as shown in FIG. As shown, Bl.

B2. It consists of B3 basic states.

First, the microprocessor 10a activates the ALE signal 55 during the B1 period and at the same time outputs the advertised address onto the AD bus 0 from B1 to B2. Continued<
The RD signal 51 is activated at a timing between the middle of 82 and the middle of B3, and data is read from the memory 80 onto the AD bus 0 in synchronization with this RD signal 51. Retrieve data on AD bus 0.

Through the above series of processes, one cycle of the program input data read cycle is completed.

[Problem to be solved by the invention]

As mentioned above, in the conventional microcombinator, the process execution unit 11a transfers an address to the address bus 14 at the B1 timing until it receives and receives the instruction code corresponding to the address in the middle of the B3 timing. , it is just waiting for the instruction code data to be input,
This idle time of the processing execution section 11a reduces the processing capacity of the entire microcomputer.

The time required to input a program is sufficiently long compared to the execution time of an instruction, and the microprocessor 1.1a frequently waits for input of an instruction code during a data read cycle. As a result, although the microprocessor has sufficient processing power, it has the disadvantage that the processing power has not been improved. Moreover, the memory 80 is
Power is consumed even when accessing LSIs other than the memory 80, which is always in an operating state and connected to the AD bus 0, and the microcomputer also has the disadvantage that it does not consume low power.

The purpose of the present invention is to provide a means for holding read addresses of programs and data, a means for pre-reading and holding these programs and data, and a method for accessing a memory in the transfer of programs and data stored in consecutive addresses. By newly providing a means for detecting this in advance and putting it into an operating state, and by reading data from the memory at high speed, the processing capacity of the microcomputer is improved and power consumption is reduced, and an address space priority control means is newly provided. An object of the present invention is to provide a microcomputer system that can effectively arrange and control a plurality of memories by controlling the above.

[Means to solve the problem]

The present invention provides a microcomputer system having a plurality of storage means for storing various processing data including instruction codes, and a data processing means for performing data processing by executing instructions, in which an address indicating the address of each of the storage means is provided. An address instruction means for storing information, an update means for updating the stored contents of the address instruction means, a holding means for holding an output of the storage means instructed and read by the address instruction means, and the storage means are arranged. address space specifying means for specifying an address space to be stored in the address space; When the state control means detects the storage means in advance of an instruction and puts the storage means into an operating state, and the address space designation means corresponding to each storage means specifies the same address space, each of these storage means simultaneously address space priority control means for controlling the priority order within the state control means so as not to be in an active state; and subsequent to sending a read address to the address instruction means in data transfer between the storage means and the data processing means. a first transfer means for performing one data transfer between the storage means and the data processing means, the operation state of which is instructed by the state control means and the address space priority control means; and the update means. and outputs an update control signal to the holding means to cause the holding means to hold read data from the storage means controlled to be in an operating state, and to preliminarily store an address to be read next in the address instruction means. The present invention is characterized by comprising a second transfer means that performs continuous data transfer between the holding means and the data processing means without transmitting address information.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of a microcomputer according to an embodiment of the present invention. This embodiment includes a microprocessor 1o that controls data input/output processing, arithmetic processing, and the entire microcomputer, and a read-only memory 33 (hereinafter referred to as R) that stores programs executed by the microprocessor.
ROM4 which stores the data necessary for calculations
It is composed of an LSI 20 with a built-in LSI 2.

The microprocessor 10 includes a processing execution unit 11 that executes instructions, an execution control unit 13 that controls the overall operation of the microprocessor 10, and a processing execution unit that stores instructions and data read from the ROM 23 and ROM 42 in the order in which they are read. The data queue 12 outputs stored contents in response to a request from a data queue 11.

A bus request signal 15 requesting activation of a data read cycle with the ROM 23 and ROM 42 in the LSI 20 and address information of access destinations of the ROM 33 and ROM 42 are transferred from the processing execution unit 11 to the execution control unit 13 as instructions are executed. The execution control section 13 outputs the hair crudge signal 16 to the processing execution section 11 upon activation of the data read cycle. The microprocessor 10 reads data from the ROM 33 and ROM 42 in the LSI 20 via the AD bus o in which address information and data are multiplexed.

In order to interface with the microprocessor 1o, the LSI 20 includes a bus interface section 21 that receives output from the microprocessor 1o and outputs control signals C1, C2, C3, C4, C5, C6, and programs and data of the microprocessor 1o. ROM2 that stores
3, ROM 42, and AD bus 0, and the bus inside the bus interface section 21 and LSI 20
A master-slave configuration pointer FPM 23.FPM 23.FPM 23.FPM 23.FPM 23.FPM 23.FPM 23.FPM 23.FPM 23.FPM 23.FPM 23.FPM 23.FPM23.
FPS24 (both controlled by the C2 signal output during the instruction code read cycle) and another master-slave configuration pointer DPM27. DPS28 (
(controlled by the C3 signal output during the data read cycle), an incrementer 25 that increments the contents of the FPS 24, and a continuous instruction code (to be described later) and a C1 signal output during the continuous data read cycle. , a multiplexer (hereinafter referred to as MPXI) 22 that selects the output of the incrementer 25, and the DPS2
Two incrementers that increment the contents of 8,
A multiplexer (hereinafter referred to as MPX2) 26 selects the output of the incrementer 29 in synchronization with the C1 signal, and selects the output of the FPS 24 based on the C6 signal output during the continuous instruction code read cycle, and selects the output of the FP The multiplexer (ME) X3) 32 that supplies the AD bus 0 to
A multiplexer (MPX4) 30 that selects the output of the FPM 23 and inputs it to the location control unit 31 as an ABD bus 39 (described later), an S L ROM (No. 4) that specifies the memory space of the ROM 33, and a multiplexer (MPX4) that specifies the memory space of the ROM 42. E N RO that controls the operation of the read buffer without reading the data of S LROM2ROM2OM33
M signal and an ENROM2NROM2 reliable location control unit 31 that controls the operation of the successive buffer without reading out the data in the ROM2, and an output latch 45 that stores the data read out when the instruction code is read out continuously from the ROM33.
and output buffers 37, 46.3 which read out the outputs of the output latch 35, output latch 45, and ROM 33 to the ADH bus 38, each controlled by the control line of the C4C5C6 signal.
It consists of 6.

Next, control signals input to and output from the microprocessor 10 and the LSI 20 will be described.

As an input control signal to the microprocessor 10, there is a reset signal 56 for initializing hardware within the microprocessor 10. As a control signal from the microprocessor 10 to the LSI 20, the address information on the AD bus o is sent to the FPM 23 or DPM 26.
ALE signal 55 for latching data, RD signal 51 for reading data from ROM 33,
Timing control (C1 signal control) for latching address information on D bus 0 in FPM 23 and ROM 33 and RO in continuous instruction code read cycle described later
Control signal 5TB that provides read timing from M42
F53 and address information on AD Babasu 0 to DPM27
Timing control (control of C3 signal) to latch the ROM 33 in the continuous data read cycle described later
and a control signal 5TBD54 that provides read timing from the ROM 42, and an RD signal 51 is a row active signal.

When the ALE signal 55 is 1", the 5TBD signal 54 is "O°
', a continuous instruction code read cycle is set,
At the following timing, the data in ROM33 or ROM42 is AD in synchronization with the rise of 5TBF signal 53.
When the ALE signal 55 is "1", the 5TBD signal 54 is "1", and the 5TBF signal is "o".
” Continuous data read cycle is set when
At the following timing, data in ROM33 and ROM42 is read out onto AD bus 0 in synchronization with the rise of the 5TBD signal, and the ALE signal 55 is '1'.
When ``'', 5TBD signal 54 is '1', 5TBF signal 5
When 3 is 1'', - data read cycles are set, and the ROM 33 or ROI is synchronized with the read signal.
The data of Vj42 is read onto AD bus o.

Next, FIG. 2 shows a detailed block diagram of the location control section 31 shown in FIG. 1. Mapping address designation units 61 and 64 designate address spaces in which the ROM 33 and ROM 42 are located, respectively. The memory access priority holding register (hereinafter referred to as MAPR) 70 determines which memory to access when the address space is limited or when two memories are switched to the same address space by a program. This is a register that specifies , and can be set under the control of the CPU.

The priority order of memory access according to the setting data is as shown in Table 1 below.

The comparator 60 compares the data of the ABD bus 39 and the mapping address designation section 61 and selects the FPM 23 or D
When the address information in the PM 27 matches the data in the mapping address designation section 61, that is, the address in the FPM 23 or DPM 27 is
3, the output (EQl) of the comparator 60 becomes "1"°. Similarly, the comparator 66 also has A
The BD bus 39 and the data in the mapping address designation unit 64 are compared, and when the address information in the FPM 23 or DPM 27 matches the data in the mapping address designation unit 64, the first output (EQD) of the comparator 66 is ) becomes "1". Similarly, the comparator 66 becomes "A".
Comparing the data of the BD bus 39 and the mapping address designation unit 64, when the address information in the FPM 23 or DPM 27 matches the data of the mapping address designation unit 64, the output (EQ2) of the comparator 66 becomes “1”. It becomes °′.

When the addresses where ROM33 and ROM42 are located do not overlap, EQI and EQ2 do not become "1'° at the same time, so the output of the AND circuit 71 becomes "Opa,"
Both NAND circuits 73 and 74 output P1° and M
Regardless of the priority set in APR70, EQI, E
The levels of Q2 are output via AND circuits 75 and 76, respectively.

Here, the outputs of comparators 60 and 66 are both active (
EQl=1. When EQ2=1), the AND circuit 71
The output of is “1°”, and the NAND circuit 73 outputs “1°”.
Outputs the inverted level of the data stored in PR70 and outputs the NAN
The data stored in the DAND circuit 74APR70 is output as is. At this time, if the data set in the MAPR 70 is "1", the output of the AND circuit 75 will be "1", and the output of the AND circuit 76 will be "0".

Conversely, if the data set in MAPR 70 is "°°0", the output of the AND circuit 75 will be "o 7°", and A
The output of the ND circuit 76 becomes ++I II.

When the output of the AND circuit 75 becomes "1", the output of the OR circuit 6
3, the ENROM signal becomes "1'', enabling the operation signal of the read buffer 35. Also, during the continuous instruction code read cycle, the C6 signal becomes "1'', so that
When the output of the inverter 41 becomes °°1'', the latch 6
The SLROM signal of No. 2 becomes °1'', and the ROM 33 is selected and becomes accessible.

During other read/write cycles, since the C6 signal is "0'°," when the output of the inverter 47 is "1'", the write clocks of the latch 62 and latch 65 are "1" and the AN
The output of D circuit 75 is input to latch 62. The same applies when the output of the AND circuit 76 is "1".

In general, read buffers read data from memory at high speed, so even in a 0MO3 configuration, they are configured to constantly consume power even when there is no change in data during the ENROM signal (or ENROM2NROM21'°) operating state. and also the ENROM signal (or ENROM
2NROM2O'' to 1°' and goes from a stopped state to an operating state, a configuration is adopted in which a predetermined time (Tbuf) is required until the steady operating state is reached.
Only when the M signal (or SLROM2LROC6 signal '°) is the bus interface section 21, the ROM23 or R
Outputs the data of OM42 to AD bus 0.

Next, operations during each read cycle will be described with reference to timing diagrams. The operation is the same when accessing either ROM33 or ROM42, so RO
Only the case of accessing M33 will be described.

FIG. 3 is a timing diagram illustrating the operation during the continuous instruction code read cycle of FIG. 1. Continuous instruction code read cycles consist of four clocks, Bl and B.
2. B3. The basic state for setting the address of B4 and the B5 state for continuously reading out the instruction code. B6. The execution control unit 13 outputs various control signals to the LSI 20 in these states to control the data read cycle of the ROM 33 and ROM 42 associated with instruction execution.

Incidentally, when continuing the continuous instruction code J sale, the B6 state is continued. The address used here is N N+1.
N+2. N+3. N+4. N+5 is address designation section 6
It is within the address range specified by 1. First, in the B1 state, the microprocessor 10 sets the A L, E signals 55 to ``1'' and the 5TBF signal 53 to ``0'' to perform AD.
Output address N on bus 0.

In LSI 20, the bus interface section is C
1 signal is '1°°, C2 signal is "1", C6 signal is "
1°' and outputs address N on AD bus 0 onto ADR bus 38. Then, the address N is written to the FPM 23 via the multiplexer 22, so the ABD
Address N is output on three buses. When the address N matches the address specified in the six mapping specification sections, the ENROM signal becomes ``1'' and the read buffer 34 is put into operation.

Next, in the B2 state, the microprocessor 10:
The ALE signal 55 is set to "o", and the AD bus 0 is also set to a state 9 (hereinafter referred to as high impedance) in which no data is carried. Then, the bus interface section 21 changes the C1 signal to 'O'.

Since the C2 signal is set to "O" and the C6 signal is set to °1'',
Since it is stored in FPM23, set the address N to FPS2.
AB bus 0 through multiplexer 32.
Output on top. Then, the SLROM signal becomes "1", and the data at the address in the ROM 33 corresponding to address N is read out as an instruction code and written into the output latch. The output latch has a master-slave configuration, and when the output of the inverter 41 is "0", it outputs the previously written content.

Next, in the middle of the B2 state, the microprocessor 10 sets the RD signal 51O". Then, the bus interface signal sets the C2 signal to 1", and also enables the ADR signal 50 to be output.

At this time, the C6 signal remains at '('. When the C2 signal becomes '1', the address N+1 incremented by the incrementer 25 is written to the FPM 23 via the multiplexer 22. At this time, the address N+1 is also within the address range designated by the mapping address designation section 61, so the ENROM signal remains at "1".

Next, in the middle of the B3 state, the microprocessor 10 sets the 5TBF signal 53 to "1", and the bus interface section 22 sets the C2 signal to "o". C
When the 2 signal becomes O'', the address N+1 is output onto the AB bus 0, and the address to the address N+1 is accessed. At the same time, the signal line C4 becomes 1, so the content (N) of the address of the ROM 33 corresponding to the address N, which is the output of the output latch 35, is output onto the ADR bus 38, and is passed through the bus interface section to the AD bus 0.
be placed on top.

The microprocessor 10 inputs data (N) at a predetermined timing in the first half of the next B4 state, puts the data (N) on the data bus 17 via the execution control unit 13, and writes it into the data queue 14.

The processing execution unit 101 decodes the data (N) as an instruction code and executes the corresponding arithmetic processing.

In the B4 state, the microprocessor 10
Since the TBF signal 53 is turned on, the bus interface section 21 sets the C2 signal to 1'.

Make it. When the C2 signal becomes "1", the address N+2 is input to the FPM 23. In the middle of the B4 state, the microprocessor 10 inputs the RD signal 51 "'1", 5TB
The F signal 53 is set to 1"'. Then, the bus interface unit 21 sets the AD bus 0 to a high impedance state and also sets the C2 signal to O. Then, the contents of the output latch ( N+1) is output.

Next, in the middle of the B5 state, the microprocessor 10 sets the RD signal 51o''.Then, the bus interface section 21 puts the data (N+1) on the ADH bus 38 on the AD bus router o.

In the B6 state, the microprocessor 10 uses 5TBF
Set signal 33 to °0'. Similarly to the B4 state, the data (N+1) on the AD bus 0 is written to the data queue 12. Similarly, when the STBF signal 53 changes from "O" to "1°", the ROM 33 The microprocessor 10 loads the data stored at consecutive addresses into AD bus 0, and by repeating inputting the data, the microprocessor 10 accesses the next address while reading the instruction code. Read instruction code at high speed.

Also, when the 5TBF signal 53 changes from "1" to "O'", it is determined whether the contents of the ABD bus 39 are within the address range specified by the relocation control unit, and the specified address is Within the range, E
The NROM signal and SLROM signal are each “1llZ”.
111°°, but when the comparator 60 (or 66) determines that it is outside the specified address range, the ENROM signal and the SLROM signal become 0" and "0", respectively, and the read buffer 34 stops operating, Low power consumption.

While the microprocessor 10 continues to generate the B6 state, successive instruction code read cycles continue, and finally the B6 state continues.
7 states are generated and the continuous instruction code read cycle is completed. In state B7, microprocessor 10
performs the same operation as the B4 state.

In the B1 state of the above continuous instruction code read cycle, the ENSOM signal becomes “1°” and the read buffer 3
After Tbuf time while 4 is in operation state, SLROM
Since the signal is set to "1°" and the ROM 33 is controlled to be accessed, the read buffer becomes in a normal operating state within the time Tbuf and normal data can be read.

Next, the operation when the address information stored in the FPM 23 is outside the address range specified by the mapping address specifying section 61 will be explained using the timing diagram of FIG.

In FIG. 4, addresses L, L+1. L+2 is outside the address range specified by the mapping address specifying section 61, and the address L+3. Assume that L+4 is within the address range. Then, Bl.

B2. B3. B4. Until the B5 state, the ENROM signal remains O", but in the B6 state, the AB
When the D bus 39 becomes L+3, the ENROM signal becomes °1'.
", and 7 accesses to ROM33(7) are possible. Also, since the SLROM signal becomes "1'', the data (L
+3) is output on AD bus 0. Even in this case, while the ENROM signal is “1”, the SLRO
The configuration is such that it takes Tbuf time for the M signal to reach 1''.

As described above, when the ROM 3B is outside the specified address range, the data reading operation of the ROM 33, which is the main operation of the LSI 20, is not performed, resulting in low power consumption.

Next, the operation of one data read cycle will be explained using FIG.

One data read cycle consists of B1, B2B5 states. In the B1 state, the microprocessor 10 sets the ALE signal 56 to "1", the 5TBF signal 53 to "1'', and the 5TBD signal 54 to "1".

Also, address K is placed on AD bus 0. Then, the bus interface unit sets the C1 signal to 1'', the C3 signal to 1°, and the C6 signal to ``O''.Then, since the C6 signal is 11011, the address is written to the DPM27. , C6 signal is 'O'', the address is input to the relocation control section via the multiplexer 30. If the address K is within the address range specified by the mapping address specification section 61, the SL
The ROM signal becomes It I II.

Next, in the B2 state, the microprocessor 10
In order to set the ALE signal 55 to II OII, the C3 signal becomes 0', an address is written to the DPS 28, and the ROM 33 is accessed via the multiplexer 32. At the same time, the SLROM signal also becomes 1'. Also,
The C5 signal also becomes ']pa, and the data (K) at the address of the ROM 33 corresponding to the address K is transferred from the output buffer 36 to AD.
It is output to the R bus 38. Microprocessor 10 is B
In order to set the RD signal to "o" in the middle of the 2 states,
The bus interface unit 21 AD
Read on Babasu 0. The microprocessor 10 is B
Data (K) is input at predetermined timings in three states and is used for arithmetic processing as process execution unit data.

Next, a continuous data read cycle will be explained using FIG. 6.

Continuous data read cycle consists of B1, B2, 83B4 states, and when data is read out continuously, B3 state is activated! +2 is returned. On Bl days 1 to 1 of the continuous data read cycle, the microprocessor 10 reads ALE (Z 55 to 1" to 5 TBF
The signal 53 is set to ``0'' and the 5TBD signal 54 is set to ``1.'' Also, the address M is output on the AD bus driver 0. Then, the bus interface section sets the C3 signal to ``1'' and
Write address M to DPM27. Since the C6 signal is "0" at this time, the multiplexers 32, 30 respectively output the DPS 28. Select the output of DPM27.

After that, 5T is executed as in the continuous instruction code read cycle.
In synchronization with the rise of the BF signal 53, the contents of the DPS 28 are incremented, and the data at the corresponding address of the ROM 33 is read out. Now, address M, M+1. When M+2 is within the address range specified by the mapping address specification section 61 and address M+3 is outside the address range specified by the mapping address specification section 61, the ABD bus 39 outputs the address M+3 in the middle of the B3 state. The comparator 60 outputs “0°, but the output of the latch 62 is 1
”, the ENROM signal remains at 1°.

In the next 83 states, the microprocessor 10
However, when the 5TBF signal 53 is set to "1"', the bus interface unit sets the latch 6 to set the C3 signal to "O".
'0''' is written to 2, and the ENROM signal and SL
The ROM signal becomes ``0'', and the data reading operation from the ROM 33 ends with the data at the address in the ROM 33 corresponding to address space 2.

Also, when reading the instruction code, FPM2B.

FPS24. Using the output latch 35, when reading data, the DPM 27. DPS28. Because the output latch 45 is used, even if a data read operation is interrupted and executed during an example code read operation, the instruction code read operation will only be interrupted, and the data will not be read after the data read operation is completed. Subsequently, the instruction code reading operation can be resumed.

As described above, the microcomputer according to the present invention can read instruction codes and data from the ROM 3B at high speed, and when an address space not designated by the relocation control unit 31 is accessed,
33 and the read buffer can be stopped to reduce power consumption, and the memory ROM access priority register 70
Under the control of , it is also possible to arrange two memories so that their address spaces overlap. Furthermore, ROM33 and RO
If the priority of M42 does not change during the execution of the corresponding program, a programmable EPROM that outputs a fixed level during program execution may be used in place of the memory access priority register 70.

FIG. 7 is a block diagram of a second embodiment of the invention. In the microcomputer of this embodiment, instead of the ROM 42 of the microcomputer explained in FIG.
(hereinafter referred to as RAM) is provided, and a write control section 44 is added. Further, the microprocessor supplies the LSI 20 with a write signal (hereinafter referred to as WR signal) for writing write data to be outputted onto the AD bus 0 onto the memory 42a following the address. During a data write cycle, the C7 signal becomes "1" in synchronization with the WR signal 52, the write data on the AD bus 0 is output to the ADR bus 39 via the bus interface section, and the write data on the ADH bus 39 is output to the ADR bus 39 via the bus interface section. is RA via the light control unit 44.
Written to M42a. Further, the SLRAM signal for selecting the RAM 42a is created by a circuit equivalent to the relocation control section 31 shown in FIG.

That is, the ROM mapping address specifying section 61 that specifies the memory mapping address range of the ROM 33 and the RA
Other jR precepts in which the RAM mapping address specifying section 64 that specifies the mapping address range of M42a is input to separate comparators 60 and 66 are basically the same as in FIG. and ROM33 and RAM4
If the mapping addresses of 2a overlap, MAP
R70 allows the access priority of the RAM 42a and ROM 33 to be set. The outputs of the latches 62 and 65 are the SLR selection signals for the ROM 33 and RAM 42a, respectively.
They are an AM signal and an SLROM signal. Further, the outputs of the comparators 60 and 66 and the output of the latch 62.65 are input to an OR circuit 63.69, respectively, and the ENROM, ENR
The write signals of the latches 62 and 65 are the same as in FIG.

The operation of this microcomputer is basically the same as that of the microcomputer shown in FIG. 1, and can read programs or data from memory at high speed. However, under the control of the relocation control unit 31, the two types of ROM 33 and RAM 42a can be selectively accessed.

In this case, the ROM 42 in Table 1 may be replaced with the RAM 42a. In addition, the output EN of the relocation control unit 31
When the address for accessing ROM33°RAM42a is outside the mapping address range designated by the relocation control unit 31 by ROM, ENRAM, SLROM, SLRAM signal control, ROM33, RAM4
2a can be stopped to reduce power consumption,
Also, under the control of MAPR70, ROM33 and RAM4
They can be arranged so that the address spaces of 2a overlap.

Similarly to the first embodiment, instead of the memory access priority register 70, an EPROM that outputs a fixed level during program execution may be used.

〔Effect of the invention〕

As explained above, the present invention requires a high-speed reference function to be added to the storage device itself, especially in a system that requires high-speed program reading and data reading.
Because the address counter and the output latch that holds the data read from memory read ahead the instruction code or data corresponding to the next address of the data, a very fast memory with short access time is obtained. It has the effect of being In addition, the relocation control circuit detects the mapping address of the memory before accessing it, thereby reducing the power consumption of the storage device when accessing addresses outside the memory mapping address space. By setting memory access priorities to It has the effect of being able to be used efficiently.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a microcomputer according to the first embodiment of the present invention, FIG. 2 is a detailed block diagram of the location control unit shown in FIG. 1, and FIGS. 3 and 4 are continuous instruction code read cycle diagrams. Fig. 5 is a one-time data read cycle diagram, Fig. 6 is a continuous data read cycle diagram, Fig. 7 is a block diagram of the second embodiment of the present invention, and Fig. 8 is an example of a conventional microcomputer. Block diagram, Figure 9 is 8
It is a data read cycle diagram in the figure. 10.10a...Microprocessor, 1111a.
...Processing execution unit, 12...Data queue, 1313a
...Execution control unit, 14...Address line, 15...
Bus request signal, 16... Acknowledge signal, 20
... LSI, 21 ... Bus interface section, 2
2.26, 30.32...MPX, 23...FPM
, 24...FPS, 25.29...Incrementer, 27...DPM, 28...DPS, 31...Relocation control unit, 33.34...ROM, 34°43... 3 Selling buffer, 35.45... Output latch, 36.37.46... Output buffer, 38...
ADR bus, 39...ABD bus, 40...AD bus 41.47...inverter, 42a...RAM
, 44... Light control unit, 50... AD Babasu 51
...RD signal, 53...5TBF signal, 54...5
TBD signal, 55...ALE signal, 56...Reset signal, 60°66...Comparator, 61.64...R
, OM (RAM) mapping address specification section, 62.
65...DFF, 63, 67.79...OR circuit,
68a-d...Output terminal, 69.72...Inverter, 70...MAPR171, 73-76.77.7
8...AND circuit, 80...memory, 81...address latch.

Claims (1)

[Claims] In a microcomputer system having a plurality of storage means for storing various processing data including instruction codes and a data processing means for processing data by executing instructions, an address instruction for storing address information indicating an address of each of the storage means. an updating means for updating the stored contents of the address indicating means; a holding means for holding the output of the storage means instructed and read by the address instruction means; and an address space in which the storage means is arranged. and detecting, prior to the address space specifying means instructing the storage means, that the address information stored in the address space specifying means is included in the address space specified by the address space specifying means. When the state control means that puts the storage means into an active state and the address space designation means corresponding to each of the storage means designate the same address space, the storage means are prevented from becoming active at the same time. an address space priority control means for controlling priorities in the state control means; and an address space priority control means for controlling priorities within the state control means; a first transfer means for performing one data transfer between the storage means and the data processing means, the operating state of which is controlled by the state control means and the address space priority control means, the update means and the holding means; Address information is output by outputting an update control signal to cause the holding means to hold read data from the storage means which is controlled to be in an active state, and at the same time storing the address to be read next in the address instruction means in advance. A microcomputer system characterized by comprising second transfer means for continuously transferring data between the holding means and the data processing means without transmitting the data.