JPH01239636A - Microcomputer system - Google Patents

Abstract

PURPOSE:To prevent the throughput of the whole of a microcomputer from being lowered and to reduce power consumption by controlling a memory equipped by a microcomputer in a prescribed way. CONSTITUTION:The microcomputer consists of a microprocessor 100 and an LSI200 incorporating the memory 213. And when a STBD signal is '0' at the time of setting an ALE signal 305 at '1', a continuous instruction code read cycle is set, and data in the memory 213 is read out on to an AD bus 300 synchronizing with the rise of an STBF signal 303 at a following timing. When a signal 304 is '1' and the signal 303 is '0' at the time of setting the signal 305 at '1', a continuous data read cycle is set, and the data in the memory 213 is read out on to the bus 300 synchronizing with the rise of the signal 304 at the following timing. Also, when the signals 304 and 303 are '1's at the time of setting the signal 305 at '1', one data read cycle is set, and the data in the memory 213 is read out on to the bus 300 synchronizing with a signal 301.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a microcomputer system including a microprocessor and a memory.

[Conventional technology]

In recent years, microprocessors have reduced power consumption through the adoption of CMOS devices, and improved architecture has enabled them to process instructions at extremely high speeds. The access time is relatively long compared to the execution time, which causes a decrease in the instruction execution time of the microprocessor. Especially when reading and inputting instruction codes stored in consecutive addresses like in a program, most of the processing time of the entire microprocessor is spent waiting for instruction codes from memory, which slows down the processing speed of the entire microcomputer system. ing.

FIG. 9 shows a microprocessor 1000. 1 shows a conventional example of a microcomputer system (hereinafter referred to as a "microcomputer") comprising a memory 1201 for storing programs and data.

The microcomputer shown in FIG. 9 includes a microprocessor 1000 that performs data input/output processing and controls the entire microcomputer;
an address latch 1205 for demultiplexing multiplexed address information, instruction code, and input data input from the microprocessor 1;
Memory 1 for storing 000 processing data and programs
201, and these units transmit an address/data bus 1301 (hereinafter referred to as "AD bus"), a read signal 1304 (hereinafter referred to as "RD double signal), and an ALE signal 13 which is a latch signal of address latch 1205.
It is connected with 03.

Next, we will discuss address information and data flow on the microprocessor 1000 and the AD bus 301 during continuous input of programs placed at consecutive addresses.
This will be explained with reference to the timing chart shown in FIG.

Normally, programs are stored in consecutive memory areas in sequence, and the microprocessor 10oo reads and executes these programs in accordance with the address order via the AD bus 301, and the program input is as shown in FIG. It is composed of basic states B2 and B3.

First, the microprocessor 1000 performs ALE during the B1 period.
32 from B1 at the same time as signal 1303 is activated.
The read address is output onto the AD bus 301. The RD signal 1304 is set to active level at the timing between B2 and B3, and the RD signal 1304
Data is read from the memory 1201 onto the AD bus 301 in synchronization with the microprocessor 1000, and the microprocessor 1000 takes in the data on the AD bus 301 at a predetermined timing within the B3 timing. Through the above series of processes, one cycle of the program input data read cycle is completed.

[Problem to be solved by the invention]

As described above, conventional microcomputers do not allow data to be input during the period from when the processing execution unit 1101 puts an address on the address line 1104 at timing B1 until it receives data corresponding to that address in the middle of timing B3. It is just waiting, and this processing execution unit 110
1's idle time reduces the overall processing power of the microcomputer.

The time required to input a program is sufficiently long compared to the execution time of an instruction, and the microprocessor 1000 is frequently in a data wait state during a data read cycle. As a result, the processing speed of the microprocessor is not improved because the processing capacity of the microprocessor is not sufficient.

In addition, the memory 1201 is always in an operating state, and
Power is also consumed when accessing LSIs other than the memory 1207 connected to the D bus 301, and the microcomputer also has the disadvantage that it does not consume low power.

[Means to solve the problem]

The present invention provides an address instruction for storing address information indicating an address of the storage means in a microcomputer system having a storage means for storing various processing data including instruction codes and a data processing means for performing data processing by executing instructions. means, updating means for updating the storage of the address instruction means, holding means for holding the output of the storage means instructed and read by the address instruction means, and specifying an address space in which the storage means is arranged. a state in which it is detected prior to the instruction of the storage means by the address instruction means that the address information stored in the specification means is included in the address space specified by the specification means, and the storage means is put into an operating state; The storage means and the data are controlled to be in an operating state by the state control means, and are instructed to send a read address to the address instruction means in data transfer between the control means, the storage means, and the data processing means. a first transfer means that performs one data transfer with the processing means; and a first transfer means that outputs an update signal to the update means and the holding means, and reads from the storage means controlled to be in an operating state within the holding means. A second method for continuously transferring data between the holding means and the data processing means without transmitting address information by holding data and preliminarily storing an address to be read next in the address indicating means. It has a transfer means.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

The microcomputer shown in FIG.
A microprocessor 100 that controls output processing, calculation processing, and the entire microcomputer, and a read-only memory (hereinafter referred to as "memory") 21 that stores programs executed by the microprocessor and data necessary for calculations.
It is composed of an LSI 200 with a built-in 3. The microprocessor 100 includes a processing execution unit 101 that executes instructions.
an execution control unit 103 that controls the overall operation of the microprocessor 100; and a data processor that stores instructions and data read from the memory 213 in the order in which they are read and outputs the stored contents in response to requests from the processing execution unit 101. 102.

A bus request signal 1 is sent from the processing execution unit 101 to the execution control unit 103 to request activation of a data read cycle with the memory 213 in the LSI 200, which will be described later, upon execution of an instruction.
05 and an address line 104 carrying address information of the access destination of the memory 213 are output, and the execution control unit 103 outputs a 7 knowledge signal 106 to the processing execution unit 101 in response to activation of the data read cycle. The microprocessor 100 reads data from the memory 213 in the LSI 200 via the AD bus 00 in which address information and data are multiplexed.

The LSI 200 has a bus interface section 201 that receives output from the microprocessor 100 and outputs control signals C1, C2, C3, C4, C5, C6 in order to interface with the microprocessor 100, and stores programs and data for the microprocessor 100. memory 2
13, is input from the AD bus 00, and is input to the bus interface section 201 and the bus inside the LSI 200 (hereinafter referred to as "
A master-slave configuration pointer FPM 20 that latches address information via the AD bus (denoted as “AD bus”) 218.
3. FPS 204 (both controlled by the C2 signal output during the instruction food read cycle) and another master-slave configuration pointer DPM 207. DPS2
08 (C3 output during data read cycle
an incrementer 205 that increments the contents of the FPS 204, and a multiplexer (MPXI) that selects the output of the incrementer 205 in synchronization with the C1 signal output during continuous instruction code and continuous data read cycles, which will be described later. 202 and DPS 2
Incrementer 209 increments the contents of 08
, a multiplexer (MPX2) 206 that selects the output of the incrementer 209 in synchronization with the C1 signal, and a multiplexer (MPX2) 206 that selects the output of the FPS 204 based on the C6 signal output during continuous instruction code read cycles and stores it in the memory 213 as the AB bus 20. Supply multiplexer (MPX3) 2
12, and similarly at 06, the output of the FPM 203 is selected and the ABD is sent to the relocation control section 211, which will be described later.
Multiplexer (MPX4) input as bus 219
210 and an SLR that specifies the memory space of the memory 213.
It outputs the OM signal and the ENSAMP signal that controls the operation of the read buffer that reads data from the memory 213, and the location control unit 211 and the instruction code to the memory 213.
an output latch 215 that stores the read instruction code when reading data continuously from the memory 213; and an output latch 22 that stores the read data when reading the data continuously from the memory 213.
5, and an output latch 4215. Output latch 225. an output buffer 217 that reads the output of the memory 213 to the ADR bus 218 under the control of control lines C4, C6, and C5, respectively;
226, 216.

Next, control signals input to and output from the microprocessor 100 and the LSI 200 will be described.

An input control signal to the microprocessor 100 is a reset signal 306 for initializing hardware within the microprocessor 100. As a control signal from the microprocessor 100 to the LSI 200,
an ALE signal 305 for causing the FPM 203 or DPM 206 to latch address information on the AD bus 00;
RD for reading data from memory 213
A signal 301, a control signal 5TBF303 that provides timing control (control of C2 signal) for causing the FPM 203 to latch address information on the AD bus 00, and read timing from the memory 213 in a continuous instruction code read cycle to be described later, and the AD bus 00. Timing control (C
3 signal control) and a control signal 5TBD 304 that provides read timing from the memory 213 in continuous data read cycles, which will be described later. RD signal 301 is a row active signal.

When the ALE signal 305 is “1”, the 5TBD signal 304 is “1”
If it is 0'', a continuous instruction code read cycle is set, and at the subsequent timing, the data in the memory 213 is changed to AD bus 00 in synchronization with the rise of the 5TBF signal 303.
read out above. When the ALE signal 305 is “1”, 5
TBD signal 304 is “1”, 5TBF signal 303 is “0”
'', a continuous data read cycle is set, and at the subsequent timing, data in the memory 213 is read onto the AD bus 00 in synchronization with the rising edge of the 5TBD signal 304.Furthermore, when the ALE signal 305 is "1", the data in the memory 213 is read out onto the AD bus 00.
When the D signal 304 is "1" and the 5TBF signal 303 is "1", one data read cycle is set, and the data in the memory 213 is transferred to the AD bus 0 in synchronization with the RD signal 301.
read on 0.

Next, FIG. 3 shows a detailed diagram of the relocation control section and will be described. The mapping address specification section 401 is stored in the memory 213.
Specify the address space in which to place. Comparator 400 is A
When the address information in the FPM 203 or DPM 206 matches the data in the mapping address specification section 401 by comparing the BD bus 219 and the mapping address specification section 401, that is, when the address information in the FPM 203 or DPM 206 matches the data in the specified memory 213. When included in the address space, the output of the comparator 400 becomes active, and the ENSAMP signal becomes 1" through the third circuit 403, enabling the read buffer 214 to operate. Also, during continuous instruction code read cycles, the C6 signal becomes '1', so when the output of the inverter 221 becomes '1', the output SLROM signal of the latch 402 becomes '1' and the memory 21
3 is selected and becomes accessible. During other read cycles, the C6 signal is "0", so when the output of the inverter 227 is "1", the write clock of the latch 402 is "1".
The output of comparator 400 is then input to latch 402. In general, the read buffer 214 uses ENSA even if it has a 0MO8 configuration in order to read data from the memory 213 at high speed.
The configuration is such that power is constantly consumed even when there is no change in data when the MP signal is in the operating state of "1", and the EN
When the SAMP signal changes from "0'" to "1" and changes from a stopped state to an operating state, a configuration is adopted in which a predetermined time (taU,) is required until the steady operating state is reached. Also, SLR
The bus interface unit 20 only when the OM signal is “1”
1 outputs the data in the memory 213 to the AD bus 00.

Next, the operation during continuous instruction code read cycles will be explained using FIG.

A continuous instruction code read cycle consists of four B1. B2. B3. Basic state for setting the address of B4, and B5.B5 for continuously reading instruction codes.
B6. It consists of states B7, and the execution control unit 1
03 outputs various control signals to the LSI 2 QO in these states to control the memory 2 during instruction execution.
It controls 13 data read cycles. In addition,
When continuing to read continuous instruction codes, the B6 state continues. The addresses used here are N, N+1. N+2, N+
3. N+4. All N+5 are within the address range designated by the address designation section 401.

First, the microprogram 100 sets the ALE signal 305 to "1" and the 5TBF signal 303 to 0 in the Bl state.
, 5TBD signal 304 to "0", and outputs address N on AD bus 00.

In the LSI200, the bus interface section sets the C1 signal to "l", the C2 signal to "1", and the C6 signal to "1", and
Address N on D bus 00 is output onto ADR bus 218. Then, F'PM203 has multiplexer 2.
Since address N is written via ABD bus 2
Address N is output on 19. When the address N matches the address specified by the mapping address specifying section 401, the ENSAMP signal becomes "1" and the read buffer 214 is put into an operating state.

Next, in the B2 state, the microprocessor 100 is AL
The E signal 305 is set to "0", and the AD bus 00 is set to a state in which no data is loaded (hereinafter referred to as a "high impedance state"). Then, bus interface section 2
01 is the CI double signal “0”.

Since the C2 signal is set to “0” and the CO multiplied signal is set to “1”, the FP
The address N stored in M203 is set to F'PS204.
AB bus 2 via multiplexer 212.
Output on 0. Then, the SLROM signal becomes "L" and the data at memory address 2130 corresponding to address N is read out as an instruction code and written to the output latch. The output latch has a master-slave configuration, and outputs the previously written contents when the output of the inverter 221 is "0". Next, in the middle of the Bl state, the microprocessor 100 sets the RD signal 301 to "0". Then, the bus interface signal changes the C2 signal to “1'',
Further, the contents of the ADR bus 218 can be output onto the AD bus 00. At this time, the C6 signal remains "1". When the C2 signal becomes 1'', the address N+1 incremented by the incrementer 205 is sent to the multiplexer 2.
02 to the FPM 203. At this time, the address N+1 is also within the address range specified by the mapping address specifying section 401, so the E M S AMP signal remains at "1n."Next, in the middle of the B3 state, the microprocessor 100 outputs the 5TBF signal, 303 “
When the C2 signal is set to ``1'', the bus interface unit 201 sets the C2 signal to ``0''. When the C2 signal becomes II OII,
Address N+1 is output onto AB bus 20, and the address of memory 213 corresponding to address N+1 is accessed. At the same time, the signal line C4 becomes "1", so the memory 21 corresponding to the address N which is the output of the output latch 215
The content data (N) at address 3 is output onto the ADR bus 218 and placed on the AD bus 00 via the bus interface section.

The microprocessor 100 inputs data (N) at a predetermined timing in the first half of the next B4 state, puts the data (N) on the data bus 107 via the execution control section, and writes it to the data key 102. The processing execution unit 101 executes data (N
) is interpreted as an instruction code and the corresponding arithmetic processing is executed. In state B4, microprocessor 10
0 sets the 5TBF signal 303 to "0", so the bus interface section 201 sets the C2 signal to "1". When the C2 signal becomes 1, address N+2 is input to the FPM 203. In the middle of the B4 state, the microprocessor sets the RD signal 301 to "1" and the 5TBF signal 303 to "1". Then, the bus interface unit 201
0 to high impedance state, and C2 signal to 0.
”.Then, the contents of the output latch (N+1) are output to the ADH bus 218.Next, in the middle of the B5 state, the microprocessor 100 outputs the RD signal 301 to
Make it ++. Then, the bus interface section 201
The data (N+1) on the ADR bus is placed on the D bus 00.

In the B6 state, the microprocessor 100 is 5TBF
The signal 303 is set to 0''. Also, similarly to the B4 state, the data (N+1) on the AD bus 00 is set to the data key 1.
Write to 02. Similarly, the 5TBF signal 303 is “0”
When the data changes from "l" to "l", the data stored in consecutive addresses in the memory 213 is placed on the AD bus 00, and the microprocessor 100 manipulates the input of that data to read out the instruction code. The next address is accessed and the instruction code is read out at high speed.

Also, when the 5TBF signal 303 changes from "1" to "0", it is determined whether the address is within the address range specified by the location control unit based on the contents of the ABD bus 219, and the address is within the specified address range. If there is, ENS
AMP signal and SLROM signal are each IIIZ1
``1'', but if the address is outside the specified address range, comparator 4
00, the ENSAMP signal and the SLROM signal each become "0"ZIIO"', and the read buffer 214 stops operating, resulting in low power consumption. While the microprocessor 100 continues to generate the B6 state, the instruction code is continuously read. The cycle continues and finally the B7 state is generated to end the continuous instruction code read cycle.

In the BT state, the microprocessor 100 performs the same operations as in the B4 state.

In the B1 state of the above continuous instruction code read cycle, the E N S AMP signal becomes "1" and the read buffer 214 is put into the operating state, and after tBt11 hours, the SL
Since the ROM signal is set to ``1'' and the memory 213 is accessed, the read buffer becomes in a normal operating state within the time tFNJf, and normal data can be read.

Next, the operation when the address information stored in the FPM2 Q3 is outside the address range specified by the mapping address specifying section 401 will be explained using FIG.

In FIG. 6, addresses L, L+1. L+2 is an address L+3 . Assume that L+4 is within the address range. Then, Bl, B2°B3. B4. The ENSAMP signal remains ``0'' until the B5 state, but the
In the 6B6 state, when the ABD bus 219 becomes L+3, the ENSAMP signal becomes 1"', and the SLEPROM signal also becomes "1" from the middle of the B6 state, making it possible to access the memory 213. Also, since the SLROM signal becomes 1, the data ( L+3) is output on the AD bus 00. In this case as well, the ENSAMP signal is ``1''
The configuration is such that tBU1 time can be taken from when the SLROM signal becomes 11111.

As described above, outside the address range where the memory 213 is specified, the main operation of the LSI 200, which is the reading operation of data from the memory 213, is not performed, resulting in low power consumption.

Next, the operation of one data read cycle will be explained using FIG.

One data read cycle consists of B1, B2 . It is composed of B3 states. In the B1 state, the microprocessor 100 sets the ALE signal 306 to
Set the TBF signal 303 to "1" and set the 5TBD signal 304 to "1".
''.Additionally, address K is placed on AD bus 00.Then, the bus interface section sets the C1 signal to “1”.
Then, the C3 signal is set to "1" and the C6 signal is set to "0". Then, since the C6 signal is '0'' at the address, the DPM
Since the C6 signal is "0", the address is input to the relocation control unit via the multiplexer 210. If the address K is within the address range specified by the mapping address specification section 401,
E N S A M P signal becomes “l”. Next, B2
state, multiplexer 100 outputs ALE signal 305
In order to set the value to 0'', the C3 signal becomes 0' and the DPS 208
Address K is written to , and memory 213 is accessed via multiplexer 212 . At the same time, SLROM
The signal also becomes 1''.The C5 signal also becomes II I II, and the data (K) at the address of the memory 213 corresponding to the address K is output from the output buffer 216 to the ADR bus 218.The microprocessor 100 is in the B2 state. In order to make the RD double signal II Or+ in the middle, the bus interface unit 201 reads data (K) onto the AD bus 00.The microprocessor 100 inputs the data (K) at a predetermined timing in the B3 state and executes the process. The unit uses it as data for calculation processing.

Next, the continuous data read cycle will be explained using FIG. Continuous data read cycles B1, B2. B3
．． It is composed of the B4 state, and the B3 state is repeatedly output during an operation in which data is read continuously. In the B1 state of the continuous data read cycle, the microprocessor sets the ALE signal 305 to "1", the 5TBF signal 303 to "'0", and the 5TBD signal to "'1". Output M.

Then, the bus interface section sets the C3 signal to "1n" and writes the address M to the DPM 207. At this time, the C6
Since the signal is “0”, multiplexer 212.210
are DPS 208. Select the output of DPM207. After that, 5 steps are performed as in the continuous command hood read cycle.
DPS 20 in synchronization with the rising edge of TBF303 signal
The contents of g are incremented, and the data at the corresponding memory 213 address is read.

Address M, M+1. M+2 is address M+3 within the address range specified by mapping address specification section 401
is outside the address range specified by the mapping address specifying unit 401, the comparator 400 outputs O in the middle of the B3 state that outputs the ABDB1 state address M+3.
However, since the output of latch 402 is “1”, EN is output.
The SAMP signal remains at "1". In the next B3 state, when the microprocessor 100 sets the 5TBF signal 303 to 111+, the bus interface section changes to C3.
In order to make the signal “0”, the latch 402 has II OI.
I is written and both the ENSAMP signal and SLROM signal are “
O'', and the data reading operation from the memory 213 ends with the data at the memory address 2130 corresponding to the address M+2.

Also, FPM203 when reading instruction code.

FPS204. The output latch 215 is used, and the DPM 207. DPS208. Output latch 22
5 is used, even if a data read operation is interrupted and executed during an instruction code read operation, the instruction code read operation is simply interrupted and the data read operation is continued after the data read operation is completed. Instruction code read operation can be resumed.

As described above, the microcomputer can read instruction codes and data from the memory 213 at high speed, and when an address space not specified by the relocation control unit 211 is accessed, the memory 213 and read buffer 214 are stopped and the Can reduce power consumption.

Next, a second embodiment of the present invention will be described using FIGS. 2 and 4.

The microcomputer shown in FIG. 2 has a memory 222 having a RAM structure capable of reading and writing data in addition to the memory 213 of the microcomputer that failed in FIG. 1. Also, the microprocessor
A write signal (hereinafter referred to as W
302 (denoted as "R signal") is supplied to the LSI 200. During the data write cycle, the C signal
7 signal becomes "1", the write data on the AD bus 00 is output to the ADR bus via the bus interface section, and the write data on the ADR bus is output to the write control section 22.
4 to the memory 222. Also, memory 2
The SLRAM signal for selecting 22 is created by the relocation control unit 211 shown in FIG.

In FIG. 4, a ROM mapping address designation section 401 that specifies the mapping address range of the memory 213 and an RA that specifies the mapping address range of the memory 222 are shown.
M mapping addressing section 404 is input to separate comparators 400 and 406, respectively, and the outputs of comparators 400 and 406 are input to latches 402 and 406, respectively.
has been entered. The outputs of latches 402 and 406 are SLROM selection signals for memories 213 and 222, respectively.
and the SLRAM signal. Further, the outputs of comparators 400 and 406 and the outputs of latches 402 and 406 are input to third circuits 403 and 410, respectively, and ENROM and E
Configure NRAM. Since the write signals of latches 402 and 406 are the same as those shown in FIG. 3, their explanation will be omitted.

The operation of the microcomputer shown in FIG. 2 is basically the same as that of the microcomputer shown in FIG. 1, and programs or data can be read from memory at high speed. However, under the control of the relocation control unit 211, 2
Seed memory 213 and memory 222 can be selectively accessed. In addition, the relocation control unit 211
Output of ENROM, ENRAM, SLROM, SLRA
The memory 213. is controlled by the M signal. When the address accessing the memory 222 is outside the mapping address range specified by the location control unit 211, the memo! , I
213. The memory 222 can be turned off to reduce power consumption.

〔Effect of the invention〕

As explained above, the present invention requires a high-speed reference function to be added to the storage device itself, especially in a system that requires high-speed program read and data read.
Because the address counter and the output latch that holds the data read from the memory read ahead the data corresponding to the next address of the instruction code or data being read, it is possible to provide extremely high-speed memory with short access time. effective. Furthermore, by detecting the mapped address of the memory prior to access by the relocation control circuit, it is possible to reduce the power consumption of the storage device when accessing an address other than the mapped address space of the memory.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a first microcomputer implementing the present invention, FIG. 2 is a block diagram of a second microcomputer implementing the present invention, and FIG. 3 is a detailed diagram of the location control section of FIG. , Figure 4 is a detailed diagram of the location control unit shown in Figure 2, Figures 5 and 6 are continuous instruction code read cycle diagrams, Figure 7 is a single data read cycle diagram, and Figure 8 is a diagram of continuous data. 9 is a block diagram of a conventional example, and FIG. 10 is a data read cycle diagram in FIG. 9. 201...Bus interface. Agent Patent Attorney Uchihara Otobaku 3rd 4th - Parents T31 52 83

Claims (1)

[Claims] In a microcomputer system having storage means for storing various processing data including instruction codes, and data processing means for performing data processing by executing instructions, address information indicating an address of the storage means is stored. an address specifying means, an updating means for updating the stored contents of the address specifying means, a holding means for holding the output of the storage means instructed and read by the address specifying means, and an address space in which the storage means is arranged. detecting, prior to the instruction of the storage means by the address specifying means, that the specifying means to specify and the address information stored in the address specifying means are included in the address space specified by the specifying means; a state control means for setting the storage means in an operating state; and a state control means for controlling the storage means to be in the operating state following transmission of a read address to the address instruction means in data transfer between the storage means and the data processing means; An update control signal is output to a first transfer means for performing one data transfer between the storage means and the data processing, the update means and the holding means, and the holding means is brought into an operating state. By holding the controlled read data from the storage means and storing the address to be read next in the address instruction means in advance, the data can be exchanged between the holding means and the data processing means without sending address information. A microcomputer system comprising a second transfer means for continuous data transfer.