JP2672532B2 - Coprocessor system - Google Patents

Description

The present invention relates to data transfer control in a coprocessor system, and further to a data transfer control technique for transferring data from a coprocessor to a memory. For example, a main processor uses a cache memory. The present invention relates to a technique effective when applied to data transfer control for achieving consistency of stored data shared by a main memory and a cache memory at the same address. [Prior Art] A coprocessor is a processor that is coupled to a main processor such as a general-purpose data processor, expands a register set and an instruction set, and adds a new processing capability and a high-speed arithmetic function to a system. As an interface method between the main processor and the coprocessor, the main processor detects the coprocessor instruction, transfers commands to the coprocessor,
There is a method in which the main processor executes all bus cycles such as data transfer between the main memory and the coprocessor. In such a coprocessor system, when the coprocessor transfers data to and from the main processor or main memory, the main processor performs bus cycle generation and control, while the coprocessor exchanges actual data. Due to the nature of having to be used, even when conventionally transferring the data calculated by the coprocessor to the main memory, the main processor temporarily takes in this data to be transferred, and the taken-in data is transferred to the main memory according to the subsequent memory cycle. The procedure of giving to memory was taken. In addition, as a document describing the coprocessor,
November 30, 1984 "LSI Handbook" issued by Ohmsha, Inc. 558
Pp. 559 and 559, Dec. 25, 1986, "Microcomputer Handbook," 680 and 681, published by Ohmsha. [Problems to be Solved by the Invention] However, there is a two-step process in which the main processor temporarily takes in the data which is to be calculated in the coprocessor and should be transferred to the main memory, and gives the taken data to the main memory according to the subsequent memory cycle. If the data transfer procedure of 1 is adopted, the data transfer processing is delayed, the occupancy period of the shared bus is lengthened, and the operating efficiency of the system is reduced. Further, when the main processor includes a cache memory such as an operand cache memory, if the operation result data is given from the coprocessor to the main memory by the above-described procedure, the operand cache memory is temporarily fetched by the data fetched by the main processor. Since the data is transferred to the main memory after the content of is rewritten, if the main processor accepts the interrupt processing during that time, the operand cache memory and the main memory that share and hold the data of the desired address in the main memory However, there is a problem that it becomes impossible to maintain consistency between the held data regarding the same address. In this regard, in order to maintain the mutual consistency by rewriting the operand cache memory and the main memory at the same timing with the data once taken in by the main processor, a memory different from the operand cache memory is used. It is necessary to specially provide such a data buffer in the input / output control unit of the main processor and store data in the data buffer in advance, which complicates the configuration of the input / output control unit of the main processor and its control procedure. An object of the present invention is to provide a coprocessor system capable of efficiently storing data output from a coprocessor in a memory under the control of a main processor. Still another object of the present invention is to maintain the consistency of the data held by the cache memory included in the main processor and the memory with respect to the same address when storing the data output from the coprocessor in the memory. The object is to provide a coprocessor system that can do so. The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings. [Means for Solving the Problems] The outline of the representative one of the inventions disclosed in the present application will be briefly described as follows. That is, an address bus and a data bus, a main processor commonly connected to the address bus and the data bus, a coprocessor for performing an operation in accordance with an instruction from the main processor, and a memory access-controlled by the main processor are provided. And the main processor includes a cache memory that holds the data held in the memory in association with the address of the data and a cache controller that controls the cache memory, and the main processor is the operation result by the coprocessor. When data is stored in the memory, a signal for instructing a data output operation is given to the coprocessor, an instruction for a write operation is given to the memory, and an address signal for accessing the memory is output to an address bus. Yes, the above coprocessor is In response to a data output operation instruction signal, the memory outputs data to the data bus, and the memory receives the write operation instruction and transfers the data on the data bus to an address specified by the address signal on the address bus. The cache controller writes the data on the data bus in correspondence with the address signal output to the address bus by the main processor when the main processor stores the operation result data by the coprocessor in the memory. A coprocessor system characterized in that it is held in the cache memory. [Operation] According to the above means, when the operation result of the coprocessor is stored in the memory, the data output from the coprocessor is directly fetched into the memory via the data bus and is also incorporated in the main processor. The data output from the coprocessor can be efficiently stored in the memory by being captured in the existing cache memory, and when the data output from the coprocessor is stored in the memory, the cache memory and the memory have the same address. It achieves to maintain the integrity of the data held in common. [Practical Example] FIG. 1 is a block diagram showing an embodiment of a coprocessor system according to the present invention. The coprocessor system shown in FIG. 1 is not particularly limited, but the functions of a main processor 1 such as a microprocessor as a general-purpose processor, a floating-point arithmetic operation, and a multi-precision arithmetic operation of a transcendental function, which are typically shown, are shown. Coprocessor 2 with dynamic RAM (random
Access memory). Although not particularly limited, the above three functional blocks are formed on individual semiconductor substrates by known semiconductor integrated circuit manufacturing techniques. The main processor 1, the coprocessor 2, and the main memory 3 are coupled to each other so that data DAT can be input / output through a 32-bit data bus 4, and the address signal ADRS output from the main processor 1 is an address. It can be supplied to the coprocessor 2 and the main memory 3 via the bus 5. The main processor 1 is not particularly limited, but as shown in FIG. 2, an instruction prefetch section, an instruction decoding section for decoding the operation code of the prefetched instruction, and an address decoded by the instruction decoding section. As an instruction control unit 6 including a micro program control unit for sequentially reading a series of micro instructions and forming various control signals required for instruction execution, and various arithmetic processing according to the control signals output from the instruction control unit 6. And an input / output unit 8 for interfacing with the coprocessor 2 and the main memory 3 described above. The input / output unit 8 is not particularly limited, but may be the second
Memory management unit 10, operand cache memory 11, cache controller 12,
And an interface controller 13 are included. The memory management unit 10 includes an address conversion table for converting a logical address into a physical address,
The logical address supplied from the execution unit 7 is converted into the corresponding physical address and the address signal ADRS is output. The operand cache memory 11 holds the data of the desired address in the operand storage area of the main memory 3 in common with the main memory 3 in association with the address. The operand cache memory 11 is composed of an associative memory unit 20 such as a content addressable memory and a data memory unit 21, although not particularly limited. The data memory unit 21 is not particularly limited, but is a static R that holds the data DAT in a rewritable manner.
Composed by AM. The associative memory unit 20 gives an address signal for addressing the data memory unit 21. When the address signal ADRS is externally applied to the operand cache memory 11, the address signal that matches the supplied address signal ADRS is the associative memory unit as the searched data.
In the case of being stored in 20, the address signal corresponding to the address signal ADRS is given to the data memory unit 21, and the data memory unit 21 reads / writes the data DAT by this address signal. Further, when the address signal matching the supply address signal ADRS is not stored in the associative memory unit 20 as the searched data, the address signal ADRS is stored in a predetermined storage area and the address signal paired with the address signal ADRS is stored. The memory cell corresponding to this address signal is given to the data memory unit 21 and the predetermined data DAT
Rewritten by Although not particularly limited, the cache controller 12 controls access to the operand cache memory 11 based on the control of the interface controller 13. The interface controller 13 exchanges predetermined interface signals and status information with the coprocessor 2 and the main memory 3 under the control of the instruction control unit 6, and outputs necessary information obtained thereby by the instruction control unit 6. Give to. In response to this, the instruction control unit 6 branches the microflow into a predetermined control procedure. Further, the interface controller 13 controls the cache controller 12, but when the operand cache memory 11 exchanges data with the coprocessor 2 and the main memory 3, the interface controller 13 outputs the bus control interface signal output from the interface controller 13. The cache controller 12 is controlled on the basis of an interface signal supplied from the outside in synchronism with the control of 1), thereby making the access control of the operand cache memory 11 possible. The internal configuration of the coprocessor 2 is not particularly shown, but a command fetch section, a command decode section for decoding the fetched command, and a series of micro-instructions with the contents decoded by this command code section as an address are sequentially read out. A control unit including a microprogram control unit that forms various control signals necessary for command execution based on the above, and an execution unit that actually executes the commands by performing various arithmetic processes according to the control signals output from the control unit, It is configured to include an input / output unit that interfaces with the main processor 1 and the main memory 3. Although not particularly limited, when the main processor 1 fetches a macro instruction of the system and the fetched instruction is the main instruction, the operation and the data transfer are executed according to the fetched instruction. When the instruction fetched by the main processor 1 includes a coprocessor instruction or a coprocessor instruction, the main processor 1 cuts out a field necessary for the coprocessor 2 from the instruction, generates a command, and gives the command to the coprocessor 2. When the command given to the coprocessor 2 includes data input / output by the coprocessor, the main processor 1 performs necessary bus cycle control. The main processor 1 uses the bus start signal ▲ ▼, the read / write signal R /, the address strobe signal ▲ ▼, and the bus access type data BA as interface signals for controlling the bus cycle by handshake.
The T and byte control data ▲ ▼ are output to the coprocessor 2 and the main memory 3, respectively, and the coprocessor data enable signal ▲ ▼ is output to the coprocessor 2. These interface signals are output from the interface controller 13. The read / write signal R / is a signal for instructing a data transfer direction, that is, a read / write operation, and the coprocessor data enable signal ▲ ▼ is a signal for instructing the coprocessor 2 to output data by its low level. The address strobe signal ▲ ▼ is a signal indicating by a low level that the address signal ADRS output from the main processor 1 is fixed on the address bus 5, and the bus start signal ▲ ▼ is a signal by the low level. This is a signal instructing the start of a cycle. The bus access type data BAT is the main processor 1
Is 3-bit data indicating the type of bus access requested by, and a combination of the 3-bits indicates, for example, a coprocessor command transfer request or an operand transfer request.
That is, it indicates whether the transfer target is a command or an operand. Byte control data ▲
▼ is 4-bit data indicating the data size to be exchanged by the low level in byte units. In various forms of data transfer among the main processor 1, the coprocessor 2, and the main memory 3, the main processor 1 starts and controls the bus cycle as described above, and the coprocessor 2 is the data transfer source. However, the coprocessor 2 outputs the data complete signal ▲ ▼ to the main processor 1 and the main memory 3, and outputs the data to be transferred according to the change of the data complete signal ▲ ▼ to the low level. Instruct to confirm. Also, the main memory 3 is
Although not particularly limited, data complete signal ▲
▼ is output to the main processor 1 and the coprocessor 2, and the low level change of the data complete signal ▲ indicates that the main memory 3 has taken in the data to be transferred. Main processor 1 for transferring data and commands
The status interface between the coprocessor 2 and the coprocessor 2 is performed by the coprocessor status data CPST output from the coprocessor 2 to the interface controller 13. This coprocessor status data CPST is
Although not particularly limited, the internal state of the coprocessor is indicated by 3 bits. For example, a combination of 3 bits can be used to receive a transfer command, execute a command, generate an error during command execution, and terminate data execution. It means ready for transfer. When the main processor 1 instructs the coprocessor 2 to execute an operation and stores the operation result in the main memory 3, the coprocessor 2 outputs the coprocessor status data CPST according to the value of the 3-bit combination. When the main processor 1 identifies that the preparation for the transfer of the data obtained by the completion of the operation execution of 2 is completed, the processing procedure of the main processor 1 transfers the data from the coprocessor 1 to the main memory 3 based on this. The main processor 1 starts the control of the bus cycle in accordance with this. In particular, when the data output from the coprocessor 2 is stored in the main memory 3, the interface controller 13 included in the main processor 1 is based on various interface signals supplied to it and control signals supplied from the instruction control unit 6. , The cache controller 12 is synchronously controlled in response to the control of the bus cycle, and the main memory 3
Access from main processor 1 to address bus 5
The data DAT output from the coprocessor 2 to the data bus 4 corresponding to the address signal ADRS output to the operand cache memory 11 is controlled. Next, the operation of storing the data output from the coprocessor 2 in the main memory 3 will be described with reference to the time chart of FIG. The coprocessor 2 performs arithmetic processing according to the command given from the main processor 1 and, for example, when a predetermined arithmetic processing is completed, it gives the coprocessor status data CPST to the main processor 1 at time t ₀ and outputs the bit By the combination of, the transfer preparation completion of the data obtained by the arithmetic processing is instructed. As a result, based on the instruction from the interface controller 13 that receives the coprocessor status data CPST, the processing procedure of the main processor 1 is branched into a microflow for transferring data from the coprocessor 2 to the main memory 3, and the data transfer is performed. The interface controller 13 changes the coprocessor data enable signal ▲ ▼ to a low level at the time t ₁ synchronized with the machine cycle MCYC while calculating the required address and the like in the execution unit 7, and transfers the data to the coprocessor 2. The output is instructed, and the read / write signal R / is changed to the low level to instruct the main memory 3 to write the data. Then, at time t ₂ one machine cycle later, the main processor 1 activates the bus cycle required for data transfer. That is, the bus start signal ▲ ▼ is changed to the low level to notify the coprocessor 2 and the main memory 3 of the start of the bus cycle, and the address signal ADRS corresponding to the address for data transfer is output from the input / output control unit 8. Furthermore, by the bus access type data BAT,
It is externally instructed that the transfer target is the operand data calculated by the coprocessor 2, and the size of the data to be transferred at this time is instructed by the byte control data ▲ ▼. Wait for the timing at which the address signal ADRS output from the main processor 1 is fixed on the address bus 5,
When the address strobe signal ▲ ▼ is changed to the low level at t ₃ , the coprocessor 2 substantially starts outputting the data DAT, and the output data DAT is fixed on the data bus 4 at the timing t. ₄ to vary the data complete signal ▲ ▼ to the low level. The main memory 3 which receives this takes in the data DAT fixed on the data bus 4 internally through a data input latch circuit or the like not shown, and at the timing (time t ₅ ) when the data is completed, the data complete signal ▲ ▼ To low level. As a result, the main memory 3 writes the data DAT output from the coprocessor 2 in a predetermined storage area corresponding to the address signal ADRS at time t ₆ . By the way, the data DAT output from the coprocessor 2
Is stored in the main memory 3, the interface controller 13 included in the main processor 1 responds to the control of the bus cycle on the basis of various interface signals supplied thereto and the control signal supplied from the instruction control unit 6. The data DAT output from the coprocessor 2 by controlling the cache controller 12 and the low level change of the data complete signal ▲ ▼ is transferred to the data bus 4.
When it is detected that the data has been determined above, the data DAT output from the coprocessor 2 to the data bus 4 in response to the address signal ADRS output from the main processor 1 to the address bus 5 for accessing the main memory 3 is detected. Is controlled by the operand cache memory 11. As a result, the data DAT is also written in the operand cache memory 11 in correspondence with the same address as the address of the main memory 3 in which the data DAT is written. This write timing is substantially the same time t ₆ ′ as the write timing t ₆ for the main memory 3, and the main memory 3 and the cache memory 11 share the same data in the same machine cycle. In this way, when the data DAT output from the coprocessor 2 is stored in the main memory 3 and written in the operand cache memory 11, the address strobe signal ▲ ▼ is negated and the data transfer operation ends. According to the above embodiment, the following operational effects are obtained. (1) When the data DAT output from the coprocessor 2 is stored in the main memory 3, the main processor 1 that controls the bus cycle required for it stores information necessary for the operation, that is, the address signal ADRS, transfer The interface controller 13 included in the main processor 1 has various interface signals, such as a data complete signal ▲ ▼, which has information on the size of data to be transferred and information on the type of bus access such as the type of transfer target data and the transfer direction. , ▲ ▼ allows the user to know the definite state of the data DAT output from the coprocessor 2 and also the taking state of the data DAT by the main memory 3, so that the interface controller 13 can externally supply various interface signals and commands. Control signal supplied from the control unit 6 Based on, the cache controller 12 in response to control of the bus cycle
Are controlled synchronously to correspond to the address signal ADRS output from the main processor 1 to the address bus 5 for accessing the main memory 3, and the data DAT output from the coprocessor 2 to the data bus 4 is transferred to the operand cache memory. 11 can also be loaded in the same machine cycle. (2) Due to the above effects, when the calculation result of the coprocessor 2 is stored in the main memory 3, the data DAT output from the coprocessor 2 is directly taken into the main memory 3 via the data bus 4, and Processor 2
The data DAT output from can be efficiently stored in the main memory 3. (3) According to the above operation and effect (1), when the calculation result of the coprocessor 2 is stored in the main memory 3, the data DAT output from the coprocessor 2 is directly taken into the main memory 3 via the data bus 4. , The cache memory 11 in the case where the data DAT output from the coprocessor 2 is stored in the main memory 3 by being fetched into the operand cache memory 11 built in the main processor 1 at substantially the same timing or at the same machine cycle. It is possible to maintain the consistency of the data shared and held with the main memory 3 with respect to the same address. (4) Due to the above-described effects, the operation efficiency of the entire coprocessor system can be improved and the reliability of the data processing operation can be improved. The invention made by the inventor of the present invention has been specifically described below based on examples, but the present invention is not limited thereto and can be variously modified without departing from the scope of the invention. For example, the control signal of the bus cycle by the main processor is not limited to that in the above embodiment, but can be changed as appropriate. For example, the data complete signal ▲ ▼ output from the memory may be supplied only to the main processor. Although the main processor, the coprocessor, and the main memory are representatively shown in the coprocessor system of the above-described embodiments, various other bus master modules and slave modules can be included as peripheral devices. In the above description, the invention made by the present inventor was mainly applied to a coprocessor system including a main processor such as a microprocessor having a cache memory formed on the same semiconductor substrate, which is the field of application of the invention. However, the present invention is not limited thereto,
It can be widely applied to various data processing systems including small, medium and large sized computers. [Effects of the Invention] The effects obtained by the representative one of the inventions disclosed in the present application will be briefly described as follows. That is, when the main processor instructs the coprocessor to output data, the main processor fetches the output data of the coprocessor into an internal circuit block such as a cache memory and the memory cycle for transferring the output data to the memory. Since the control and the control can be performed at the same time, when the operation result of the coprocessor is stored in the memory, the data output from the coprocessor is directly taken into the memory via the data bus and is also stored in the main processor. The data output from the coprocessor can be efficiently stored in the memory by being taken into the built-in cache memory as well as the cache memory used when storing the data output from the coprocessor in the memory. Shared with memory for the same address There is an effect that it is possible to maintain the integrity of the data.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an embodiment of a coprocessor system according to the present invention, FIG. 2 is a block diagram showing an example of an input / output control unit in a main processor, and FIG. 6 is a time chart for explaining an operation for transferring data output from the processor to the main memory and fetching the data in the operand cache memory of the main processor. 1 ... Main processor, 2 ... Coprocessor, 3 ... Main memory, 4 ... Data bus, 5 ... Address bus, 6
...... Command control unit, 7 ...... Execution unit, 8 ...... Input / output control unit, 10 ...... Memory management unit, 11 ......
Operand cache memory, 20 ... Associative memory, 21
...... Data memory section, 12 …… Cache controller,
13 ... Interface controller, DAT ... Data, A
DRS ... Address signal, CPST ... Coprocessor status data, BAT ... Bus access type data, ▲
▼ …… Byte control data, ▲ ▼ …… Bus start signal, ▲ ▼ …… Coprocessor data enable signal, R / …… Read / write signal, ▲ ▼ …… Address strobe signal, ▲ ▼, ▲ ▼ …… Data complete signal.

Claims (1)

(57) [Claims] An address bus and a data bus, and a main processor commonly connected to the address bus and the data bus,
It has a coprocessor that performs an operation according to an instruction from the main processor, and a memory whose access is controlled by the main processor, and the main processor holds the data held in the memory in association with the address of the data. The main processor includes a cache memory and a cache controller for controlling the cache memory, and the main processor gives a signal for instructing a data output operation to the coprocessor when storing operation result data by the coprocessor in the memory. An instruction signal for a write operation is given, and an address signal for accessing the memory is output to the address bus. The coprocessor receives the instruction signal for the data output operation and outputs data to the data bus. The above memory is the write operation In response to the instruction, the data on the data bus is written to the address specified by the address signal on the address bus. The cache controller is used when the main processor stores the operation result data by the coprocessor in the memory. A coprocessor system for holding the data of the data bus in the cache memory in correspondence with an address signal output from the main processor to the address bus.