JPH0467241A - Cache system - Google Patents

Abstract

PURPOSE:To enable a CPU to carry out the exceptional data processing by producing an interruption when an abnormal bus access signal is inputted while a cache is reading plural remaining data and informing an external device of the abnormality of a bus access. CONSTITUTION:When a cache 2 decides a cache miss, the continuous data including the single data undergone a read access of a CPU 1 are read out of a memory system 3 formed on a system bus. If an abnormal bus access request signal is inputted at read of a 1st word, the accesses are carried out with the address signals received from the CPU 1 and the cache 2. Then the cache 2 discontinues the accesses for a 2nd and succeeding word. Meanwhile the cache 2 outputs an interruption signal INT to an interruption controller 21 when the abnormal bus access request signal is inputted at read of the data on the 2nd - 4th words. Thereafter the controller 21 can request the CPU 1 for the interruption processing. Therefore the CPU 1 can perform the processing to an abnormal bus access.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention provides that when an abnormal bus access signal is input when reading multiple data from a memory system at the time of a cache miss, the cache receives an error request from the memory system. This relates to a cache method that can reliably handle errors.

[Conventional technology]

FIG. 4 is a block diagram showing a CPU and a cache peripheral part as an example of a cache system to which a conventional cache method is applied. This example shows a configuration in which memory system 3 is accessed only in block transfer mode, which transfers multiple pieces of data from memory system 3 when cache 2 misses a single data read access from the CPUI. There is.

The configuration will be explained with reference to FIG. A system bus buffer 6 is provided as a common interface between the CPU 11 cache 2 and the system bus 38. Signals between these can be broadly classified into control signals, address signals, and data signals, and control signal SCa is used as a bidirectional common control signal between CPL II, cache 2, and data bus 6. On the other hand, the control signal SCb 1, which is used only when the CPU is the bus master, is the CPU, cache 2, and c.
It is used as a bidirectional signal between pUl and system bus buffer 6.

The control signal SCb 14 that is input to the CPUI is the one that has passed through the OR circuit 9 between the ready signal SCb 12 that is output from the cache 2 and the ready signal scc 12 that is output from the memory system 3 via the system bus buffer 6. This is used to notify the CPUI of the end of data transfer. Note that the ready signal SCb 12 is used as a cache hit signal when a cache hint is made.

The control signal SCc 15 is an abnormal bus access signal for read access from the memory system 3, and is sent to the CPU along with the ready signal 5Cc12 from the error detection circuit 20.
Output to I or cache 2. This signal is used, for example, to notify that the read access operation was inappropriate. SCe is an operation permission signal from the cache 2 to the memory system 3, and SCf is used to control the CPU 1 from the cache 2 to stop executing new bus cycles and not to activate address signals or bus control signals. Ru.

Address signal AO: 27 is CPU1 → cache 2, C
Address signals A28:29 are signals transmitted from PUI to the system bus buffer 6 and are used only when the CPU is the bus master.
Signals transmitted to multiplexer 8, address signals CA28:29 used only when cache 2 is the bus master
serves as a signal transmitted from cache 2 to multiplexer 8.

Multiplexer 8 follows address signals A28:29, C according to multiplexer control signal SC2 from cache 2.
Either one of A28:29 is set as address signal AD2B=
29, it has a function of outputting to the system bus buffer 6. Note that the data signal SD is used as a bidirectional common signal between the CPU 1, cache 2, and system hash buffer 6. Note that the control signal output from the CPUI or the cache 2 is output as L active. Further, φ is a clock transmitted to the CPU 1 and the cache 2. In addition, 10 is an abnormal bus access detection circuit, 11.12.13 is SCe, SC2, SC
f control circuit, 20 is an error detection circuit, and C3T is a hash access stop signal.

In such a configuration, the case where the CPUI uses the cache 2 and there is a cache hit and a cache miss will be described. In the following description, it is assumed that the read access of single data by the CPU is performed on the cache 2, so it is assumed that the control signal SCa enables the cache 2. In the conventional system configuration shown in Figure 4, the CPUI is configured as shown in Figure 6 (
Timings T1 to T4 of the clock φ in a) (in the figure, T
1234) is one bus cycle, and in a single data read access, there are 2 bus cycles without a wait.
The operation is completed in a bus cycle. Figure 6 shows the CPU
In a read access to cache 2 for single data from I, execution of a no-wait operation is shown when a cache hit is made. Here, the signals in FIG. 6(b) to (el) indicate the signals output from the CPUI, and the address signal AO:27 (address value m) is the upper 2nd address.
8 bits, address signal A28:29 (address value n)
indicates the lower two bits of the address (Fig. 6(b),
(C)).

Control signals SCb 10, SC in FIGS. 6(d) and (e)
b11 are both signals included in the control signal scb, and the former is a signal that indicates that the CPU 1 will start bus access to an external device, so the rising edge of timing TI (hereinafter indicated as T1↑) is one bus cycle. This is a signal that is asserted for a period of time. The latter is a signal that expects data to be confirmed, and starts asserting at timing T4↑ when control signal 5CblO is asserted. On the other hand, Fig. 6 (f
) to (j) are signals output from the cache 2, and the ready signal 5Cb12(
6 (f)), a data signal SD (Fig. 6 (phantom)), a control signal SCe (Fig. 6 (h)) requesting permission for operation from the memory system, and a cache 2 cp
There is a new control signal SCf (FIG. 6(I)) for Ul that stops the activation of the bus cycle. Further, SC2 in FIG. 6(0) is a multiplexer control signal, and FIG. 6('k) shows the cache state.

Here, in order to explain the internal operation of cache 2, the fifth
The figure shows an internal block diagram of cache 2.

An example of this is CQ Publisher's magazine "Interface, Aug.
, 1987 (P2S5) J, and shows a two-step associative system. However, this diagram only describes the parts related to the basic operation of the cache.

As shown in FIG. 5, the internal blocks of cache 2 are:
Broadly divided into a tag address memory 31 and a data memory 33 that store addresses of the memory system 3, which is the main memory.
Consisting of Address signal AO input from outside: 29
is tag address AO:19: entry address A20
:27, word address A28:29 or CA28:2
Of these, entry addresses A20:27 are decoded by the decoder 30 and given to the tag address memory 31 and data memory 33 as entry signals (ENTO-255). Here, the tag address memory 31 is LRU (Least Recently Used) when the cache 2 misses a read.
d) updated by 34 to the address that accesses the memory system 3; Furthermore, four words of data corresponding to the updated tag address AO:19 are stored in the data memory 33 according to the word address AD28:29. At this time, there is a valid pit memory 32 in the same entry that indicates that the stored data is valid.
Make this valid.

The operation of the lead pushbutton will be explained with reference to FIGS. 4 to 6. As shown in Figure 6, CPU1 to 5Cb
lO (FIG. 6(d)) is asserted, and the address signal A
O:27. A28:29 (Figure 6(b), (C1)
starts outputting. Cache 2 this bus cycle
This state is called state SRI (FIG. 6, 0c)), and it is determined whether cache 2 has been hit during this period. Here, inside the cache 2, an address signal AO19 is input, and a comparator 35 compares the contents of the tag address memory 31 on the entry specified by the entry address A20:27 with the tag address Ao:19 every two ways. Compare each. Then, if the address matches the contents of either tag and the bind bin 32 is valid, it is determined that the cache hit has occurred, and the cache hit is executed during the next bus cycle, state 5R2H (FIG. 6(k)). Ready signal 5Cb12 (Fig. 6(f))
) is passed through the OR circuit 9 in FIG. 4 (7) to generate the ready signal 5Cb.
14 to the CPUI. Furthermore, the requested data is obtained by selecting the word select 36 from the data memory 33 according to the word address A28:29, and inputting the way select signal 3 from the comparator 35 to the way select 37.
The way hit by 8 is output to the CPUI.

Next, a method and operation of reading 4 words of data including a single piece of data for which a read access request was made from the CPUI due to a cache miss will be described. When the cache 2 determines that there is a cache miss, the CP is transferred from the memory system 3 on the system hash SB using the round-robin method.
Consecutive 4 containing a single piece of data read accessed by the UI
Read word data. FIG. 7 shows a time chart of normal access operation in non-burst read mode due to this read cache miss. In Figure 7,
(b) - (el is a signal output from the CPUI as in Fig. 6, (fl - (Jl is a signal output from the cache 2 as in Fig. 6)
(k) to (b) show signals output from the system bus buffer 6.

First, in the state SRI (Figure 7(n)) where a read access request was made from the CPUI, the cache 2
When the CPU determines that there is a cache miss, it sends a ready signal 5Cb12 (see FIG.
g)) is not asserted, and the control signal S Ce (Fig. 7 (
hl) Assert to the system bus buffer 6 to activate the read operation for the memory system 3. Cache 2 receives multiplexer control signal SC2 (see FIG. 7).
j)) is asserted to the multiplexer 8, and the address signal CA28:29 is output from the cache 2.
(Address value n accessed from CPUI, Fig. 7 (
f)) The address signals A028:29 are outputted to the memory system 3 through the system bus buffer 6. The ready signal 5Cc12 (FIG. 7 (kl)) transferred from the memory system 3 to this address is input to the cache 2 and simultaneously inputted from the OR circuit 9 as the CPUI ready signal SCb 14.At this time, In state SR2M (FIG. 7(n)) of this bus cycle, the CPU further asserts a control signal SCf that stops the activation of a new bus cycle.A ready signal SCc is passed from the memory system 3 to the system buffer 6.
12 and data signal SD ((2) in FIG. 7) are asserted, the CPUI and cache 2 are activated at timing T3.
Sample at the same time with ↓ and read the data. At this time, if the read response from memory system 3 is slow,
By delaying the assertion of the ready signal SCc 12, reading data from the CPUI and the cache 2 can be delayed. Then, the CPU1 outputs a control signal 5cbll.
(FIG. 7(e)) is negated to complete the single data read access.

The control signal SCf (Fig. 7 (1) has already been sent from the cache 2
)) is asserted, the next bus cycle of CPUI is not asserted and address signal A017 (I
ll), A28:29(n) retains its previous value. During this time, the CPU 1 can continue executing internal processing (for example, pipeline processing). On the other hand, cache 2 subsequently receives address signals CA28:29 (FIG. 5(f)
)) by the round tropin method: H+l, n+2. n+
3 and accesses the memory system 3 sequentially to access the corresponding 2nd . Third. Read the data of the fourth word. At this time, inside Catshu 2,
As shown in FIG. 5, 4 words of data are written in the data memory 33 of the update way designated by the LRU 34 according to the address signals CA28:29, and the valid bit 3
2 becomes valid.

Note that when cache 2 is outputting n+3 as address signals CA28:29, CP
Control signal SC so that the UI can be accessed normally
f (Fig. 7 (1)) and read the fourth word data, the control signal SCe (Fig. 7 (-)
is negated to stop outputting address signals CA28:29. Note that SCc 15 in FIG. 7+1) is an abnormal bus access signal.

Here, let us consider, for example, the case where the memory system 3 has a parity check function or the like. When cache 2 has a cache miss and reads 4 words from memory system 3 using the round-robin method, address signal AO: 27 (b) output from CPU 1 and address signal CA 28: 29 (n-n+3) from cache 2.
The operation when an error is determined as a result of parity checking of the data output from the memory system 3 by the error detection circuit 20 shown in FIG. 4 in accessing the first to fourth words determined by the following will be described.

For example, if the memory system 3 has a parity check function, when the cache 2 misses the cache and reads 4 words from the memory system 3 using the round-robin method, the address signal output from the CPU 1 is first read. ADI (e) and address signal CA D 2 from cache 2 (first word access determined by nl)
When an error is determined as a result of checking the data output from the memory during an access to the same address at which the CPU 1 first accessed the cache 2, the following operation is performed.

In response to the occurrence of this error, the memory system 3 responds to the abnormal bus access signal 5CC15 (
Figure 8 (1)) and ready signal SCc12 (Figure 8 (k)
) (hereinafter, these signals are collectively referred to as the abnormal bus access request signal) and is transmitted to the CPUI and the cache 2. Assertion of these signals causes CP
The data accessed by the UI is also read by the cache 2 at the same time, and when it is determined that there is an abnormal bus access, the CPU must invalidate the data and execute processing for this abnormal bus access. On the other hand, cache 2
determines that the first word data was an abnormal bus access, and the four words of data read in block transfer mode must be invalidated without being stored in the cache. At this time, without reading the remaining three words for this abnormal bus access cycle, the abnormal bus access detection circuit 10 in FIG.
Each control circuit 11°12 of C2 (Fig. 8 (hl to (J))
．． 13, and negates these signals, causing the cache 2 to abort the block transfer midway.

As a result, the CPU 1 can quickly execute processing for abnormal bus access, for example, as the next bus access. Note that although this application describes only parity errors, the same applies to other errors. In FIG. 8, (b) and (C) are address signals output from CPU 1, (f) is an address signal output from cache 2, and the other signals are the same signals as in FIG. 7. .

Next, the operation will be explained with reference to the time chart of FIG. 9 when the cache 2 performs non-burst read. Here, the cache 2 misses and the error detection circuit 20 sends the abnormal bus address signal 5Cc15 (FIG. 9 (1)
)) and ready signal 5Cc12 (Fig. 9(k)) (
Since the operation is the same as that shown in FIG. 7 until the signal (hereinafter collectively referred to as the abnormal bus access request signal) is asserted, the operation after the signal is asserted will be described. This is because when the cache 2 is reading the second word data after a cache miss as shown in FIG. 9, when the abnormal bus address request signal is asserted from the system bus SB, the address AO:2T, The valid bit 32 specified by CA28:29 is invalidated, and the corresponding data is invalidated. Cache 2 was configured to continuously read the second to fourth words of this 4-word unit access, so even if an abnormal bus access is input at the second word, it will continue to read emptyly. . Then, address signals CA28:29. Control signals SCe, SCf.

Negate SC2.

At this time, an abnormal bus access request signal is generated at the address accessed by cache 2, so in order to maintain reliability of this system, CPU 1 needs to execute processing for the abnormal bus access of cache 2. However, in the configuration of the conventional cache system shown in FIG. 4, there is no means to notify this to the CPU 1, so the reliability of the system cannot be maintained.
rt> signals are similar to the signals in FIGS. 8(a) to (n).

[Problem to be solved by the invention]

In this way, in the conventional cache method, the CPU makes a read access to the cache for a single piece of data and causes a cache miss, and when the cache reads the data of the first to fourth words, the CPU and the cache operate in parallel. After reading the first word, if the abnormal bus access request signal is asserted in the second to fourth words in which only the cache is read, the CPU has already completed the read request for the first requested data (first data). Because there is C
It was not possible to notify the PU. For this reason, it has been necessary to either reduce the reliability of the system or provide another device externally to notify the CPU. For this reason,
Under these conditions, the cache must promptly notify the CPU of an abnormal bus access request and process it without adding as many external devices as possible.

[Means to solve the problem]

In order to solve such problems, the present invention generates an interrupt signal in response to assertion of an interrupt generation request signal from an abnormal bus access detection circuit, and inputs a bus access in progress signal from the same abnormal bus access detection circuit. , the remaining data accesses can also be stopped.

[Effect]

According to the cache method according to the present invention, after the data at the address specified by the CPU is read into the CPU and the cache as first data, while the data of the second to fourth words are being read only from the cache, Even if an abnormal bus access signal is input from the error detection circuit, the interrupt generation circuit inside the cache can assert the interrupt signal from the cache and notify the external interrupt controller, which reduces the reliability of the system. It is possible to cause the CPU to execute exceptional data processing.

〔Example〕

Embodiments of the present invention will be described using FIGS. 1 to 3.

FIG. 1 shows a CPU 1.0 as a cache system to which an embodiment of the present invention is applied. FIG. 3 is a configuration diagram showing the peripheral portion of the cache. This example shows a configuration in which the memory system 3 is accessed only by block transfer in which multiple pieces of data are transferred from the memory system 3 when the cache 2 misses a single data read access from the CPUI. Regarding the numbers, device names, and signal names in FIGS. 1 to 3, the same or equivalent parts as in FIGS. 4 to 9 are given the same reference numerals. The system shown in FIG. 1 also includes a new interrupt generation circuit 14 inside the cache 2, and when an abnormal bus access request signal is input, an interrupt signal INT (FIG. 2(k), FIG. 3(k)
)) This system differs from the system shown in FIG. 4 in that it has a function of generating.

In such a configuration, cases of cash hit and cache miss will be explained. In the following description, it is assumed that the CPUI accesses the cache 2, so it is assumed that the control signal SCa enables the cache 2.

In the cache system of FIG. 1 to which an embodiment of the present invention is applied, the CPU 1 operates at timings T1 to T4 (T1234 in FIG. 6) of the clock φ, as shown in FIG.
) is defined as one hash cycle, and in a single word read access, the operation is completed in two pass cycles without a wait. FIG. 6 shows execution of a no-wait operation when a cache hint occurs in a read access from the CPUI to the cache 2 for single data. This is the same as the operation of the cache system shown in FIG. 4 in the previous example, and the explanation for the cash hit is also the same as in the previous example, so the explanation thereof will be omitted.

Next, a method and operation of reading four words of data including a single piece of data for which a read access request was made from the CPU 1 due to a cache miss will be described. cache 2
When the CPU determines a cache miss, it is transferred from the memory system 3 on the system bus SB to the CPU in a round-robin manner.
1 reads consecutive four words of data including the single data read accessed. The time chart for normal access due to read cache miss in this embodiment is the same as that in FIG. 7 of the preceding example.

Here, when reading 4 words of data including a single piece of data for which a read access request was made from the CPU due to a cache miss, for example, an abnormal bus access signal SCc 15 and a ready signal 5Cc12 are sent from the error detection circuit 20 on the system bus SB. (Hereinafter, these signals will be collectively referred to as the abnormal lot access request signal) will be described regarding the operation when the signal is asserted. Here, the timing at which the abnormal bus access request signal is input will be explained by dividing into two timings: when reading the data of the first word and when reading the data of the second to fourth words.

If it is input when reading the first word, the address signal AO:27 (e) output from the CPUI and the address signal CA28:29 (n
), and as explained in the prior art example, cache 2 stops accessing the second and subsequent words. Since the CPU 1 also samples the first word at the same time that the cache 2 samples the data of the first word, the CPU 1 can thereafter process the abnormal bus access request.

Further, FIG. 2 shows a time chart when an abnormal bus access request signal is input when reading data of the second to fourth words. When these signals are input, the specified address AO shown in FIG. 5 is executed inside the cache 2:
27 (e) is invalidated, and the corresponding data in cache 2 is invalidated. On the other hand, the abnormal bus access detection circuit 10 sends an interrupt generation request signal IREQ to the interrupt generation circuit 14, and outputs an interrupt signal INT to an external interrupt controller 21.

After this, the interrupt controller 21 can request the CPU 1 to handle this interrupt, so the CPU
is capable of handling abnormal bus accesses.

In FIG. 2, after the abnormal bus access signal is input, the remaining 3. To read the fourth word, the CPU 1 starts a new hash access cycle by continuing the empty reading and negating the control signal S(:, e, SC2 and negating the control signal SCf to the CPUI). I'm trying to make it possible.

FIG. 3 shows that when the abnormal bus access request signal is input when reading the second word, the cache 2 stops reading the remaining data and uses the access control signals SCe, SC2, SC.
This is a time chart when it is also possible to negate f.

In addition, if an abnormal bus access request signal is generated from the outside, a latch function that stores the address value inside cache 2, the type of abnormal bus access request, the data at that time, etc. can be provided. You can perform more reliable error handling.

〔Effect of the invention〕

As explained above, in the present invention, when a cache miss occurs in response to a single data read request from the CPU to the cache, the cache does not return a ready signal and the CPU
When starting the memory system and reading multiple data by block transfer, the CPU and Karatsuyu read the data requested by the CPU in response to the ready signal from the memory system, complete the CPU read cycle, and fill up the remaining cache. When an abnormal bus access signal is input while reading multiple data, the cache generates an interrupt and notifies the external device that the bus access is abnormal, thereby preventing system reliability from being degraded ( , there is an effect that the CPU can execute exceptional data processing.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a cache system to which an embodiment of the present invention is applied, and FIG. 2 shows an abnormal bus access signal when cache 2 causes a read cache miss and reads data of the second word in the system of FIG. Figure 3 is a time chart in which the remaining accesses are controlled to be canceled when the abnormal bus access signal is asserted. Figure 4 is a cache system to which the conventional cache method is applied. Configuration diagram, 5th
The figure is an internal basic block system diagram of the cache of the cache system shown in Figs. 1 and 4, and Fig.
A time chart when a cache hint is used for a single data read access, which is common to the systems shown in the figure. Figure 7 is a time chart when a cache miss occurs and the access is normal in the systems shown in Figures 1 and 4. , 8th
FIG. 9 and FIG. 9 are time charts when the abnormal bus access signal is asserted when the cache misses the read cache and reads the data of the second word in the conventional configuration.

Claims (1)

[Claims] C connected directly or indirectly to the same system bus
In a cache system consisting of a PU, cache, and memory, when a cache miss occurs in response to a single data read request from the CPU to the cache, the cache does not return a ready signal and makes the CPU wait and starts the memory system. However, when reading multiple data by block transfer, the CPU and cache read the data requested by the CPU based on the ready signal from the memory system, and finish the CPU read cycle. A cache method characterized in that when an access signal is input, the cache generates an interrupt to notify an external device that the bus access is abnormal.