JPS6356733A - Microcomputer system - Google Patents

Abstract

PURPOSE:To improve an instruction execution speed, etc., without starting a bus cycle which outputs the address of a fetch destination by a microprocessor (MP) by allowing the MP to control the operation of a memory chip directly and perform close coupling operation. CONSTITUTION:An instruction code fetch cycle consists of T3 timing succeeding to one-time T3 timing. The execution control part 100-7 of the microprocessor 100 makes all control signals inactive so as to avoid a collision against a previous bus cycle in the front half of the T1 timing. Thus, the execution control part 100-7 makes an RD signal 105 active in the T3 timing period and controls the rising and falling of an IRD signal 107 to update an IP101-4 continuously, thereby fetching instruction codes continuously from a memory 101-1 where the address information on the instruction code fetch destination is inserted in the output bus cycle in the middle.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a microcomputer system including a microprocessor and a memory.

[Conventional technology]

In recent years, the performance of microprocessors has significantly improved due to improvements in operating frequency due to improvements in process technology, etc., and improvements in architecture such as adoption of a pipeline system, and extremely high-speed instruction execution has been realized. However, when considering a microcomputer system consisting of a microprocessor, memory, peripheral input/output devices, etc., although the inside of the microprocessor can operate at very high speed, due to the limitations of memory access speed, The instruction code fetch cannot keep up with the processor's instruction execution, causing a bus neck and causing the microprocessor's instruction execution to enter a wait state.
Improvement in overall system performance is suppressed.

FIG. 7 shows a conventional example of a microcomputer system consisting of a microprocessor, a program, and a memory for storing data.

The microcomputer system shown in FIG. 7 includes a microprocessor 800 that controls data input/output processing, arithmetic processing, and the entire microcomputer system, and multiplexed address information, instruction codes, and information input/output from the microprocessor 800. An address latch 801 for demultiplexing input/output data, a program memory 802 in which a program executed by the microprocessor 800 is stored, and the microprocessor 80
These units include an address/data bus 804 (hereinafter referred to as AI) bus in which address information, instruction codes, and input/output data are multiplexed; Address bus 805 (hereinafter referred to as A bus) demultiplexed from bus 804 by address latch 801
connected by.

Furthermore, the microprocessor 800 includes a program counter 800-1 (hereinafter referred to as PC) that points to an address in the program memory 802 where an instruction code to be executed next is stored, and an incrementer 800-2 that increments the PC 800-1. , an instruction queue 800-3 that stores instruction codes read ahead from the program memory 802;
, an instruction register 800-4 (hereinafter referred to as IR) that holds the instruction code read from the instruction register 800-3, and an instruction register 800-4 (hereinafter referred to as IR) that decodes the instruction code stored in the IR 800-4 and outputs various control signals related to instruction execution. an instruction decoder 800-5, a processing execution unit 800-6 that executes instruction processing in response to a control signal from the instruction decoder 800-5, and an execution control unit 8 that controls the overall operation of the microprocessor 800.
It consists of 00-7.

From the processing execution unit 800-6 to the execution control unit 800-7,
Data read/read from data memory 803 as instructions are executed
Bus request signal 5 requesting start of write cycle
oo-s (hereinafter referred to as BRQ signal) and an address m carrying address information of the data memory 803 to be accessed.
5oo-9 is output and the execution control unit 800-7 receives the data read/write cycle activation request, and sends an acknowledge signal 800-10 to the processing execution unit 800-6.
(hereinafter referred to as ACK signal) is output from the instruction queue 800-3 to the execution control unit 800-7.The instruction queue 800-3 contains an appropriate number of instruction codes, and the instruction codes can be read. Queue ready signal 5oo-11 (hereinafter referred to as Q a 11 Y signal) indicating that
Then, a queue full signal 800-12 (hereinafter referred to as QFUL signal) indicating that the instruction code in the instruction key -800-3 is full is output.

The microprocessor 800 is connected to an AD bus 04 on which address information and input/output data are multiplexed, and reads instruction codes from the program memory 802 and reads out instruction codes from the data memory 8 through the AD bus 04.
Data is read/written to/from 03.

As input control signals to the microprocessor 800,
There is a reset signal 806 for initializing the hardware (in the microprocessor 800), and as an output control signal from the microprocessor 800, the address latte 801 provides the timing for latching the address information on the AD bus 04. Address latch enable signal 807 (hereinafter referred to as ALE signal Q), read signal 808 (hereinafter referred to as RD double signal) for the microprocessor 800 to read data from data memory 803 and fetch instruction code from program memory 802, There is a write signal 809 (hereinafter referred to as W signal) for writing data into the data memory 803. Here, the R1J signal 808 and the WR signal 809 are row active signals.

Next, the bus cycle operation of the microcomputer system shown in FIG. 7 will be described.

The bus cycle of the microprocessor 800 is composed of three basic operating states and a three-way state consisting of a plurality of clocks. B3
By outputting the three operation signals and the BI double signal indicating that the bus cycle is stalled, the instruction code fetch cycle from the program memory 8o2 and the data read/write cycle with the data memory 803 due to instruction execution are controlled. Controls the bus cycle.

Next, we will show timing charts of two basic bus cycles: (1) instruction code fetch cycle, and (2) data read/write cycle, and explain the operation of each unit. A timing chart of the instruction code fetch cycle is shown in FIG. 8, a timing chart of the data read cycle is shown in FIG. 9-1, and a timing chart of the data write cycle is shown in FIG. 9-2.

(1) Instruction code fetch cycle The instruction code fetch cycle is performed at t31. B2. Consists of three timings: B3.

The microprocessor 800 performs ALE at the Bl timing.
Raise signal 807. Next, in order to avoid contention on the AI) bus 804 with the data in the previous pass cycle, in the latter half of the Bl timing, the address of the instruction code to be extracted next in the program memory 802 is placed on the AL) bus 804. Output the information from PC800-1, and then
The ALE signal 807 falls at the trailing edge of one timing.

The address latch 801 receives the address information on the AL bus 804 at the falling edge of the ALEg number 807.

At B2 timing and B3 timing, A bus 805
At the top, address information is output from the address latch 801.

The microprocessor 800 uses the AI) bus 804 in preparation for the instruction code fetch cycle in the second half of the B2 timing.
After setting the B33 timing to the 70-ting state, R
Activate D signal 808. As a result, A bus 8
Program memory 80 pointed to by the address information on 05
From 2 onwards, data begins to be output on AD bus 0=1.

And the microprocessor 8oo has an Al) bus 80
The instruction code on the AD bus 04 is taken into the instruction queue 800-3 at a predetermined clock within the B3 timing when the instruction code read on the AD bus 04 becomes valid.

(2) Data read/write cycle The data read/write cycle is similar to the instruction code fetch cycle.
Bl, B2. It consists of 3 timings of B3.

The microprocessor 800 performs ALE at the Bl timing.
Raise signal 807. Next, in order to avoid contention on the AI) bus 804 with data in the previous bus cycle, in the latter half of the B1 timing, the data memory of the access destination is output from the processing execution unit 800-6 to address 1soo-9. Address information in 803 is transferred to At) bus 804
Then, at the trailing edge of the B1 timing, the ALE signal 807 falls. Address latch 801 is ALE
At the falling edge of the signal 807, the address information on the AD bus 04 is input. At B2 timing and B3 timing, address information in the data memory 803 to be accessed is output from the address latch 801 onto the A bus 805.

For data read cycles, the microprocessor 80
0 makes the RD signal 808 active during the B3 timing period after setting the AD bus 04 in a floating state in preparation for a read cycle in the latter half of the B2 timing. As a result, data starts to be output onto the AD bus 04 from the data memory 803 pointed to by the address information on the A bus 805.

The microprocessor 800 then runs the AD Babus 04
The data on the AD bus 04 is input at a predetermined clock within the B3 timing when the data read above becomes valid.

For data write cycles, the microprocessor 80
0 activates the W signal 809 during the B3 timing period and outputs the write data on the AI) bus 804. Then, at a predetermined clock within the B3 timing when the data on the At) bus 804 becomes valid, the data on the AI) bus 804 is written to the data memory 803 indicated by the address information on the A bus 805.

In this way, the instruction code fetch cycle from the program memory 802 and the data read/write cycle with the data memory 803 associated with instruction execution are executed in the same number of bus cycles, and one bus cycle consisting of B1, B2 and B3 is executed. In each cycle, one of instruction code fetch, data read, and data write is performed.

The execution control unit 800-7 receives the QRDY signal 800-11 and the QFUL signal 800- from the instruction queue 800-3.
12 and a BRQ signal 800 from the processing execution unit 800-6.
-8 depending on the state of Bl, B2. B3. In addition to controlling the output timing of the basic timing signal of BI, it also controls the starting priority of the data read/write cycle and the instruction code fetch cycle. Show and describe.

QRI) When the Y signal 800-11 is active, the first
FIG. 11 shows a case where the QRI)Y signal 800-11 is inactive.

(1) If the Q-DY signal 800-11 is active, the Q
When RDY signal 800-11 is active, BR
While the Q signal 800-8 is inactive, the QFUL signal 800-12 is output from the instruction queue 800-3 until the instruction code in the instruction queue 800-3 becomes full.
Initiate an instruction code fetch cycle. When the QFUL signal 800-12 from the instruction queue 800-3 becomes active, the execution control unit 800-7
Q signal 800-8 becomes active or QF
BI is output until the LIL signal 800-12 becomes inactive again, keeping the Babas cycle in an idle state.

When the BRQ signal 800-8 becomes active, the start priority of the data read/write cycle is higher than the start priority of the instruction code fetch cycle. Initiate a read/write cycle.

FIG. 10 shows a case where a data write cycle is accepted during a BI cycle.

(2) When the QRDY signal 800-11 becomes inactive When the QRDY signal 800-11 becomes inactive, the instruction code fetch cycle is started continuously regardless of the state of the BRQ signal 800-8. do.

In this case, since the priority order after activation of the instruction code fetch cycle is higher than the priority order after activation of the data read/write cycle, even if the B-Q signal 800-8 becomes active, consecutive instruction code fetch cycles By Q
Activation of the data read/write cycle is delayed until the RDY signal 800-11 becomes active.

FIG. 11 shows a case where activation of the data write cycle is delayed until the QRff)Y signal 800-11 becomes active.

[Problem that the invention seeks to solve]

In the above-mentioned conventional microcomputer system, multiplexing of addresses and data is caused by limitations from memory access speed and limitations on the number of pins of the package.
The number of cycles required for instruction code fetch and data read/write pass cycles is increasing, and as a result, the time required to fetch the instruction code for the instruction is relatively longer than the instruction execution time in the microprocessor. As a result, path necks are occurring more frequently.

When this pathneck occurs, not only is it impossible to obtain the effect of prefetching the instruction code by providing an instruction queue, but also
Due to a lack of instruction codes in the instruction queue, the microprocessor's instruction execution itself is forced to wait, or the microprocessor prioritizes the activation of the instruction code 7 etching cycle, causing data read/write cycles to start in conjunction with instruction execution. As a result, the instruction execution time is extended for a long time, which wastes hardware resources related to instruction execution and reduces the performance of the entire system.

Furthermore, many additional nodes such as latches and drivers are required between the microprocessor and the memory, which impairs the economic efficiency of the system and reduces reliability due to an increase in the number of parts.

[Means for solving problems]

The microcomputer system of the present invention includes a first storage means and a second storage means (hereinafter simply referred to as storage means unless otherwise specified) that store various data and programs, and data processing by executing instructions based on a program jlC. a data processing means to perform the processing, a selection means for selecting either the first storage means or the second storage means, and a transfer control means for controlling the transfer of the processed data to and from the storage means and the transfer of the program from the storage means. an instruction storage means for storing the instruction code of the program read from the storage means prior to execution of the instruction; an instruction means for storing positional information of the storage contents of the storage means; and an update means for updating the contents of the instruction means. ), the transfer control means, following the sending of the selection information by the selection means and the sending of instruction information instructing the read destination and the data transfer destination in the data transfer between the storage means and the data processing means, a first transfer means for transferring data to a storage means specified by the instruction means; and a first transfer means for transferring data to the storage means designated by the instruction means; By outputting an update ff11m signal to the second transfer means that performs the transfer and the means for sending and updating selected information by the selection means and updating the contents of the instruction means, the storage means can be stored without sending instruction information. and a transfer selection means for selecting the first transfer means, the second transfer means, and the third transfer means in a predetermined priority order. .

In the present invention, a microprocessor, a pointer pointing to the address of the instruction code fetch destination, an incrementer for updating the pointer, a ROM (first memory) for storing a program and read-only data, and a RAM for storing read/write data The present invention provides a microcomputer system consisting of a memory chip in which a second memory (second memory) and a memory selector for selecting either the first memory or the second memory are provided on a single semiconductor substrate.

In the above configuration, the microprocessor controls the update timing of the pointer in the memory chip. Therefore,
It becomes possible to continuously read instruction codes from the memory in the memory chip without outputting the address of the instruction code fetch destination. As a result, the present invention aims to shorten the critical code fetch cycle, supply a necessary and sufficient amount of instruction codes to the microprocessor, minimize the occurrence of pathnecks, and provide an instruction queue. It enhances the reverse effect of code preemption and has original content regarding improving the performance of microcomputer systems.

Also, when reading and suspending information from memory, it is important to consider whether the information is a program or data, and
By having a mechanism in which the microprocessor independently instructs the memory chip whether to read from OM (first memory) or RAM (second memory), read-only data can be stored in the same ROM as the program. Example 1 Next, an example of the present invention will be described with reference to the drawings.

FIG. 1 shows a block diagram of an embodiment of a microcomputer system according to the present invention.

The microcomputer system shown in FIG. 1 includes a microprocessor 1 (JO) that controls data input/output processing, arithmetic processing, and the entire microcomputer system, a program executed by the microprocessor 100, and processing data necessary for program execution. The memory chip 101 includes a memory 101-1 that stores read-only data and a memory 101-2 that stores read/write data. -1 is a mask ROM.

The memory 101-2 is a RAM.

Next, each constituent unit of microprocessor 100 will be explained. The microprocessor 100 stores the instruction code to be executed next in the memory 1 of the memory chip 101.
Program counter 100 pointing to address within 01-1
-1 (hereinafter referred to as PC), an incrementer 100-2 that increments PCloo-1, and a memory 101.
An instruction queue 100-3 that stores instruction codes read ahead from -1 and an instruction register 100 that holds instruction codes read from the instruction queue 100-3.
-4 (denoted as IR under Ju), and an instruction decoder 100- that decodes the instruction code stored in the box 100-4 and outputs various control signals related to instruction execution.
5, and a processing execution unit 100- that executes instruction processing upon receiving a control signal from the instruction decoder 100-5.
6, and an execution control section 100-7 that controls the overall operation of the microprocessor 100.

The types of control signals and control relationships between the constituent units of the microprocessor 100 will be explained next. Process execution unit 100-
6 to the execution control unit 100-7, a bus request requesting activation of a data read cycle with the memory 101-1 in the memory chip 101 or activation of a data read/write cycle with the memory 101-2 in response to instruction execution. A signal 100-8 (hereinafter referred to as BRQ signal Q), a branch signal 100-9 (hereinafter referred to as BR multiplication signal Q) requesting activation of a branch processing cycle, and memory 101-1 or memory 1
01-2 access destination data address information XA is address 1 carrying the branch destination program address information
00-10 is output, and when the execution control unit 100-7 receives a request to start a data read/write cycle or a request to start a branch processing cycle, the processing execution unit 100-7
An acknowledge signal 100-11 (hereinafter referred to as λCK signal) is output to the instruction queue 100-3 to the execution control unit 100-7. Queue ready number 100-12 indicates that instruction code reading is possible.
(Hereinafter referred to as DY), a queue full signal 100 indicates that the instruction code in the instruction queue 100-3 is full.
-13 (hereinafter referred to as QFUL signal) is output.

The microprocessor 100 is connected to an AL) bus 102 on which address information and input/output data are multiplexed, and the memory chip 10 is connected to an AL) bus 102 on which address information and input/output data are multiplexed.
Read instruction code from memo IJIOI-1 in memory 101-1 and read data from memory 101-1 and memory 1
Read/write data with 01-2.

Next, each constituent unit of the memory chip 101 will be explained. The memory chip 101 is the microprocessor 10
0 executes the program and the microprocessor 100
Memory 101-1 for storing read-only processing data of
, a memory selector 101-3 for selecting either memory 101-1 or memory 101-2, and memory 1.1101-1 for storing processing data for both reading and writing. Inside or memo! Address decoder 1 that selects cells within 7101-2
01-4, an address latch 101-5 for demultiplexing multiplexed address information and input/output data input/output from the AI) bus 102, and an instruction code to be executed next by the microprocessor 100. instruction pointer 101-6 (hereinafter referred to as IP) pointing to the address in the memo IJIOI-1
, an incrementer 101-7 that increments IPIOI-6, and a bus interface section 101-8 that controls operations within the memory chip 101 based on various control signals from the microprocessor 100, which will be described later. are connected by a memory address/data bus 101-9 (hereinafter referred to as MAD bus).

Next, a microprocessor 100 and a memory chip 101
This section describes the control signals that are input and output.

As input control signals to the microprocessor 100,
There is a reset signal 103 for initializing the 7--ware within the microprocessor 100. The address latch 101-5 is the output control signal from the microprocessor 100 to the memory chip 101.
An address latch enable signal 104 (hereinafter referred to as ALE signal) that provides timing to latch address information on the bus 101-9 causes the microprocessor 100 to read an instruction code from the memory IJIOI-1 in the memory chip 101 or read out an instruction code from the memory 101-9. 1 or the read signal 105 (hereinafter referred to as RL) signal for reading data from Memo January 01-2, and Memo January 01-2.
The write signal 106 (hereinafter referred to as WR multiplication signal) for writing data to the memory chip 101 and the timing at which If' 101-6 in the memory chip 101 is incremented by the incrementer 101-7 to fetch the instruction code of the next instruction. and °increment result address information as IPI
An instruction read signal 107 (hereinafter referred to as IRD signal ψ) that provides timing for writing to OI-6, and an instruction that selects whether the address output source for address decoder 101-4 is address latch 101-5 or IPIOI-6. /data signal 108
(hereinafter referred to as I/D signal) and memory selector 101-
M88 times 109 which means whether the memory selection instruction for 3 is the memory IJIOI-1 or the memory 101-2.
(hereinafter referred to as MS signal). RD signal 105 and W
The R signal 106 is a low active signal, i/l
) When the signal 108 is at a high level, IPlol-6 is selected as the address output source to the address decoder.
At low level, address latte 101-5 is selected. When the MS signal 109 is at a high level, the memory selector 101-3 selects the memory 'JIOI' as the specified memory destination.
-1 is selected and at low level, the memo IJIOI-
2 is selected.

Further, the address space of the microprocessor 100 is R
A distinction is made between the OM space and RAM1, which allows access to memory twice the capacity of the address space.

Next, the bus cycle operation of the microcomputer system shown in FIG. 1 will be described.

The bus cycle of the microprocessor 100 consists of three basic operating states and a live state, each consisting of a number of clocks. The execution control unit 100-7 receives basic timing signals TI, T2 . 'I
By outputting the control signals for each block to the memory chip 101 described above according to the three operation signals indicated by '3' and the TI double signal indicating that the bus cycle is idle, and this basic timing signal, the memory 101- Instruction code fetch cycle from 1 and memory 10 associated with instruction execution
1-1 and the memory 101-2, and the bus cycle of the data write vehicle with the memory 101-2.

Next, a timing chart of four basic bus cycles (1) instruction code fetch cycle (2) data read cycle (3) data write cycle (4) branch processing cycle will be shown, and the operation of each unit and control signal will be explained. The timing chart of the instruction code fetch cycle is shown in Figure 2.
The timing chart of the data read cycle when reading data from the memory 101-1 is shown in Part 3-1.
Figure 3-2 shows a timing chart of a data read cycle when data is read from the memory IJ 101-2, and Figure 3-2 is a timing chart of a data write cycle when data is written to the memory 101-2. is shown in FIG. 4, and a timing chart of the branch processing cycle is shown in FIG.

(1) Instruction code fetch cycle The instruction code fetch cycle consists of one T1 timing and consecutive T3 timing.
Consists of timing. The execution control unit 100-7 of the microprocessor 100 makes all control signals inactive during the first half of the T1 timing to avoid conflict with the previous bus cycle.

Next, the execution control unit 100-7 sets the 1/L) signal 108 to high level from the latter half of the TI timing, and further sets the MS signal 109' (i- to high level. As a result, the instruction code in the memory step 101 is Stored memory 101
11'1O1-6 as address output light for -1
is selected, and the bus interface unit 101-8
The value of PIOI-6 is output to the address decoder 101-4, and the memory selector further selects the memory 101-1.

Next, the execution control unit 100-9 (between timing T33)
By activating the LD signal 105, the bus interface section 101-8 transfers the instruction code information in the memory 101-1 pointed to by the IPIOI-6 and the memory selector 101-3 via the MAL) bus 101-9. hand,
Output to AD bus 02.

The execution control unit 100-7 transfers the instruction code on the AL) bus 102 to the instruction queue 100 at a predetermined clock within the T3 timing when the instruction code on the AL) bus 102 becomes valid.
At the same time, the IR and D signals 107, which were at high level, are brought down in the latter half of the 'r3 timing, and T3
Stand up again at the trailing edge of timing.

As a result, the bus interface section 101-8 of the memory chip 101 outputs the address value of IPI O1-6 to the incrementer 101-7 at the falling edge of the If7 signal 107 to increment it, and then
When the signal 107 rises, the incremented address value is written back to I)' 101-6 to update the address information.

Thereafter, the execution control unit Zoo-7 continuously activates the signal 105 during the T33 timing 81) and controls the rise and fall of the IRLI signal 107, thereby performing 5. I
PIOl-6 is updated continuously, and the instruction code is continuously read from the memory 1oi-i pointed to by the updated IPlol-6 without inserting a bus cycle that outputs the address information of the instruction code fetch destination. can be fetched.

During the instruction code fetch cycle, the execution control unit 100
-7 keeps the I/I) signal 108 and the MS signal 109 at high level, thereby causing the bus interface section 1
01-8 selects IPlol-6 as the output source of address information to the memory 101-1.

(2) Data read cycle Data read/write cycle is TI, T2.

It consists of three timings, T3. Further, data reading is performed in both memory 101-1 and memory 101-2.

First, the case where data reading is performed on the memory IJIOI-1 will be explained. The execution control unit 100-7 of the microprocessor 100 raises the ALE signal 104 at the TI timing in order to write address information of the access destination into the address latch 101-5 in the memory chip 101. In response to the rise of the ALE signal, the bus interface section 101-8 opens the input gate of the address latch 101-5, and the address latch 101-5 receives the MAD signal.
The contents of the bus are entered.

Next, in order to avoid conflict with the previous bus cycle, the execution control unit 100-7 outputs the memory IJIOI of the access destination output from the processing execution unit 100-6 to the address ilOO-10 from the latter half of the T1 timing. The address information within -1 is outputted onto the AD bus 02, the ■/D signal 108 is set to low level, and the MS signal is set to high level. By setting the I/D signal 108 to a low level, the address latte 101-5 is selected as the address output source to the address decoder 101-4 in the memory chip 101, and the address information on the AD bus 02 is transferred to the MAD bus 10.
Address decoder 101-4 because it is output on 1-9.
The address information on the AI) bus 102 is
D bus 1o1-9. Addressra: /f Output via 101-5. Furthermore, by setting the MS signal 109 to a high level, the memory selector 101-3
In order to select 01-1, address decoder 101-4
Make a note of the address information above! j given to 101-1.

Next, the execution control unit 100-7 lowers the ALE signal 104 at the trailing edge of the TI timing. Following this, the input gate of the address latch 101-5 is closed at the fall of the ALE signal 104 in the hash interface section 101-8i, and the address information on the MAD path 101-9 is latched into the address latch 101-5.

In the case of a data read cycle for reading data from the memory 101-1, the execution control unit 100-9 sets the AL) bus 102 to a 70-ting state in the second half of the T2 timing in preparation for the read cycle, and then sets the AL) bus 102 to a 70-ting state in the second half of the T2 timing period. Activate the RD signal 105. This results in
The bus interface unit 101-8 provides address information of the address latch 101-5 and memory selector 101-3.
Memory selection information and notes pointed to by! The data in JIOI-1 is output onto AD bus 02 via MAL bus 101-9.

Then, the execution control unit 100-7 executes the AD bar, '(102
The data on the AD bus 02 is read at a predetermined clock within the T3 timing when the data read above becomes valid.

During the data read cycle when reading data from the memory 101-1, the execution control unit 100-7 performs
By keeping the J signal 108 at low level and the MS signal 109 at high level, the bus interface section 10
1-8 selects the address latch 101-5 as the output source of address information to the memory 101-1.

Next, a case will be described in which data reading is performed on the memory IJIOI-2. The execution cloth 1j controller 100-7 of the microprocessor 100 raises the ALE signal 104 at timing T1 in order to write all address information @ of the access destination into the address latch 101-5 in the memory chip 101. At the rising edge 9 of the ALE signal, the bus interface section 101-8 opens the input gate of the address latch 101-5, and the address latch 101-5 receives the M signal.
Al) The contents of the bus are input.

Next, in order to avoid conflict with the previous bus cycle, the execution control unit 1007 selects the memory 101 to be accessed, which is output from the processing execution unit 100-6 to the address 1v1iloO-10, from the latter half of the T1 timing. -2 on the AI) bus 102, and outputs the address information in I/D signal 1
08 and MS signal to low level.

By setting the I/f) signal 108'e to low level,
The address latch 101 serves as an address output source for the address decoder 101-4 in the memory chip 101.
-5 is selected, and the address information on AD bus 02 is M
Since the address information on the AD bus 02 is output on the AD bus 101-9, the address decoder 101-4 receives the address information on the AD bus 101-9. It is output via address latch 101-5. Furthermore, by setting the MS signal 109 to low level, the memory selector 101-3
01-2, the address decoder 101-4
The above address information is given to memory 101-2.

Next, the execution control unit 100-7 lowers the ALE signal 104 at the trailing edge of the TI timing. In addition to this, bus interface section 101-8 id, ALE signal 10
4, the input gate of address latch 101-5 is closed, and the address information on MAD bus 101-9 is latched into address latch 101-5.

In the case of a data read cycle for reading data from the memory 101-2, the execution control unit 100-9 sets the Al) bus 102 in a floating state in preparation for the read cycle in the second half of the T2 timing, and then outputs the RD signal during the T33 timing. Activate 105. As a result, the bus interface section 101-8 receives the address information of the address latch 101-5 and the memory selector 101-8.
The data in the memory 101-2 indicated by the memory selection information No. 3 is output onto the ALI bus 102 via the MAD bus 101-9.

Then, the execution control unit 100-7 reads the data on the AI) bus 102 at a predetermined clock within the T3 timing when the data read on the AD bus 02 becomes valid.

During the data read cycle when reading data from the memo IJIOI-2, the execution control unit 100-7 controls the i/
By keeping the D signal 108 and the MS signal 109 at a low level, the bus interface section 101-8 selects the address latch 101-5 as the output light of the address information to the memo '1101-2.

(3) Data write cycle The data write cycle consists of TI, T2. It consists of three timings, T3. Further, data writing is performed only to memory 101-2.

The execution control unit 100-7 of the microprocessor 100
In order to write the address information of the access destination into the address latch 101-5 in the memory chip 101, the ALE signal 104 is raised at timing T1.

When the ALE signal rises, the bus interface unit 101-8 opens the input gate of the address latch 101-5, and the contents of the MAI) bus are input to the address latch 101-5.

Next, in order to avoid conflict with the previous bus cycle, the execution control unit 100-7 selects the memory 100 to be accessed, which is output from the processing execution unit 1oo-s to the address Iv11100-10, from the second half of the T1 timing. -2 on the ALI bus 102, and
08 and the MS signal 109 are set to low level. When the I/D signal 108 becomes low level, the memory chip 1
The address latch 101-5 is selected as the address output light for the address decoder 101-4 in the MAL) bus 10.
Address decoder 101-4 because it is output on 1-9.
, address information on the AD bus 02 is output via the MAD bus 1O1-9 and address latch 101-5. Furthermore, since the memory selector 101-3 selects the memory 101-2 by setting the MS signal 109 to a low level, the address information on the address decoder 101-4 is given to the memory 101-2.

Next, the execution control unit 100-7 lowers the ALE signal 104 at the trailing edge of the TI timing. As a result, the bus interface section 101-8 closes the input gate of the address latch 101-5 at the falling edge of the ALE signal 104, and latches the address information on the MAI) bus 101-9 into the address latch 101-5.

In the case of a data write cycle, the execution control unit 100-7 outputs write data to the AD bus 02 from the latter half of the T2 timing to
The data on AD bus 02 is output onto AD bus 101-9.

Next, the execution control unit 100-7 executes W1 between T33 timings.
4 signal 106 is activated. As a result, the bus interface section 101-8 allows the biAD bus 1
The data on 01-9 is written to the memory 101-2 pointed to by the address information of the address latch 101-5 and the memory selection information of the memory selector 101-5.

During the data write cycle, the execution control unit 100-7 keeps the I/I) signal 108 and the Ms signal 109 at low level, thereby causing the bus interface unit 101-
sh, the address latch 101-5 is selected as the output light of the address information to the memory 101-2.

(4) Branch processing cycle The branch processing cycle consists of TI, T2. Consists of 3 timings of T3. Further, the instruction code read in the branch processing cycle is stored in the memory IJIOI-1.

The execution control unit 100-7 of the microprocessor 100
The AL and E signals 104 are raised at the 'r1 timing.

Next, in order to avoid conflict with the previous bus cycle, the execution control unit 100-7 starts from the second half of the Tl timing to write the information in the memo IJIOI-1 output from the processing execution unit 100-6 to the address 1100-10. Branch destination address information 1, A
L) Output on the bus 102 and set the I/D signal 108 and MS signal 109 to high level. As a result, the bus interface unit 101-8 outputs the address information of the branch destination on the AD bus 02 to the MA Ll hash 101-9, and selects IPlol-6 as the address output source for the address decoder 101-4. At the same time, AL
Since both the E signal 104 and the I/1) signal 108 become the information level, the IPIO is transferred from the MAD bus 101-9.
Open the input gate to I-6. As a result, the branch destination address information on the MAL) bus 101-9 is changed to IPIOI-6.
A1) is input to the address decoder 101-4.
The branch destination address information on the bus 102 is biAD bus 101-9. It is output via IPIOl-6. Furthermore, since the memory selector 101-3 selects the memory 101-1', the address information on the address decoder 101-4 is given to the memory 101-1.

Next, the execution control unit 100-7 lowers the ALE signal 104 at the trailing edge of the Tl timing. Accordingly, the bus interface unit 101-6 closes the input gate of IPIOI-6 when the ALE signal 104 falls, and closes the input gate of the MA
Address information on D bus 101-9 is latched into IPIOI-6.

Next, the execution control unit 100-7 controls the T3 mapping period R.
Activate the D signal 105 4 (by which the bus interface unit 101-8 reads the instruction code of the branch destination in the memory 101-1 pointed to by the address information of IPIOI-6 and the memory selection information of the memory selector 101-3). The information is sent to the AD bus 0 via the MAL bus 101-9.
Output on 2.

The execution control unit 100-7 sends the instruction code on the AI bus 102 to the machine queue 100 at a predetermined clock within the T3 timing when the instruction code on the Af) bus 102 becomes valid.
At the same time, the IRL) signal 107, which was at a high level, falls at the latter half of the T3 timing and rises again at the trailing edge of the T3 timing.

As a result, at the falling edge of the IRD signal 107, the bus interface section 101-8 of the memory chip 101
The address value of If-'101-6 is output to the incrementer 101-7 and incremented, and then IRI
) At the rising edge 9 of the signal 107, the incremented address value is written back to IPIO1-6 to update the address information.

From then on, by continuing the T3 timing, the instruction code fetch cycle described in (1) is activated continuously,
Branch processing and instruction code fetch from the branch destination are executed continuously.

During the branch processing cycle and subsequent instruction code fetch cycle, the I/D signal 108 and the input iS signal 109 remain at a high level, so that the bus interface unit 101-8 outputs address information to the memory 101-1. IPIOI-6 is selected as the source.

Next, the overall operation of the microcomputer system shown in FIG. 1 will be described in terms of (1) operation at reset, (2) operation at normal instruction execution, and (3) operation at branch processing.

(1) Operation at reset The microprocessor 10
When the reset signal 103 of 0 becomes active, the execution control unit 100-7 initializes PCloo-1. For bus cycle control, the reset signal 103
The TI signal is output until the bus becomes inactive, and the bus cycle becomes idle. In addition, the instruction queue 100-
3 is flashed and becomes main, and the QRDY signals 100-12 are inactive.

When the reset signal 103 becomes inactive, the execution control unit 100-7 starts a branch processing cycle. At this time, the initial value of PCloo-1 as the branch destination address is
AL) is output to path 102. Execution control unit 100-7
After the branch processing cycle ends, the instruction code fetch cycle is continuously activated to read the entire instruction code from the memory 101-1 into the instruction queue 100-3.

(2) Operation during normal instruction execution When the Q)LL)Y signal 100-12 from the instruction queue 100-3 becomes active, the microprocessor 100 reads the instruction code from the head of the instruction queue 100-3, and reads the instruction code from the lR100. -Fetch to 4.

The value of pcxoo-1 is changed to the incrementer 100-1 by reading the instruction code from the instruction queue 100-3.
Incremented by 2. The instruction code fetched into the lR 100-4 is decoded by the instruction decoder 100-5, and is decoded by the control signal output from the instruction decoder 100-5.
The processing execution unit 100-6 executes command processing.

The processing execution unit 100-6 performs a read/write operation when a read operation of processing data with the memory 101-1 in the memory chip 101 or a read/write operation of processing data with the memory IJIOI-2 is required in executing an instruction. After completing the address calculation of the memory 101-1 or memory 101-2, the BRQ signal 100- is activated and the address information of the access destination is set to address? It is output to the IM 100-10 to request the execution control unit 100-7 to start a data read/write cycle.

The execution control unit 100-7 controls the currently executed bus cycle (
After completion (if any), the ACK signal 100-11 is activated, a data read/write cycle activation request is accepted from the processing execution unit 100-6, and the data read/write cycle is immediately activated.

(3) Operation during branch processing In the case of a branch instruction, the processing execution unit 100-6 calculates the branch destination address and determines whether to branch to the branch destination. At the same time as writing the branch end address, the BR signal 100-9 is activated, and the address information in the branch destination memory 101-1 is written as address &
100-10 to request the execution control 81007 to start a branch processing cycle.

The execution control unit 100-7 controls the currently executed bus cycle (
After completion (if any), the ACK signal 100-11 is activated, a branch processing cycle activation request is accepted from the processing execution unit 100-6, and the branch processing cycle is immediately activated.

Further, since the instruction key 100-3 is flashed and becomes a beam, the QRL)Y signal 100-12 becomes inactive.

After the branch processing cycle ends, the execution control unit 100-7 continuously activates the instruction code fetch cycle and stores the memo IJ.
Transfer the branch destination instruction code from IOI-1 to the instruction queue 100.
-Incorporate into 3.

[Example 2] A second embodiment of the present invention will be described with reference to FIG.

The difference between the second embodiment and the first embodiment is that the memory 601-1 in the memory chip 601 is a FROM. Therefore, VP to provide the electric wire for writing FROM
Since the P terminal 601-10 and a part of the AD102, which is the address/data multi-register bus, are used exclusively for data, the address terminal 601-11 is newly added to provide additional address information that is insufficient as a paoM pledge address. It is added to the memory chip 601. Memo! J6
Since 01-1 is FROM, the program can be rewritten.

〔Effect of the invention〕

As explained above, the present invention includes a microprocessor, a pointer pointing to the address of the instruction code fetch destination, an incrementer for incrementing the pointer, a ROM (first memory) for storing programs and read-only data, and a read/write R for storing dual-use data
A microcomputer consisting of a memory chip with AM (second memory) and first memo +)6 or memo for selecting either 6 or second memory -t=Nirefta on a single semiconductor substrate. The microprocessor directly controls the operation of the memory chip and performs tightly coupled operation, resulting in the following effects.

(1) Since a counter is provided for reading the memory storing the instruction code, the microprocessor does not need to activate a bus cycle for outputting the fetch destination address in the instruction code fetch cycle. This reduction in the number of bus cycles speeds up the instruction code fetch cycle, thereby reducing the frequency of bus neck occurrences and improving the instruction execution speed of the entire system.

(2) By increasing the speed of the instruction code fetch cycle and supplying the necessary and sufficient amount of instruction codes to the microprocessor, the microprocessor is equipped with an instruction queue, which increases the effect of preempting instruction codes, and further reduces the occurrence of pathnecks. It can be kept to a minimum.

(3) At the time of reset or branch processing, writing to the counter for reading the LOM (in which the instruction code is stored) and fetching the instruction code from the ROM pointed to by the written counter are performed continuously. This speeds up the execution time of the public corporation instruction at the time of branching.

(4) A pointer pointing to the program address where the instruction code is fetched, an incrementer that increments the pointer, an address latch that stores the data address, and a memory that stores the program and data are configured on a single semiconductor substrate as a memory chip. This makes it possible to connect the microprocessor and memory chip directly without adding hardware such as latches and drivers between the microprocessor and memory chip, making it possible to have a very compact system configuration and reliability is improved.

(5) The memory in the memory chip is ROM RAΔ1
4) It is determined whether an access to the ROM is an access to the RAM by a memory selector that operates according to a selection signal sent to the microprocessor color memory chip. This makes the program) LOM,
Read-only data such as initial values and various tables are stored in R(J
M, data for outputting/writing images such as variables to RAM
We have realized that the program and read-only data can be placed in the same ROM.
/RAM configuration is simplified.

In this way, the present invention improves bus memory access efficiency by speeding up the instruction code fetch cycle without increasing the negative phase on the hardware, minimizes the occurrence of path necks, and It is of great practical importance because it enhances the effect of prefetching instruction codes used in the line method, and further improves system reliability and economic efficiency.

[Brief explanation of the drawing]

FIG. 1 shows block V1 of Embodiment 1 of the present invention.
1, 3-2, 4 and 5 are the timing charts of FIG. 1, FIG. 6 is a block diagram of the second embodiment of the invention, and FIG. 7 is a block diagram of the conventional example. Figure 8, Figure 9-1,
Figures 9-2, 10, and 11 are the timing charts of Figure 8.
...PC, 100-2...Incrementer, 100-3...Instruction queue, 100-4.
Old...IRl 100-5...Instruction decoder, 100-6...Process execution unit, 1
00-7...Execution control unit, 100-8...
...BRQ signal, 100-9...BR double signal 1
00-10... Address ffl, 100-11
......λCK signal, 100-12-...QR
I) Y signal, 100-13 ---QFUL signal, 1
01... Memory chip, 101-1...
・Mask ROM memory, 101-2...R11
lMemo Ic101-3...Memory selector, 1
01-4・-・・・Address decoder, 101-5・
...Address Latte, 1o1-6...I
P, 101-7...Incrementer, 1o1-
8...Bus interface section, 101-9.
...MAL) bus, 102...AL) bus, 1o3...reset signal, 104...
・・ALE signal, 1o5・・・・Kori signal, 106
...WH, signal, 107...-IRD signal, 108...I/I) signal, 109...
...MS signal, 601...Memory chip, 60
1-1... PROM memo 1c 601-10.
......■Terminal, 601-11...Address terminal, 800...Microprocessor, 80
0-1...PC, 800-2...Incrementer, 800-3...Instruction queue, 80
0-4...IR, 800-5...Instruction decoder, 800-6...Process execution unit, 800-7...Execution control unit, 80 〇－
8...BRQ signal, 800-9...Address line, 800-10...ACK signal, 80
0-11...QRDY signal, 800-12...
...QFUL signal, 801...Address latch, 802...Program memory, 803...
...Data memo T), 804...AI)
Bus, 805...A bus, 806...
Reset signal, 807...ALE signal, 808
......kLi) Signal, 809...WR double signal fist 3 ~ l Kyo → Niji → Go L → Yu L 10- AD no desu to2 ryo 1Lλ young
Chee? Input Figure 3-2 Figure 4 Figure -Hμ-+ノL→'1←- Nest'? -f Begyu q-2 diagram

Claims (1)

[Claims] A microcomputer system including first and second storage means for storing various processing data and programs, and data processing means for performing data processing by executing instructions based on the program, the microcomputer system comprising: first and second storage means for storing various processing data and programs; a selection means for selecting either one of the storage means or the second storage means, and between the first storage means or the second storage means selected by the selection means and the data processing means; a transfer control means for controlling the transfer of the processing data and the transfer of the program from the first storage means or the second storage means selected by the selection means; and the selection means prior to execution of the instruction. an instruction storage means for storing an instruction code of the program read from the first storage means or the second storage means selected by the selection means; and the first storage means or the second storage means selected by the selection means. The transfer control means includes an instruction means for storing positional information of the storage contents of the storage means, and an update means for updating the contents of the instruction means, and the transfer control means transmits the selection information by the selection means and the information selected by the selection means. Following the sending of instruction information instructing a read destination and a write destination in data transfer performed between the first storage means or the second storage means and the data processing means, the selection means selects the data processing means. a first transfer means for transferring data to said first storage means or said second storage means; and following the sending of selection information by said selection means and sending of instruction information to said instruction means; a second transfer means for transferring the command specified by the instruction means from the first storage means or the second storage means selected by the selection means to the command storage means;
By sending selection information by the selection means and outputting an update control signal to the updating means to update the contents of the instruction means, the selection information selected by the selection means can be updated without sending out instruction information. a third transfer means that performs continuous transfer from the first storage means or the second storage means to the instruction storage means; the first transfer means, the second transfer means, and the third transfer means; A microcomputer system comprising transfer selection means for selecting a transfer in a predetermined priority order.