JPH03111950A - Microcomputer system - Google Patents

Abstract

PURPOSE:To save power consumption without losing rapid processing speed by controlling a storage means to a driven state only when address information is included in address space information. CONSTITUTION:Prior to addressing to the storage means 213, whether address information AB stored in address information storing means 215, 225 is included in address space information stored in an address space information storing means 211 or not is detected, and only when the address information AB is included in the address space information, the storage means 213 is controlled to the driven state. Consequently, power consumption in the unsed period of the storage device 213 can be suppressed and power consumption can be reduced without losing the high processing speed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a microcomputer system in which a data processing means sequentially reads and executes programs and processing data stored in a memory.

[Prior Art] In recent years, microprocessors have been able to significantly improve their instruction processing execution speeds due to architectural improvements, making it possible to perform high-speed instruction processing.

However, the read time for programs and data between a microprocessor and memory is relatively long compared to the microprocessor's execution time due to memory access speed limitations, and the overall time required for microprocessor instruction execution is This is a major cause of prolonging the In particular, when reading and inputting instruction codes stored in consecutive addresses like in a program, most of the processing time of the entire microprocessor is spent waiting for the instruction code from memory, which slows down the processing speed of the entire microcomputer system. ing.

FIG. 10 is a block diagram showing the configuration of a conventional microcomputer system.

A microprocessor 500 that controls data input/output processing and the entire microcomputer system, and a memory 600 that stores processing data and programs of this microprocessor 500 are connected to an address data bus (hereinafter referred to as
AD Babasu) 700. The microprocessor 500 includes a processing execution unit 5 that executes instructions.
01, and an execution control unit 502 that controls the overall operation of the microprocessor 500. The microprocessor 500 reads processing data and programs from the memory θOO using a read signal (hereinafter referred to as the RD double signal). Further, an address latch 601 is connected to the AD bus 700. The address latch 601 is
The multiplexed address information, instruction code, and input data provided from the microprocessor 500 via the AD bus 700 are demultiplexed, and only the address information is output as an address latch enable signal (hereinafter referred to as AL).
The address of the memory 600 is specified via an address bus (hereinafter referred to as ADRS bus) 802.

microprocessor 500 and AD bus 7 in successive inputs of programs located at successive addresses;
11 Regarding address information and data flow on 00
This will be explained with reference to the timing chart shown in the figure.

Generally, programs are stored in consecutive memory areas in sequence, and the microprocessor 500 reads and executes these programs via the AD bus 700 in accordance with the address order. As shown in FIG. 11, the program input is B1°B2. It consists of B3 basic states.

First, the microprocessor 500 is in the BI state.
At the same time as the LE signal is activated, read addresses from B to B2 are output onto the AD bus 700. The RD double signal is set to active level at a timing between the middle of the subsequent B2 state and the middle of the B3 state. As a result, the AD bus 7 is transferred from the memory 800 to the AD bus 7 in synchronization with the RD double signal.
Data is read on 00. microprocessor 5
00 is the AD bus 7 at a predetermined timing in the B3 state.
Import the data on 00. Through the above series of processing,
One data read cycle of program input is completed.

[Problems to be Solved by the Invention] However, in the conventional microcomputer system described above, the processing execution unit 501 outputs the address ADR8 to the execution control unit 502 in the B state, and then processes the address in the middle of the NB3 state. Until the data is received, the processing execution section 501 is simply waiting for the data to be input, and this idle time of the processing execution section 501 reduces the processing speed of the entire microcomputer. In particular, the time required to input a program is sufficiently long compared to the execution time of an instruction, and the microprocessor 500 frequently enters a data wait state during a data read cycle. As a result, there is a problem in that although the microprocessor has sufficient processing power, its processing speed has not been improved.

In addition, in the conventional microcomputer system described above, in order to shorten memory access time as much as possible,
It is necessary to keep the memory 600 in a standby state at all times. For this reason, even when a memory with a CMO8 configuration is used, for example, power is always consumed regardless of whether it is accessed or not, and there is a problem in that it is difficult to reduce the power consumption of the entire microcomputer system.

The present invention has been made in view of such problems, and includes:
An object of the present invention is to provide a microcomputer system capable of high-speed processing and low power consumption.

[Means for Solving the Problems] A microcomputer system according to the present invention includes a storage means for storing information consisting of instruction codes and data, and a data processing unit for executing predetermined processing according to information read from the storage means. means, address information storage means for storing address information specified by the data processing means, address space information storage means for holding address space information indicating an address space to which the storage means is allocated, and the address information storage means detecting whether or not the address information stored in the address space information stored in the address space information held in the address space information storage means is included in the address space information held in the address space information storage means before specifying an address to the storage means, and if the address information is included in the address space information; a control means for controlling the storage means to an operating state only when the storage means is in operation; an updating means for continuously updating the address information stored in the address information storage means; and an updating means for continuously updating the address information by the updating means. It is characterized by comprising a transfer means for continuously transferring information read out continuously from the storage means to the data processing means.

Furthermore, the microcomputer system according to the present invention includes:
In the above system, the address information storage means includes a first address information storage means for storing an instruction code read address, and a second address information storage means for storing a data read address, and each of these addresses first and second updating means that separately and continuously update the address information stored in the information storage means;
first and second transfer means that continuously transfer information continuously read from the storage means to the data processing means in accordance with continuous updates by these update means;
The present invention is characterized in that it has the update means and the transfer means.

[Function] According to the present invention, the address information stored in the address information storage means is continuously updated by the updating means, and the address information of the storage means is specified by the continuously updated address information. Since data is continuously read from the storage means, high-speed memory access with short access time is possible, and overall processing time can be shortened. Moreover, according to the present invention, it is detected whether or not the address information stored in the address information storage means is included in the address space information held by the address space information storage means, prior to specifying an address to the storage means, and Since the storage device is controlled to be activated only when address information is included in the address space information, power consumption can be suppressed during periods when the storage device is not used, and processing speed can be increased significantly. It is possible to achieve lower power consumption.

Further, according to the present invention, by providing a system for continuous reading of instruction codes and a system for continuous reading of data separately and independently, it is possible to prevent the data reading operation from being interrupted during the instruction code reading operation. Even if you execute it, the reading operation of the instruction code will be interrupted.
The instruction code reading operation can be restarted immediately after the data reading operation is completed, and the processing speed can be further improved.

[Example] Hereinafter, an example of the present invention will be described based on the accompanying drawings.

FIG. 1 is a block diagram of a microcomputer system according to a first embodiment of the present invention.

This microcomputer system includes a microprocessor 100 that performs data input/output processing, arithmetic processing, and overall control of the microcomputer, and an LSI memory unit that stores programs executed by the microprocessor 100 and data necessary for the arithmetic operations. It consists of 200. 100 of these microprocessors
and the memory unit 200 are connected by an address data bus (hereinafter referred to as AD bus) 300.

A reset signal RESET is supplied to the microprocessor 100 and the memory unit 200, and the internal hardware is initialized by this signal.

The microprocessor 100 includes a processing execution unit 101 that executes instructions, a data storage unit that stores instruction codes and processing data read from the memory unit 200 in the order in which they are read, and sequentially outputs them in response to requests from the processing execution unit 101. It consists of a queue 102 and an execution control unit 103 that controls the overall operation of the microprocessor 100. Along with the execution of an instruction, the processing execution unit 101 sends a bus request signal BRQ requesting the execution control unit 103 to start a memory read cycle with a memory 213 in the memory unit 200, which will be described later, and access to the memory 213. The previous address information ADR8 is output. The execution control unit 103 receives the bus request signal BRQ and outputs a response signal ACK to the processing execution unit 101.

Additionally, an address latch enable signal (hereinafter referred to as
ALE signal), read data signal (hereinafter referred to as RD double signal), and control signals 5TBF signal and 5T.
BD signal is supplied and tail. The ALE signal transmits address information on the AD bus 00 to FPM203 or D
This is a signal for causing PM206 to latch. The RD double signal, the row active signal for reading data from the memory 213, and the 5TBF signal are used to determine the timing for latching the address information on the AD bus 00 into the FPM 203 and for reading from the memory 213 in a continuous instruction code read cycle, which will be described later. The 5TBD signal is a control signal that provides timing, and the 5TBD signal is a control signal that provides timing for causing the DPM 208 to latch address information on the AD bus 00 and read timing from the memory 213 in a continuous data read cycle, which will be described later.

On the other hand, the memory unit 200 is configured as follows.

That is, a bus interface unit 201 is provided at the interface with the microprocessor 100. This bus interface section 201 receives the various signals described above from the microprocessor 100, and receives the control signal C.
Outputs s + C2r C3+C4, C5, co, and C7.

FPM203. The FPS 204 is a master-slave configuration pointer that connects the AD bus 00 to the bus interface section 201 to the internal bus of the memory unit 200 (hereinafter referred to as A).
DR bus) 218 and multiplexer (hereinafter referred to as M
(referred to as PX) 202 is latched.

These FPM203. The FPS 204 is controlled by the C2 signal output during the instruction code read cycle. In addition, another mask slave configuration pointer DPM20
7. The DPS 208 also latches address information in the same way as described above, and is controlled by the C3 signal output during the data read cycle. The contents of FPS 204 are incremented by incrementer 205 and MP
It is given to one input of X202. MPX2-0
2 selects the output of the incrementer 205 in synchronization with a C1 signal output during continuous instruction code and continuous data read cycles, which will be described later. Further, the contents of the DPS 208 are incremented by an incrementer 209 and given to one input of the MPX 208. MPX
An ADR bus 218 is connected to the other input of 208 .

The MPX206 increments the incrementer 2 in synchronization with the C1 signal.
Select the output of 09. FPS204 and DPS208
The output of is given to MPX212. MPX21
2 is C output during consecutive instruction code read cycles.
Based on the 6 signals, the output of the FPS 204 or the DPS 208 is selected, and the address information AB is sent via the AB bus 20.
is supplied to the memory 213.

Furthermore, the outputs of bits 15 and 14 of the FPM 203 and DPM 207 are also given to the MPX 210. The MPX 210 selects bits 15 and 14 of the address information from the FPM 203 or DPM 207 using the C8 signal, and supplies the selected 2-bit address bit data ABD to the location control unit 211 via the ABD bus 219, which will be described later. do.

The memory 213 is a read-only memory (ROM) that stores programs and data for the microprocessor 100.
It is. This memory 213 contains addressing bits 2
28 is added. This addressing bit 228
stores only bits 14 and 15 of the mapping address, which specify the address space to which memory 213 is allocated. Further, output latches 215 and 225 are connected to the memory 213 via a read buffer 214. The output latch 215 has an instruction code stored in the memory 213.
When the instruction code is read continuously from
It is latched sequentially in synchronization with the two signals. Also, output latch 2
25 sequentially latches the data in synchronization with the 03 signal when the data is continuously read from the memory 213. Output buffers 217, 226, 216 output the outputs of output latches 215, 225 and memory 213 to C4, respectively.
, Ca, and C5 signals to the ADR bus 218.

The address bit register 229 sets bit 14 to A B r and bit 15 to A among the information read from the address designation bit 228 in synchronization with the 07 signal at the time of initialization.
Store each in B2.

Further, the relocation control unit 211 outputs an SLROM signal specifying the memory space of the memory 213 and an ENSAMP signal controlling the operation of the successive buffer 214, and is configured as shown in FIG. 2, for example.

That is, the comparator 400 compares the address bit data ABD with the contents of the address pit register 229, and
When bits 14 and 15 of the address information in PM203 or DPM20e match AB, AB2 of the address pit register 229, that is, the memory 213 with the specified address in FPM203 or DPM20θ
When the read buffer 214 is included in the address space, its output is activated and the ENSAMP signal is set to "1" via the OR circuit 402 to enable the read buffer 214 to operate.

Further, the output of the comparator 400 is given to a latch 401. This latch timing is determined by the inverters 221, 2
AND circuit 406 which receives the output of C.27 and the C6 signal as input.
, 407, an OR circuit 408, and an inverter 409. During the continuous instruction code read cycle, the C8 signal becomes "1", so when the output of the inverter 221 becomes "1", the latch 401
The output SLROM signal of becomes "1", the memory 213 is selected, and access becomes possible.

During other read cycles, the C8 signal is "0", so when the output of the inverter 227 is "1", it is input to the latch 401. Generally, the read buffer 214 is the memory 213
In order to read data at high speed, even in the 0MO8 configuration, power is constantly consumed when the ENSAMP signal is in the operating state of "1", regardless of whether there is a change in data. When changing from "0" to "1" and changing from a stopped state to an operating state, a predetermined time (tn, r) is required until the steady operating state is reached. Further, only when the SLROM signal is "1", the bus interface unit 201 outputs the data in the memory 213 to the AD bus 00.

Next, the operation of the microcomputer system configured as described above will be explained.

This system has three read cycle modes: continuous instruction code read cycle, continuous data read cycle, and single data read cycle.

When the ALE signal is "1" and the 5TBD signal is "O", the continuous instruction code read cycle mode is set. In this mode, 5TBF in the following timing
Data in the memory 213 changes to A in synchronization with the rise of the signal.
The data is read out onto the D bus 00.

When the ALE signal is “1”, the 5TBD signal is “1”, 5
When the TBF signal is "O", continuous data read cycle mode is set. In this mode, data in the memory 213 is read onto the AD bus 00 in synchronization with the rise of the 5TBD signal at the subsequent timing.

When the ALE signal is “1”, the 5TBD signal is “1”, 5
When the TBF signal is "1", a one-time data read cycle mode is set. In this mode, data in the memory 213 is read onto the AD bar 300 in synchronization with the RD double signal.

Next, the operation during continuous instruction code read cycles will be described with reference to the timing chart of FIG.

The continuous instruction code read cycle consists of four basic states Bll B21 B51 B4 for address setting;
State B5+ BG that reads instruction codes continuously
+ B7. The execution control unit 103 outputs various control signals to the memory 213 in each of these states, thereby controlling the memory 213 as the instructions are executed.
control the data read cycle. When continuing to read continuous instruction codes, the B8 state is repeated. Note that the addresses N, N+1 . N+
2, N+3. N+5 is all addressing bits 228
is within the address range specified by .

First, the microprocessor 100 is in AL state in B1 state.
The E signal is set to "1", the 5TBF signal is set to "0", and the 5TBD signal is set to "O", and the address N is output onto the AD bus 00. Bus interface section 201 of memory unit 200
The C1 signal is “1”, the C2 signal is “1”, and the C6 signal is “1”.
” and set address N on AD bus 00 to ADH bus 2.
Output on 18. As a result, the FPM 203 has M
Since address N is written via PX202, A
Bits 14 and 15 of address N are output onto BD bus 219. Bits 14 and 15 of address N are ABt of address bit register 229.
, AB2, the ENSAMP signal becomes “1”.
”, and the read buffer 214 becomes operational.

Next, in state 82, microprocessor 100:
The ALE signal is set to "O" and the AD bus 00 is set to a state in which no data is output (hereinafter referred to as a high impedance state). Then, the bus interface unit 201 outputs the cr multiplied signal as “0”, the C2 signal as “0”, and the CG signal as “0”.
Since the double signal is set to "1", the address N stored in the FPM 203 is transferred to the FPS 204, and the address N stored in the FPM 203 is transferred to the
The signal is output onto the AB bus 20 via the AB bus 20. Next, S
The LROM signal becomes "1", and the data at the address in the memory 213 corresponding to the address N is read out as an instruction code and written into the output latch 215. Output latch 21
5 has a mask slave configuration, and inverter 2
When the output of 21 is "0", the previously written content is output. In the middle of the B2 state, the microprocessor 100 sets the RD double signal to "0". In response to this, the bus interface section 201 sets the C2 signal to "1",
It also enables the contents of the ADR bus 218 to be output onto the A and D buses 300. At this time, the C6 signal remains "1". When the C2 signal becomes l(I I+, the address N+1 incremented by the incrementer 205 becomes M
It is written to the FPM 203 via the PX 202. At this time, since the address N+1 is also within the address range specified by the address designation bit 228, the ENSAMP signal remains at "1".

Next, in the middle of the B3 state, the microprocessor 10 sets the 5TBF signal to "+1", and the bus interface unit 201 sets the C2 signal to "O".
”, the address N+1 is output to the AB bus 20, and the address of the memory 213 is accessed for the address N+1. At the same time, the 04 signal becomes “1”, so the address N, which is the output of the output latch 215, is The data (N) that is the content of the corresponding memory 213 address is A
It is output onto the DH bus 218 and the bus interface section 2
It is output to AD bus 00 via 01.

Subsequently, at a predetermined timing in the first half of the B4 state, the microprocessor 100 inputs data (N) and writes the data (N) (ADI) to the data queue 102 via the execution control unit 103. The processing execution unit 101 decodes the data (N) (AD2) as an instruction code and executes the corresponding arithmetic processing. In this B4 state, the microprocessor 100 sets the 5TBF signal to "O", so the bus interface unit 201 sets the C2 signal to "O".
1”. When the C2 signal becomes “1”, the address N+
2 is written to FPM203. In the middle of the B4 state, the microprocessor 100 outputs the RD double signal “1”.
, sets the 5TBF signal to "1".

Then, the bus interface section 201 puts the AD bus 00 in a high impedance state and also sets the C2 signal to "O". As a result, data (N+1), which is the content of the output latch 215, is output to the ADR bus 218.

Next, in the middle of the Ba state, the microprocessor 10
0 makes the RD multiplied signal "0". As a result, the bus interface section 201 outputs the data (N+1) on the ADR bus 218 onto the AD bus 00.

In the B8 state, the microprocessor 100
Set the BF signal to “0”. Also, as in the B4 state, data (N+1) on AD bus 00 is transferred to data queue 1.
Write to 02. Similarly, when the 5TBF signal changes from "0" to "1", the data stored in consecutive addresses of the memory 213 is placed on the AD bus 00, and the microprocessor 100 inputs the data. By repeating this, the instruction code is continuously read.

Furthermore, when the 5TBF signal changes from "1" to "0", the contents of the ABD bus 219 are
1 determines whether the address is within the specified address range, and if it is within the specified address range,
ENSAMP signal and SLROM signal are "1" and "1" respectively
However, if the address is outside the specified address range, comparator 4
00, the ENSAMP signal and the SLROM signal become "0" and "0", respectively, and the successive buffer 214 stops operating to suppress power consumption.Microprocessor 1
While 00 continues to generate the B8 state, the continuous instruction code read cycle continues, and finally the B7 state is generated to end the continuous instruction code read cycle. In the B7 state, the microprocessor 100 performs the same operations as in the B4 state.

In the above continuous instruction code read cycle, the ENSAMP signal becomes "1" in the B+ state and the read buffer 2
After tBur time after 14 becomes operational, SLR
Since the OM signal is set to "1" to control the access to the memory 213, the access is started after the successive buffer 214 is in a completely steady operating state. Therefore, normal data reading becomes possible.

Next, in this continuous instruction code read cycle, F
The operation when the address information stored in PM 203 is outside the address range specified by address designation bit 228 will be described with reference to FIG.

In FIG. 4, addresses L, L+1. L+2 is outside the address range specified by addressing bits 228, address L+3 . Assume that L+4 is within the address range.

In this case, Bt t 82 +B3. B4. The ENSAMP signal remains “0” until the B5 state, but the NB
When the ABD bus 219 becomes L+3 in the 6B6 state, the ENSAMP signal becomes "1", and the SLROM signal also becomes "1" from the middle of the B8 state, and the memory 213
access is possible. Also, the SLROM signal is “1”.
”, so data (L + 3) is AD bus 0
Output on 0. In this case as well, ENSAMP
The configuration is such that jBuf time can be taken from when the signal becomes "1" until the SLROM signal becomes "1".

As described above, when the memory 213 is outside the specified address range, the main operation of the memory unit 200 is the memory 213.
No. 13 data read operation is performed, and power consumption can be suppressed.

Next, the operation of a one-time data read cycle will be explained with reference to FIG.

A one-off data read cycle consists of three states Bl.
, B2-B3. In state B, the microprocessor 100 sets the ALE signal to “1”.
Set the 5TBF signal to "1" and the 5TBD signal to "1".

Also, address K is placed on AD bus 00. Then, the bus interface unit 201 transfers the C signal to 1'',
Set the C3 signal to "1" and the C6 signal to "0". As a result, since the C8 signal is “0” in the address, the DP
The data is written to M207 and input to the relocation control unit 211 via the MPX 210. When address K is within the address range specified by addressing bits 228, the ENSAMP signal goes to 1''.

Next, in the B2 state, the microprocessor 100
In order to set the LE signal to "O", the C3 signal becomes "O", address K is written to DP8208, and MPX21
The memory 213 is accessed via 2. At the same time, the SLROM signal also becomes 1.The C5 signal also becomes 1, and the data (K) at the address of the memory 213 corresponding to address K is transferred from the output buffer 218 to the ADR bus 218.
is output above. Since the microprocessor 100 sets the RD double signal to "0" in the middle of the B2 state, the bus interface unit 201 outputs the data (K) to the AD bus 00.
Read above. The microprocessor 100 takes in data (K) at a predetermined timing in the B3 state, and the processing execution unit 101 uses it as data for arithmetic processing.

Next, a continuous data read cycle will be explained with reference to FIG.

In FIG. 6, continuous data read cycles are Bt, B
2. B3. It is composed of the B4 state, and during an operation in which data is read continuously, the B3 state is repeatedly executed. In the B+ state of consecutive data read cycles, the microprocessor 100 outputs the ALE signal as “
1", the 5TBF signal is set to "0", and the 5TBD signal is set to "1".

It also outputs the address M on the AD bus 00.

Then, the bus interface section 201 sets the C3 signal to "1" and writes the address M to the DPM 207.

At this time, since the C8 signal is “O”, the MPX212
, 210 select the outputs of the DPS 208 and DPM 207, respectively. After that, like the instruction code read cycle, 5
The contents of the DPS 208 are incremented in synchronization with the rising edge of the TBF signal, and the data at the corresponding memory 213 address is read out. Address M, M+1. Within the address range where M+2 is specified by addressing bits 228,
If address M+3 is outside the address range specified by addressing bits 228, comparator 400 outputs "0" in the middle of the B3 state where ABD bus 219 outputs bits 14 and 15 of address M+3; Since the output of latch 401 is “1”, ENSA
The MP signal remains "1".

In the continuation<83 state, the microprocessor 100
When the bus interface section 201 sets the C3 signal to "0", the latch 401
“0” is written to the ENSAMP signal and SLR
Both OM signals become "0", and the data read operation from the memory 213 is performed by the memory 213 corresponding to address M+2.
It ends with the data at address.

Next, the operation of address bit register 229 will be explained based on FIG.

First, during initialization, the C7 signal becomes "1" in synchronization with the falling edge of the reset signal, and the address designation bit 228 is selected. At this time, the C5 signal from the bus interface unit 201 becomes "1". Therefore, memory 21
Bits 0 and 1 of the addressing bits 228 corresponding to bits 14 and 15 of the mapping address, which specify the address space in which the 3 is located, are output to the ADR bus 218 via the output buffer 216.

Then, bit 0 and bit 1 of the output address designation bit 228 are the ABI of the address pit register 229.
, AB2, respectively.

According to this system described above, high-speed memory access can be achieved by continuous instruction code read operations and continuous data read operations, and since the memory space to be accessed is determined prior to memory access, the access By putting unnecessary memory into a hibernation state, it is possible to reduce power consumption.

Further, according to this system, when reading an instruction code, the FPM 203, FPS 204, and output latch 215
is used, and when reading data, DPM207, DP
Since S208 and the output latch 225 are used, even if a data read operation is interrupted and executed during an instruction code read operation, the instruction code read operation is simply interrupted and the data read operation continues after the data read operation is completed. The instruction code reading operation can be resumed.

FIG. 8 is a block diagram showing the configuration of a microcomputer system according to a second embodiment of the present invention. In FIG. 8, the same parts as those in FIG. 1 are given the same reference numerals, and explanations of overlapping parts will be omitted.

In the microcomputer system according to this embodiment,
In addition to the memory 213 in the microcomputer system of the first embodiment shown in FIG. 1, a memory 222 having a RAM configuration in which data can be randomly written is provided. Moreover, the microprocessor 100
A write signal (
(hereinafter referred to as the WR multiplied signal) is supplied to the memory unit 200.

During a data write cycle, C8 is synchronized with the WR double signal.
The signal becomes “1” and the write data on the AD bus 00 is transferred to the ADR bus 21 via the bus interface section 201.
The write data on the ADR bus 218 is written to the memory 222 via the write control unit 224. Furthermore, the upper two bits of the address designation bits 228 are RA which designates the address space in which the memory 222 is located.
Bits 15 and 14 of the M mapping address are specified, and the lower two bits are bit 1 of the ROM mapping address, which specifies the address space where the memory 213 is located.
5 and bit 14.

The address pit registers 229 are AB, AB2 . A
This is a 4-bit register consisting of B, , AB4. AB, AB2 of this register 229 contain C7 at initialization.
bit 14 of the ROM mapping address in synchronization with the signal.
and bit 15, ie, bit O and bit 1 of addressing bits 228, are stored, and AB3. AB4 stores bits 14 and 15 of the RAM mapping address, ie, bits 2 and 3 of the addressing bits 228.

Further, the relocation control unit 211 generates an SLRAM signal for selecting the memory 222. Details of this relocation control section 211 are shown in FIG. Note that in FIG. 9, the same parts as in FIG. 2 are given the same reference numerals, and explanations of overlapping parts are omitted.

Mapping address range of memory 213 and memory 22
A B + of the address pit register 229 storing the mapping address range of 2.

AB2 is connected to the comparator 400, and AB 3 , AB
4 are respectively input to the comparator 403. Comparator 40
0 and the output of comparator 403 are input to latch 401 and latch 404, respectively. Latch 401 and latch 40
The outputs of 4 are SLROM signals which are selection signals for the memories 213 and 222, respectively. In addition, a comparator 400,
The output of 403 and the outputs of latches 401 and 404 are input to OR circuits 402 and 405, respectively, and ENROM and EN
It is output as RAM. The write signals for latches 401 and 404 are similar to the circuit of FIG.

The operation of the microcomputer system according to this embodiment is basically the same as that of the microcomputer shown in FIG. 1, and can read programs or data from memory at high speed. However, in this embodiment, under the control of the relocation control unit 211, two types of memories 213,
222 can be selectively accessed. Furthermore, ENROM and E, which are outputs of the relocation control unit 211,
By controlling the NRAM, SLROM, and SLRAM signals, when the address that accesses the memories 213 and 222 is outside the mapping address range specified by the location control unit 211, the memories 213 and 222 are stopped to reduce power consumption. can be achieved.

[Effects of the Invention] As explained above, according to the present invention, the address information stored in the address information storage means is continuously updated by the updating means, and the continuously updated address information is used to update the address information stored in the address information storage means. Since the address is specified,
Data is read out continuously from the storage means, enabling high-speed memory access with short access time. Therefore, it is possible to significantly shorten the overall processing time.

Moreover, according to the present invention, prior to specifying an address to the storage means, it is detected whether or not the address information stored in the address information storage means is included in the address space information held by the address space information storage means, Since the storage means is controlled to be in an active state only when the address information is included in the address space information, power consumption during periods when the storage device is not used can be suppressed, and the processing speed can be significantly reduced without impairing the speedup. This has the effect of reducing power consumption.

Furthermore, in the present invention, by providing a system for continuous reading of instruction codes and a system for continuous reading of data separately and independently, it is possible to interrupt the data reading operation during the instruction code reading operation. Even if the instruction code is executed, the instruction code read operation is simply interrupted, and the instruction code read operation can be restarted immediately after the data read operation is completed, thereby further improving the processing speed.

[Brief explanation of drawings]

1 to 7 are diagrams for explaining a microcomputer system according to a first embodiment of the present invention. FIG. 1 is a block diagram of the system, and FIG. 2 shows details of the location control section. Block diagram, Figures 3 and 4 are operational waveform diagrams during continuous instruction code read cycles, Figure 5 is operational waveform diagrams during single data read cycles, and Figure 6 is operational waveforms during continuous data read cycles. 7 is an operational waveform diagram of the address pit register, FIG. 8 is a block diagram of the microcomputer system according to the second embodiment of the present invention, and FIG. 9 is a block diagram showing details of the relocation control section in the system. 10 is a block diagram of a conventional microcomputer system, and FIG. 11 is an operating waveform diagram of the same system. 100.500; microprocessor, 101°501
;Processing execution unit, 102;Data queue 103.502
; Execution control unit, 200, 250; Memory unit, 20
1; bus interface section, 202, 206, 210.
212; multiplexer, 203, 204, 206.2
07; Pointer, 213.222,600; Memory, 2
19; Relocation control unit, 229; Address pit register, 300, 700; Address data bus, 60
1; Address latch

Claims (2)

[Claims] (1) Storage means for storing information consisting of instruction codes and data, data processing means for executing predetermined processing according to the information read from this storage means, and storing address information specified by this data processing means. an address space information storage means for holding address space information indicating an address space to which the storage means is allocated, and address information stored in the address information storage means is held in the address space information storage means. control means that detects whether or not the address information is included in the address space information that has been specified before specifying an address to the storage means, and controls the storage means to be in an operating state only when the address information is included in the address space information; updating means for continuously updating the address information stored in the address information storage means; and updating means for continuously updating the address information stored in the address information storage means; 1. A microcomputer system comprising: a transfer means for continuously transferring data to a processing means. (2) Storage means for storing information consisting of instruction codes and data, data processing means for executing predetermined processing according to the information read from the storage means, and reading of the instruction code specified by the data processing means a first address information storage means for storing address information; a second address information storage means for storing read address information of data specified by the data processing means;
address space information storage means for holding address space information indicating an address space to which the storage means is allocated;
detecting whether or not the address information stored in the first or second address information storage means is included in the address space information held in the address space information storage means prior to specifying an address to the storage means; control means for controlling the storage means to be in an active state only when the address information is included in address space information; and control means for continuously updating the address information stored in the first and second address information storage means, respectively. first and second updating means, and the information continuously read from the storage means as the address information is continuously updated by the first or second updating means is transmitted to the data processing means, respectively; A microcomputer system comprising first and second transfer means for transferring information.