JP2962431B2 - Programmable controller - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention]

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a programmable controller widely used for control of industrial systems such as steel, papermaking plants, public water systems such as water and sewage systems, and the automobile industry, and more particularly, to shorten the scan execution time. Therefore, the present invention relates to a programmable controller provided with an I / O batch input / output module.

[0002]

2. Description of the Related Art Programmable controllers (hereinafter referred to as P
C) uses a number of I / Os. Especially large PC
, The number of input / output points to be controlled increases,
The number of O also increases. These I / Os cannot be accommodated in one I / O unit and are distributed and implemented in a plurality of units. Each unit is connected to an I / O bus from a CPU module, and connected to a local I / O bus in each unit via a buffer module or the like.
/ O is connected. Each I / O is given a unique I / O address, and the CPU module accesses each I / O using this I / O address. Now, when scanning the control program, the PC must read data from all input modules for each scan and output the operation results of the control program to all output modules. This is called batch input / output. The time required for batch input / output becomes longer as the number of I / Os increases, and there is a disadvantage that the scan time of the PC becomes longer.

FIG. 2 shows a hardware configuration of a conventional PC. In FIG. 2, reference numeral 7 denotes an I / O bus buffer module. Conventionally, the CPU 2 uses the bus buffer 7
, I / Os 5 are read or written one by one according to the input / output type. Therefore, I / O
As the number of devices increased, the input / output time also increased.

[0004]

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and a module for collective input / output is provided in an I / O unit of a PC. The batch input / output of I / O in a plurality of units is performed in parallel by sharing the batch input / output of / O, so that the batch input / output time of the entire PC is reduced, and the scan execution time is reduced. It is intended to be. [Configuration of the Invention]

[0005]

According to the present invention, there are provided a plurality of input / output units having a plurality of input / output modules connected by an I / O bus, and the input / output units connected to the input / output units via a CPU bus.
In a programmable controller having a CPU module for inputting / outputting data to / from an input / output module of an input / output unit, the input / output unit is configured to input / output data to / from the input / output module. A microprocessor for performing the output, a dual port memory accessible from both the CPU module and the microprocessor, and a microprocessor.
Connect the address and data bus of the processor to the I / O bus.
A first buffer circuit and an address of the CPU module.
And a second buffer for connecting the data bus to the I / O bus.
Circuit and microprocessor or CPU module.
To arbitrate the bus right of the I / O bus,
CPU module directly to input / output module via
A module for batch input / output consisting of a bus right control circuit for accessing the module is provided. When the CPU module inputs / outputs data to / from the input / output module of the input / output unit, the data is stored in the dual port memory. - micro allowed to bulk input and output data
Dual port memory and I / O module for processor
The gist is to execute data input / output between them. This
In such a configuration, each of a plurality of input / output units
I / O batch input / output is executed to the batch input / output module.
By doing so, batch input / output at each I / O unit is
Can be performed on columns. Also, the CPU module
When it is desired to directly access the I / O, the bus right control circuit
Arbitration of I / O bus right with microprocessor
To give a bus right to the CPU module, and
Direct access through the web circuit.

[0006] Also, CPU module - by receiving Le simultaneously, - CPU module bulk output start command from Le - a plurality of collective input-output modules connected to bus Le
The timing of batch input / output in each I / O unit is synchronized, and the CPU module performs input / output for each I / O unit.
Time difference between input and output in all I / O compared to
Let it be less.

[0007]

FIG. 1 shows an embodiment of a main part of the present invention.
In FIG. 1, 1 is a batch input / output module, 1-1 is a microprocessor, 1-2 is a bus right control circuit, 1-3 is a bus buffer for μP, 1-4 is a bus buffer for CPU of PC, and 1-5. Is a dual port memory. 2 is PC
CPU, 3 is a CPU bus, 4 is an I / O bus, 5 is an input / output module, and 6 is an I / O unit.

In this embodiment, the CPU 2 first writes data to be output to the dual port memory 1-5 of each module 1 for batch input / output. Since this writing is performed using the memory address, it can be executed at high speed. Further, the bus right control circuit 1-2 includes an address decoder, and according to the address output from the CPU 2,
Writing is performed in a distributed manner to / O units.

Next, the CPU 2 outputs a start command to the all batch input / output module 1. This start-up output uses a common address for all the batch input / output modules 1. When the bus right control circuit 1-2 decodes this command, it outputs an interrupt signal to the μP 1-1.
When this interrupt signal is input, the μP 1-1 starts batch input / output. The μP 1-1 accesses the I / O 5 via the local I / O bus 4. At this time, the bus right control circuit 1-2 arbitrates the bus right of the I / O bus 4 and
-1 is given a bus right. Then, the data written to the dual port memory 1-5 is output to the output module, and the data read from the input module is written to the dual port memory 1-5. When the access of all the modules is completed, the completion flag is set in the status register in the bus right control circuit, and the reading from the CPU 2 is waited. The CPU 2 monitors the status of each batch input / output module 1 and reads input data from the dual port memory 1-5 when the completion flag is set. In this way, one batch input / output is completed. In general, I / O access takes more time than memory access. Therefore, even if batch input / output is performed via memory, I / O access is performed in parallel by a plurality of I / O units.
By performing input / output of / O, the entire batch input / output time can be sufficiently shortened.

When the CPU 2 wants to directly access the I / O 5, it accesses using the I / O address. I
When the / O address is input, the bus right control circuit 1-2 sets the μP
1-1 arbitrates the bus right of the I / O bus 4 and
The bus right is given to PU2. At this time, the bus buffer 1-4
Is enabled, and the CPU can directly access the I / O5.

In the above description, the configuration is such that the collective input / output module is independent as a module. However, it is also possible to adopt a configuration in which the circuit of this module is included in the motherboard of the I / O unit. Needless to say, there is.

[0012]

As described above, according to the programmable controller of the present invention, batch input / output of I / O of a plurality of input / output units can be executed in parallel. Time can be reduced. Also, C
If you want to access the I / O directly to the PU module,
The bus right control circuit transfers the I / O to the CPU module.
The bus right of the O bus is given, and the
CPU module
Can directly input / output to I / O.

[Brief description of the drawings]

FIG. 1 is an embodiment diagram showing a main part configuration of a programmable controller according to the present invention.

FIG. 2 is a block diagram showing a main part configuration of a conventional PC.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Batch input / output module 1-1 ... Microprocessor 1-2 ... Bus right control circuit 1-3 ... Microprocessor bus buffer 1-4 ... PC-CPU bus buffer 1-5 ... Dual ball memory 2. PC -CPU 3 CPU bus 4 I / O bus 5 I / O 6 I / O unit 7 Bus buffer module

Claims (2)

(57) [Claims] A plurality of input / output modules connected to each other via an I / O bus ;
In a programmable controller having a CPU module connected via a CPU bus for inputting / outputting data to / from the input / output module of the input / output unit, the input / output unit includes Data for output module
Microprocessor for executing input / output of data, and CPU
A dual port memory accessible from both the module and the microprocessor ; and the microprocessor.
Address and data bus connected to the I / O bus.
Buffer circuit and the address and data of the CPU module.
A second buffer circuit for connecting a bus to the I / O bus
And the microprocessor or the CPU module.
And arbitrates for the bus right of the I / O bus.
The CPU module is connected to the input / output module via a circuit.
A batch I / O module comprising a bus right control circuit for directly accessing the I / O module, wherein the CPU module is an I / O module of the I / O unit.
When inputting / outputting data from / to the microprocessor, the data is collectively input / output to / from the dual port memory and the microprocessor is used.
Data between the dual port memory and the I / O module.
A programmable controller characterized by executing input / output of data . Wherein said CPU module - each batch input-output module of said plurality of input and output units by the activation command from Le - simultaneously de Le - this you so that initiates the input and output of data <br / The programmable controller according to claim 1, wherein