JPS59229662A - Common memory control circuit - Google Patents

Abstract

PURPOSE:To avoid software competition by a hardware constitution by making processors correspond to respective holding circuits and setting up these holding circuits to permit write/read to/from a common memory. CONSTITUTION:The holding circuits L1, L2, logical gates G1, G2 and decoders D1, D2 are made to correspond to respective processors MPU1, MPU2. Read detecting signals detected by the decoders D1, D2 are sent to the latch inputs D of the holding circuits L1, L2 as setting signals S1, S2 respectively through the logical gates G1, G2. The latch output Q of one holding circuit L1 is applied to the MPU1 side as a write permission signal Q1 of one MPU1 corresponding to the circuit L1. The write permission signal Q1 is applied to the logical gate G2 corresponding to the other MPU2 as an inhibition signal.

Description

[Detailed Description of the Invention] [Technical Field] The present invention relates to a technology that is particularly effective when applied to information processing technology and microcomputer systems, for example, in order to share one memory among multiple processors. The present invention relates to techniques that are effective for use in shared memory control circuits.

[Background technology]

In microcomputer systems, two processors (MPUs) are sometimes used in the same system to increase processing capacity. In such multiprocessor systems, some of the memory is shared by the two processors. In this case, the shared memory is shared between the two processors MP, as shown in FIG. 1, to avoid electrical contention between the two processors.
U1. It is connected to the MPU 2 in a time-sharing manner in units of one machine cycle. However, according to the inventor's study, even if electrical contention could be avoided as described above, one MPUI would read and write, as shown in FIG. If the other MPU 2 writes during the interval, there is a risk that the instruction execution state in one MPUI will be disturbed in terms of software.

In order to avoid such software conflicts between the two MPUIs and MPU2, instructions that can read and write in the same machine cycle are required.

Either use a microprocessor with so-called TAS instructions, or create an operating system program that does not cause such conflicts, and operate two MPUIs, MPU2, under the control of this operating system program. must be done. However, in the former case, processors having TAS instructions are limited to some types of processors.

Therefore, if one of the two MPUI and MPU 2 is a processor that does not have a TAS instruction, that TAS instruction cannot be used for the above-mentioned conflict avoidance. In the latter case, for example, 1
It is necessary to perform troublesome procedures such as performing interrupt processing and executing a routine for conflict avoidance every time an instruction is executed. The inventors have revealed that, as a result, the software burden becomes extremely large, leading to problems such as a significant decrease in processing speed.

[Purpose of the invention]

The purpose is to avoid software conflicts without using special instructions such as TAS instructions. In addition, by simply adding a relatively simple hardware configuration without significantly increasing the software processing load, it is possible to reliably avoid software conflicts that occur when a single memory is shared by multiple processors. An object of the present invention is to provide a shared memory control circuit as described above.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Summary of the invention]

A brief overview of typical inventions disclosed in this application is as follows.

In other words, it is a circuit that controls the use of memory shared by a plurality of processors, in which each processor is associated with a holding circuit, and when a - processor reads from the shared memory, the circuit controls the use of memory shared by a plurality of processors. a set signal is given to a holding circuit to be used, and the set state of the holding circuit prohibits setting of the holding circuit corresponding to each other processor;
Further, a signal is given from the holding circuit to only the - processor corresponding to the set holding circuit to permit writing to the shared memory, so that, for example, the TAS
It is possible to share one memory among multiple processors by simply adding a relatively simple hardware configuration, without using special instructions such as commands, and without significantly increasing the software processing burden. The purpose of this is to ensure that software conflicts that occur in the software can be avoided.

〔Example〕

Hereinafter, typical embodiments of the present invention will be described with reference to the drawings.

In addition, the same or corresponding parts are indicated by the same reference numerals in the drawings.

FIG. 2 shows an embodiment of a shared memory control circuit according to the present invention. The circuit shown in the figure includes a shared memory RAM consisting of a random access memory, latch circuits Ll and L2 provided as holding circuits, and logic gates Gl and G2.
, decoders DI, D2, etc. Latch circuits Ll, L2. Logic gates Gl, G2, decoder DI
, D2 correspond to the respective processors MPUI and MPU2.

That is, one is provided for each processor.

Here, RAM is two microprocessors MPUI
, MPU2. MPUI side bus B1
and bus B12 on the MPUZ side are each bus switching circuit MP.
Connect to the RAM via X. This connection is performed in a time-division manner in units of one machine cycle, as shown in the timing chart shown in FIG. This avoids electrical contention between the MPUI and the MPU2.

The buses B1 and 82 include an address bus, a data bus, and a control signal bus for write, read, chip select, and the like. Each bus Bl, B2 has a decoder DI, D, respectively.
Connected to 2. Each decoder DI.

Each D2 detects whether the corresponding processor has started a read operation to the RAM via the buses B1 and B2. This detection can be performed easily and immediately in real time by, for example, logically multiplying the read signal and the chip select signal. Decoder DI.

The readout detection signal detected by D2 passes through logic gates Gl and G2, respectively, and then to a latch circuit Ll.

The latch of R2 is sent as set signals SL and S2.

Here, the latch output Q of one latch circuit L1 is given to one MPUI as a write permission signal Q1 of one MPUI corresponding to this latch circuit L1. At the same time, the write enable signal Q1 is given as an inhibit signal to the logic game G2 corresponding to the other MPU2. In addition, the latch output of the other latch circuit L2 is
The write permission signal Q2 of the other MPU2 corresponding to the write permission signal Q2 is given to the MPUI side. At the same time, the write permission signal Q2 is a logic game corresponding to one MPU1)
is given as a prohibition signal. In other words, the latch circuits Ll and L2 operate exclusively. Only the latch circuit L1 or R2 corresponding to the processor that starts the read operation to the RAM first is set. Then, the processor M receives the write enable signal Q1 or G2 from the set latch circuit L1 or R2.
Only PUI or MPU2 gets the right to write after its read. This right lasts until the reset signal R1 or R2 is applied to the reset force R of the latch circuit. This reset signal R1 or R2 is
It is given from the processor side that received the write permission signal. The reset signals R1 and R2 are generated, for example, by a register allocated to a specific address area in a memory address space managed by the processor. When the processor sets the register in the specific address area, the set state of the register becomes the reset signal R1 or R2 and is sent to the reset signal R of the corresponding latch circuit L1 or R2. In addition, the write permission signal Q1
．． Q2 sets a register assigned to a specific address area within the memory address space managed by the processor. The processor can determine the presence or absence of the write permission signal Q1 or G2 by reading the specific address area assigned to the register. Once it is confirmed that there is a write permission signal, it is not possible to continue writing or reading by occupying the shared RAM unless the user issues a reset signal and relinquishes the right. can.

In FIG. 3, one MPUI first performs successive output, which sets one latch circuit L1, and the other MPUI
2 shows a state in which setting of the latch circuit L2 corresponding to No. 2 is prohibited. As a result, one MPU 2 can continue to use the shared RAM until the series of processing operations is completed without performing interrupt processing or the like in the middle.

〔effect〕

The two MPUIs and MPU2 each manage the presence or absence of the write permission signal Q1pQ2 for itself, which is a very simple procedure.
Software conflicts caused by sharing
This can be reliably avoided without significantly sacrificing processing speed. Further, the hardware configuration for this purpose has the advantage that only a simple additional configuration is required as described above. without using special commands such as TAS commands,
In addition, by simply adding a relatively simple hardware configuration without significantly increasing the software processing load, it is possible to reliably avoid software conflicts that occur when a single memory is shared by multiple processors. be able to.

Although the invention made by the present inventor has been specifically explained above based on examples, it goes without saying that this invention is not limited to the above-mentioned examples, and can be modified in various ways without departing from the gist thereof. Nor. For example, the write permission signal Q, 1. Q2 may be mutually sent to the other processor as a write inhibit signal.

[Application field]

In the above description, the invention made by the present inventor has mainly been explained with respect to microcomputer systems, which is the field of application behind the invention, but the present invention is not limited thereto, and can be applied to, for example, peripheral devices.

[Brief explanation of drawings]

FIG. 1 is a timing chart showing an example of software conflict. ↓ The second is a circuit diagram showing an embodiment of the shared memory control circuit according to the present invention. FIG. 3 is a timing chart showing an example of the operation of the circuit shown in FIG. MPUI, MPU2...microprocessor, MP
X...Shared memory switching circuit, RAM...Shared memory, Ll, L2...Holding circuit (latch circuit), Dl. B2...Decoder, Gl, G2...Gate, 81°B2...Set signal, Q it Q 2...Write permission signal, R1, R2...Reset signal, Bl, B2
···bus. Figure 1 Figure 3, Figure 12 Figure 2

Claims (1)

[Claims] 1. A circuit for controlling the use of a memory shared by a plurality of processors, wherein each processor is associated with a holding circuit, and a - processor reads the shared memory. At the same time, a set signal is given to the holding circuit corresponding to the processor, and depending on the set state of the holding circuit, setting of the holding circuit corresponding to the other processors is prohibited, and A shared memory control circuit characterized in that the holding circuit gives a signal to only the corresponding processor - to permit writing to the shared memory. 2. The shared memory control circuit according to claim 1, wherein the shared memory is connected to each processor in a time-sharing manner in units of one machine cycle.