JPH0716190Y2 - Vending machine controller - Google Patents

Description

[Detailed Description of the Invention] (Industrial Application Field) The present invention relates to mechanism control data, product sales control data, sales circuit data, etc. of a vending machine stored in a Random Access Memory (hereinafter referred to as RAM). The present invention relates to a vending machine control device that controls a vending machine with a microcomputer using data.

(Prior Art) In a conventional vending machine, when the microcomputer controls the product discharge mechanism, temperature, and other controls, the data and flags required for each control are stored in RAM, and the microcomputer controls. At the time of execution, the RAM is directly operated by hardware to read or write data or the like, and the control sequence is processed according to the data. That is, when writing data to the RAM, conventionally, the microcomputer writes the data by sending the memory request signal MREQ and the write signal WR which are write signals to the CE terminal and WE terminal of the RAM.

(Problems to be solved by the invention) However, in the past, when a program ran out of control due to noise or some other factor and a write signal was erroneously output from the microcomputer, erroneous writing of data occurred and the RAM There is a problem that normal data will be destroyed, and even after stopping the program runaway after such a state, it was impossible to recover the control function because the RAM data was destroyed. .

(Means for Solving the Problems) In order to achieve the above-mentioned object, the present invention receives a central processing unit of a microcomputer, a RAM, and an I / O request signal and a write signal sent from the central processing unit. I
I / O controller that sends / O write signal and also sends memory write signal in response to memory request signal and write signal, and RAM write by receiving port signal for I / O circuit selection sent from the central processing unit A programmable selector that sends a select signal,
Receiving an I / O write signal and a RAM write select signal sent from each of the input / output controller and the programmable selector to enter a data writable state and receiving a memory write signal sent from the input / output controller in the data writable state. A data write control circuit that sends a data write signal to the RAM only during a period of time, and stops sending of the data write signal when the memory write signal is cut off, and returns to a data write prohibited state. I am trying.

(Operation) According to the present invention, the data write control circuit which can be selected by the port output of the microcomputer is provided between the microcomputer and the RAM, and the data write control circuit normally puts the RAM in the data write disable state. Therefore, the write signal is not sent to the RAM only by receiving the write signal from the microcomputer.

When writing data to RAM, the RAM write selector signal is sent from the programmable selector to the data write control circuit based on the program sequence predetermined by the microcomputer, and the I / O write signal is sent from the input / output controller. Then, the data write control circuit is set to the data writable state, and the write signal is sent to the RAM only while the memory write signal is sent from the input / output controller to the data write control circuit in the data writable state. I try to write data. The data write control circuit becomes write-inhibited again at the same time when the memory write signal is sent.

(Embodiment) An embodiment of the present invention will be described below with reference to the control block diagram showing the circuit configuration of FIG. 1 and the time chart of FIG.

In the figure, 1 is a central processing unit of a microcomputer, 2 is a RAM, 3 is an input / output controller for sending out input / output control signals, 4 is a programmable selector for selecting an input / output circuit, and 5 is data writing in RAM2. Is a data write control circuit that controls the data writing, 6 is a data write signal that enables writing of data in the RAM 2, 7 is a data bus, and 8 is an address bus.

Central processing unit 1 of microcomputer, data bus 7
And address bus 8 to RAM2. When a predetermined port signal is sent from the output ports P0 to P3 of the central processing unit 1 to the programmable selector 4 for selecting an input / output circuit based on a predetermined program sequence, the programmable selector 4 outputs a data write control circuit. A RAM write select signal is sent to 5. Further, in synchronization with this, an I / O request signal IORQ and a write signal WR are sent from the central processing unit 1 to the input / output controller 3, and the input / output controller 3 which has received these signals sends the data write control circuit 5 to the input / output controller 3. I / O write signal is sent out.

RAM write select signal and I to the data write control circuit 5
In the state where the / O write signal is sent, the data write control circuit 5, which is normally in the data write inhibit state for the RAM 2, latches the RAM write select signal and the I / O write signal input almost at the same time to write data. It becomes the writable state (enable state).

Next, a memory request signal is sent from the central processing unit 1 to the input / output controller 3 based on the program sequence.
The MREQ and the write signal WR are sent out, and the memory write signal is sent to the data write control circuit 5 from the input / output controller 3 which receives this signal. At this time, the central processing unit 1 of the microcomputer sends the data to be written in the RAM 2 to the data bus 7.

As described above, when the memory write signal is input while the RAM write select signal and the I / O write signal are input to the data write control circuit 5, the data write control circuit 5 receives the memory write signal. Only while
The data write signal 6 is sent to the RAM 2, and the RAM 2 receives the data write signal 6 and becomes writable, and the value on the data bus 7 is written in the address shaded by the address bus 8.

Next, the data write sequence of the RAM 2 will be described with reference to the flowchart of FIG.

The microcomputer 1 first sets a data write address (step 1), then sets write data (step 2), and then sets a data write permission port (step 3). Next, the I / O write signal and the RAM write select signal are sent from the input / output controller 3 and the programmable selector 4 to the data write control circuit 5 (step 4). Next, the memory write signal is sent from the input / output controller 3 to the data write control circuit 5,
The data write signal 6 is sent from the data write control circuit 5.
The data is sent to the RAM2, and the data is written from the microcomputer 1 to the RAM2 through the data bus 7 (step 5). Next, the control signal output of the microcomputer 1 is cut off, the memory write signal of the input / output controller 3 is cut off, and the data write control circuit 5 releases the latch and enters the write-inhibited state again, where the data write sequence is ended. (Step 6).

(Effect of the Invention) As described in detail above, according to the present invention, a data write control circuit which can be selected by the port output of the microcomputer is provided between the microcomputer and the RAM. Since the RAM is in the data write prohibited state, the write signal is not sent to the RAM only by receiving the write signal from the microcomputer. When writing data to RAM, the RAM write selector signal is sent from the programmable selector to the data write control circuit based on the program sequence predetermined by the microcomputer, and the I / O write signal is sent from the input / output controller. Then, the data write control circuit is set to the data writable state, and the write signal is sent to the RAM only while the memory write signal is sent from the input / output controller to the data write control circuit in the data writable state. Since the data is written, unless the microcomputer normally executes each step of the sequence control, the write protection by the data write control circuit cannot be released and the data cannot be written in the RAM. Therefore, even when the program runs out of control and the write signal is erroneously output from the macro computer, it is possible to reliably prevent the RAM data from being destroyed and protect the data.

[Brief description of drawings]

FIG. 1 is a control block diagram showing a circuit configuration of the present invention, FIG. 2 is a flow chart of a RAM writing sequence of the present invention, and FIG. 3 is a time chart of the present invention. 1 ... Microcomputer, 2 ... RAM, 3 ... Input / output controller, 4 ... Programmable selector, 5 ... Data write control circuit, 6 ... Data write signal, 7 ... Data bus, 8 ... Address bus.

Claims (1)

[Scope of utility model registration request] 1. A central processing unit 1 of a microcomputer.
And RAM2 and I / O request signal and write signal sent from the central processing unit 1 to send I / O write signal and memory request signal and write signal to send memory write signal I / O controller 3
A programmable selector 4 for receiving a port signal for selecting an input / output circuit sent from the central processing unit 1 and sending a RAM write select signal; and an I / O sent from the input / output controller 3 and programmable selector The data write signal is sent to the RAM 2 only while receiving the memory write signal sent from the input / output controller 3 in the data writable state in response to the O write signal and the RAM write select signal. And a data write control circuit (5) that stops sending of the data write signal and returns to a data write prohibited state when the memory write signal is cut off.