JPS60239850A - Microprocessor system provided with no-break memory - Google Patents

Abstract

PURPOSE:To prevent a no-break memory from incorrect writing due to the runaway of a program by inhibiting writing ordinally, forming a write inhibition releasing signal only at a writing time and impressing AND between the release signal and the writing signal to a non-volatile RAM. CONSTITUTION:Ordinarlly, an H level reading signal is impressed from a gate 6 to the R/W terminal of the non-volatile RAM(NVRAM)4, data reading is available and writing is inhibited. When a data writing request is generated, an L level signal S'w for releasing write inhibition is outputted from the PA1 terminal of an interface 15 to the gate 16. Since a write request signal W'R' is outputted from a CPU1 to the gate 16, the output of the gate 16 is turned to the L level and a write signal W'R' is impressed to the NVRAM4. The NVRAM4 stores data obtained from a data bus 5 in an address area selected by a chip selector signal C'S' outputted from an address decoder 7.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a microprocessor system equipped with an uninterruptible memory that prevents erroneous writing to the uninterruptible memory due to program runaway or the like.

[Conventional technology]

An example of a conventional microprocessor system equipped with an uninterruptible memory is the one shown in Figure 1.
A ROM 2 stores programs for causing the UI to execute various processes.

A RAM 3 that temporarily stores the results of processing by the OPU 1 and various data, and a non-volatile memory IJ (NVRAM) that stores data or programs that are supplied with power from the battery after the main power is cut off. 4
, a data bus 5 that connects each component and transmits data in parallel bits, an address bus 6 that performs address specification, and a memory group connected to the control lines of the address bus s and 0PUx to perform chip selection of the memory group. The battery 9 is connected to the power supply terminal of the NVRAM 4 via the address decoder 7 and the diode 8 for backflow prevention, and supplies the main power supply d at one time. For example, +4.3V)
The circuit 9 is composed of an electric FA voltage detection circuit 10 and an electric FA voltage detection circuit 10 which switches the power supply to the NVRAM 4 to the battery 9 when the voltage becomes below. Although not shown in the figure, an output interface 78 for controlling external equipment, terminal equipment, etc., and an input interface 78 for inputting all types of information are connected to the data bus 5 and address bus 6. has been done.

'-The source voltage detection circuit 10 is the power supply ■. . A resistor 11 is connected to the resistor 11, a Zener diode 12 is connected between the resistor 11 and ground and the Zener voltage v8 is set to the detection level voltage (4,3V), and input terminals are connected to both ends of the resistor 11. A voltage comparator 13 maintains the output voltage at a high level when vcc>v2 and changes the output voltage to a low level when v8≧vcc, and is turned on when the output voltage of the comparator 13 is at a high level. . , is applied to the NVRAM 4, and when the output voltage is at a low level, it is turned off and the voltage of the battery 9 is transferred to the JffRAM via the diode 8.
41c is applied to the transistor 14.

In the above configuration, the RD signal from 0PU1 is transferred to the ROM.
When the program is output to RAM 2, the program in ROM 2 is read out, and the WR signal or WR signal is output to RAM 3 and NV.
Data is written to or read from the memory chip selected by the O8 signal applied to the RAM 4 and output from the address decoder 7. For example, when VCC drops to 91% due to a power outage, etc., %4.3■
Then, OPU 1, ROM 2, RAM
3 and address decoder 7 become inoperable,
Although the data stored in RAM 3 will be deleted, NV
At the same time as the transistor 14 turns off, the RAM 4
Since the voltage of the battery 9 is applied, the stored data is preserved without being erased.

[Problem that the invention seeks to solve]

However, according to the conventional uninterruptible memory IJ t-equipped microprocessor, V, the program crashed due to some reason.
: If this occurs, there is a risk that the uninterruptible memory will be accessed by mistake, and if such a situation occurs, the contents of the uninterruptible memory will not be guaranteed and may cause serious damage to the equipment being controlled. There is a fear that it will not reach the target.

[Means and operations for solving the problems] The present invention has been made in view of the above.

In order to prevent erroneous writing to the uninterruptible memory due to program runaway, etc., writing is always prohibited and a write prohibition release signal is generated in synchronization with the write signal. The logical product of the release signal and the write signal WR1 is taken and a write signal is applied to the NVRAM "j7" to provide an uninterruptible memory for the microprocessor system.

〔Example〕

Hereinafter, a microprocessor system equipped with an uninterruptible memory according to the present invention will be described in detail.

Figure 2 shows an embodiment of the present invention, and the same parts as in Figure 1 are indicated by the same reference numerals, so redundant explanation will be omitted, but writing is prohibited only when a write request is made according to the program set in ROM2. The interface 15 outputs a release signal 8W, and the gate 16 (
A V writing prohibition circuit) is provided.

In the above configuration, the overall operation is as described above, so redundant explanation will be omitted, but the write operation will be explained based on FIG. 3. During normal operation, a high-level read signal from the gate 16 is applied to the R/W terminal of the NVRAM 4.

This makes it possible to read data from the RAM 4 at any time (in a write-inhibited state).

On the other hand, CPU 1
interface 150PAI as determined by
A release signal for releasing the low level write protection is output from the terminal to the gate 16, and a write request signal WR from the n terminal of 0PUI is output to the gate 12. At this time.

Both inputs of the gate 16 are at a low level, so the output voltage changes from a high level to a low level state, and a -2F write signal WR is applied to the NVRAM 4. NVRAM that receives the WR multiplied signal output from gate 16
4 stores the data on the data bus 5 in the address area selected by the preset V vector signal (aS) output from the address decoder 7. OP the end of writing
When U1 is determined, it outputs the WR multiplication signal to the gate 16, and also outputs the write inhibit signal 5v to the interface 15.
It outputs to the rf gate 16 and changes the output voltage of the gate 16 from low level to high level.

In this way, writing to the NVRAM 4 is possible only when both of the gates 16 are at low level, and writing is prohibited in normal times. Therefore, even if a program stall occurs due to power supply voltage cutoff or the like, a write failure signal will not be applied to the NY) LAM 4, and erroneous data will not be written.

〔Effect of the invention〕

As explained above, according to the TL microgrosse and T system, the uninterruptible memory of the present invention is provided.

A signal that can be negatively ANDed with the write signal WB output from the OPU and WB only at the time of writing is output, and the write signal is applied to the NVRAM when the logical conditions for both are satisfied, so writing is prohibited. Even if the program sometimes goes out of control, the uninterruptible memory will not be overwritten, and there is no risk of data being erroneously written.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a conventional microprocessor system equipped with an uninterruptible memory 'Th, FIG. 2 is a circuit diagram showing an embodiment of the present invention, and FIG. 3 is a time chart of the embodiment of FIG. 2. Explanation of codes 1... OPU, 2... Shame M, 3... Pigeon, 4...
Uninterruptible memory (NVRAM), 5...data bus, 6...address bus, 7...address decoder. 8...Diode% 9...Battery, 10...
・Power supply voltage detection circuit, 15...interface, 1
6...Gate. Patent applicant: Fuji Zero, representative of Kusu Co., Ltd. Patent attorney: Shin Matsuhara 2 Patent attorney: Kiyoshi Muraki Patent attorney: Taira 1) Yudo Tadashi Patent attorney: Atsushi Ueshima - Patent attorney: Hitoshi Suzuki Figure 1, Figure 2 figure

Claims (1)

[Scope of Claims] An operating system that is equipped with an uninterruptible memory that is backed up by a battery when the voltage of the main power supply drops below a certain value, and that executes various processes according to programs stored in the ROM.
In a microprocessor system that writes and reads data using a PU. signal generating means for outputting a write prohibition release signal when a data write request is made to the uninterruptible memory, and outputting a write prohibition signal upon completion of the write operation; A microprocessor system equipped with an uninterruptible memory, comprising: a game circuit that outputs a write signal to the uninterruptible memory only when an AND condition with a write signal is satisfied.