JP2002099468A - Writing control circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To efficiently prevent a miswriting into a memory. SOLUTION: In a writing control circuit, a protect circuit 20 is arranged on a line to apply a writing control signal to a memory 12 from a CPU 10. The circuit 20 does not output the control signal while a reset signal is applied from a reset circuit 22. Then, an occurrence of the miswriting into the memory 12 at on-off time of power source is prevented with outputting the reset signal at dropping of a power source voltage.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a write control circuit for permitting data writing to a memory in response to a write control signal from a CPU.

[0002]

2. Description of the Related Art Conventionally, in a data processing device such as a microcomputer, various memories are used for storing data, and a flash memory or an EEPROM is used as a rewritable nonvolatile memory. .

[0003] These nonvolatile memories store predetermined data at the time of manufacture, are shipped, and rewrite data as needed.

[0004]

In such a non-volatile memory, it is assumed that the stored contents are not lost when the power is normally turned off. Therefore, if an erroneous write occurs here, there is a problem in the subsequent operation. Occurs. For this reason, there is a demand to prevent erroneous writing to the memory.

On the other hand, the CPU and the memory are connected by a plurality of signal lines, and writing of the memory is controlled by the CPU. For example, as shown in FIG.
The memory 10 and the memory 12 are connected by a write control signal line, a chip selection signal line, an address bus, and a data bus. Then, as shown in FIG. 7, while the write control signal line and the chip select line are at L level, the data set on the data bus is written to the address of the memory set on the address bus.

Here, erroneous writing to the memory is likely to occur when the power is turned on or off or when the CPU goes out of control. The reason will be described.

First, when the power supply is turned on and off, the power supply voltage rises from 0 to a predetermined voltage and drops from the predetermined voltage to 0. The normal memory has a write protection function that prevents writing when the voltage of the device itself drops. Therefore, the memory is protected from erroneous writing when the power supply voltage becomes a fixed voltage, for example, about 2 V or less in a memory operating at 3.3 V.

On the other hand, a guaranteed operation voltage is specified for a CPU, and a 3.3 V operation CPU is usually 2.7 V to 3.6 V.
V. Therefore, in the range of 2V to 2.7V, the CPU
Erroneous output from the memory, and erroneous writing to the memory may occur. That is, as shown in FIG. 8, when both the write control signal and the chip select signal are at L level, undefined data is written to an undefined address at that time.

When the CPU goes out of control, all outputs may be undefined. In such a case, both the write control signal and the chip select signal may be at the L level.

The present invention has been made in view of the above problems, and has as its object to provide a write control circuit that can effectively prevent erroneous writing to a memory.

[0011]

According to the present invention, there is provided a write control circuit for permitting data writing to a memory in response to a write control signal from a CPU.
A reset signal generating circuit for generating a reset signal when the voltage is higher than the operation guarantee voltage of U and lower than a normal power supply voltage; and a write control signal when the reset signal is generated from the reset signal generating circuit. And a protection circuit for prohibiting write permission by the above.

As described above, according to the present invention, the reset signal is generated from a voltage higher than the voltage at which the CPU may malfunction, and writing to the memory is prohibited.
Therefore, even if the CPU generates an erroneous write control signal, erroneous writing to the memory can be effectively prevented.

According to another aspect of the present invention, there is provided a write control circuit for permitting data writing to a memory in response to a write control signal, comprising: a general-purpose I / O port whose signal output is controlled by a CPU; A protection circuit for prohibiting write permission by a write control signal when a write permission signal is not output from the O port.

As described above, according to the present invention, when writing to a memory, it is necessary to permit writing from a general-purpose I / O port. When CPU runs away, general-purpose I / O
It is almost impossible to perform a procedure such as outputting a write enable signal from a port and then generating a write control signal. Therefore, even if the CPU goes out of control, erroneous writing to the memory can be effectively prevented.

[0015]

Embodiments of the present invention (hereinafter referred to as embodiments) will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of the embodiment. A CPU 10 and a memory 12 are connected by a write control signal line, a chip selection signal line, an address bus, and a data bus. And a write control signal,
When the chip selection signal is set to L, data on the data bus is written to an address of the memory 12 determined by a value on the address bus.

In this embodiment, the protection circuit 20 is inserted and arranged in the write control signal line.
The protection circuit 20 is supplied with a reset signal from a reset circuit 22.

The protection circuit 20 is formed of, for example, an OR gate as shown in the drawing, and when the reset signal is H, the output is fixed at H. Therefore, the reset signal is H
During this period, the write control signal 2 is prohibited from going low.

On the other hand, when the power supply voltage is C
When the voltage is equal to or lower than the operating voltage of the PU 10 (for example, D [V]: about 2.8 V), H is output as a reset signal.
For example, a comparator is provided which inputs a power supply voltage to a negative input terminal and a voltage D to a positive input terminal. Thereby, when the power supply voltage becomes equal to or less than D, H is obtained in the output of the comparator. The output of H from this comparator indicates that the power supply voltage is a voltage (for example, B
[V]: H may be output up to 2.0 V), which is set as such.

Therefore, according to this circuit, erroneous writing is prevented as shown in FIG. That is, in this example, the power supply voltage gradually decreases, and
When the voltage becomes equal to or lower than the voltage B at which the operation of
U10 outputs L as the write control signal 1. Therefore, the write control 1 supplied from the CPU 10 to the protection circuit 20 becomes L level. However, at the stage when the power supply voltage has dropped to the voltage D, the reset signal has become H, so that the write control signal 2 which is the output of the protection circuit 20 remains at H, and the writing to the memory 12 is surely performed. Is prevented.

It is also preferable that the protection circuit 20 or the reset circuit 22 inform the CPU 10 of this protection state to notify that the writing process cannot be performed.

FIG. 3 shows a configuration for preventing erroneous writing of the memory 12 when the CPU 10 runs out of control. In this example, the protection circuit 20 includes a general-purpose I / O
A signal from the port 24 is supplied.
Then, when writing to the memory 12, the CPU 10 controls the general-purpose I / O port 24 to output a write permission signal. Then, writing to the memory 12 is enabled only during the period when the write permission signal is output from the general-purpose I / O port 24.

That is, as shown in FIG.
Causes the general-purpose I / O port 24 to output L as a write enable signal. Next, the CPU 10 executes the write control 1
To L. Since the write enable signal is at L, the protect circuit 20 outputs L as the write control 2.
Therefore, in this state, the CPU 10 sets the chip selection signal to L.
Thus, the data on the data bus is written to the memory address determined by the value on the address bus. When the writing is completed, the CPU 10 returns to the general-purpose I / O.
The write enable signal from the / O port 24 is returned to H.

On the other hand, when the CPU 10 is running out of control, the CPU 10 controls the general-purpose I / O port 24 as described above.
It is almost impossible to set the write enable signal from L to L in advance and then set both the write control 1 and the chip select signal to L. Therefore, CPU
Even at the time of runaway of 10, the erroneous writing to the memory 12 can be effectively prevented.

[0025]

As described above, according to the present invention,
A reset signal is generated from a voltage higher than the voltage at which the CPU may malfunction, and writing to the memory is prohibited. Therefore, even if the CPU generates an erroneous write control signal, erroneous writing to the memory can be effectively prevented.

According to the present invention, when writing to a memory, it is necessary to permit writing from a general-purpose I / O port. When the CPU goes out of control, it is almost impossible to take a procedure such as outputting a write enable signal from the general-purpose I / O and then generating a write control signal. Therefore, even if the CPU goes out of control, erroneous writing to the memory can be effectively prevented.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of a first embodiment.

FIG. 2 is a diagram illustrating waveforms of respective units according to the first embodiment.

FIG. 3 is a diagram illustrating a configuration of a second embodiment.

FIG. 4 is a diagram illustrating waveforms of respective units at the time of writing according to a second embodiment.

FIG. 5 is a diagram illustrating waveforms of respective units when writing is prohibited according to the second embodiment.

FIG. 6 is a diagram showing a configuration of a conventional example.

FIG. 7 is a diagram for explaining a write operation of a conventional example.

FIG. 8 is a diagram for explaining erroneous writing in a conventional example.

[Explanation of symbols]

10 CPUs, 12 memories, 20 protection circuits,
22 reset circuit, 24 general purpose I / O ports.

Claims (2)

[Claims] 1. A write control circuit for permitting data writing to a memory in response to a write control signal from a CPU, wherein the power supply voltage is higher than the operation guarantee voltage of the CPU and is lower than the normal power supply voltage. A reset signal generating circuit that generates a reset signal in a low state; and a protect circuit that prohibits writing by a write control signal when the reset signal is generated from the reset signal generating circuit. Write control circuit. 2. A write control circuit for permitting data writing to a memory according to a write control signal, comprising: a general-purpose I / O port whose signal output is controlled by a CPU; A write control circuit, comprising: a protection circuit for prohibiting write permission by a write control signal when a permission signal is not output.