JP2701790B2 - Nonvolatile semiconductor memory device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a non-volatile semiconductor device, and more particularly to a non-volatile semiconductor device for preventing a program from being rewritten twice.

[0002]

2. Description of the Related Art Conventionally, as a countermeasure to prevent writing to a non-volatile memory IC twice due to runaway of software or the like, writing to a memory IC is performed by providing a protection terminal to the memory IC and applying a high voltage. Is made impossible.

However, in the above-mentioned method, since control for applying a high voltage to the memory IC is performed by software, if the software runs out of control after the software releases the guard, the above-described method is performed. The countermeasure taken is invalidated, and there is a possibility that chip element destruction or the like may occur.

Further, since a high voltage is applied, a memory IC
In this case, two power supply systems, i.e., a normal voltage and a high voltage, are provided on a board that uses the power supply, thereby significantly reducing the reliability of the board.

[0005] Therefore, there is a memory IC disclosed in Japanese Patent Application Laid-Open No. 5-67758 as a memory IC in which the above points are improved.

FIG. 3 is a block diagram of a memory IC disclosed in Japanese Patent Application Laid-Open No. 5-67758.

The memory IC shown in FIG. 3 is a flash EEPROM having a memory cell array 11 divided into four blocks 110 to 113. A source line SL is provided in each of the blocks. Data can be erased. further,
In each block, a state storage circuit 2 storing 1-bit data indicating whether data has already been written or data has been erased from the block.
00, 210, 220 and 230 are blocks 110 to 110
113 are provided for each of them.

In this conventional example having the above-described configuration, the potential level in a block is detected prior to data rewriting and data erasing for an arbitrary block, whereby data has already been written in the block. It can be checked in a short time whether the data has been erased or the data has already been erased from within the block, and erroneous data writing or data erasing can be prevented.

[0009]

In a nonvolatile memory IC, when new writing is performed without erasing written data, that is, when data is written twice, the data in the element is not written. Overlap may occur, causing a temporary unstable state or, in the worst case, destruction of the element.

In the above-mentioned conventional example, there is provided a state storage unit for confirming whether data is written or erased in the memory cell.

However, since the state storage unit is configured using the same elements as the nonvolatile memory unit, there is a possibility that the state storage unit itself may become unstable due to twice writing data. Further, since the write state is determined by detecting the potential level in the block, when the detected level is determined to be in the erased state near the threshold level, the write state is determined even when the state is close to the written state. Is performed, which may cause an unstable state of the memory IC or destruction of elements.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems of the prior art, and prevents an unstable state of a nonvolatile memory IC due to twice writing of data or occurrence of element destruction. It is an object of the present invention to provide a nonvolatile semiconductor memory device that can perform the above-mentioned operations.

[0013]

SUMMARY OF THE INVENTION In order to achieve the above object, the present invention relates to a nonvolatile semiconductor memory device in which external data writing is prohibited while data is being written in a nonvolatile memory section. A second threshold having a value lower than a first threshold which is a threshold for judging a data write state in the nonvolatile memory unit; comprises a potential state holding register is determined to be a state in which the potential level data in the nonvolatile memory unit if it exceeds the second threshold value is written, said potential state holding register
The star is configured by an element different from the nonvolatile memory.
It is characterized by having been done.

The nonvolatile memory section for writing data and the potential level of the electric charge in the nonvolatile memory section when the data is written from the outside to the nonvolatile memory section are set as threshold values. And determining whether or not the first threshold value exceeds a first threshold value. If the first threshold value is exceeded, a write state holding register for prohibiting data writing to the nonvolatile memory unit is provided. Having a value lower than the first threshold value as a second threshold value, and when writing data from the outside to the nonvolatile memory portion, the potential level of the electric charge in the nonvolatile memory portion. Is determined to be greater than or equal to the second threshold value, and if so, a potential state holding register for inhibiting writing of data to the nonvolatile memory unit is set. And Bei, said potential state holding register,
It is composed of an element different from the nonvolatile memory.
It is characterized by the following.

[0015]

[0016]

According to the present invention constructed as described above, at the same time data is written from the outside to the nonvolatile memory section, the potential level of the charges in the nonvolatile memory section is input to the potential state holding register. It is determined whether or not the potential level input to the potential state holding register exceeds a certain threshold value, thereby determining whether or not data is being written. Is lower than the threshold value in the non-volatile memory section, so that it is determined that data is being written even when the potential level of the input charge is near the threshold value in the non-volatile memory section. Is done.

In the case of adopting an existing architecture having a write state holding register, the threshold value of the potential state holding register is set lower than that of the write state holding register. It is determined that data is being written even when the potential level is near the threshold value in the nonvolatile memory section.

[0018]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is an internal block diagram showing one embodiment of the nonvolatile semiconductor memory device of the present invention.

In this embodiment, as shown in FIG. 1, a nonvolatile memory section 2 for writing data, an address control circuit 1 to which an address and a chip select signal are input and outputs an address latch signal, A read control circuit 5 that receives a read signal and reads data from the nonvolatile memory unit 2 and a write / read circuit that receives write data or an erase signal from the outside to the nonvolatile memory unit 2
The erase control circuit 6, a write state holding register 3 for holding a write state of data in the nonvolatile memory section 2, and a write state of the data in the nonvolatile memory section 2 held in the write state holding register 3. And a potential state holding register 4 to be held.

The operation of the above configuration will be described below.

(1) In case of read access The ADR signal lines a and / CS
An address and a chip select signal are input from the outside via the signal line b.

When an address and a chip select signal are input to the address control circuit 1, an address latch signal is sent to the nonvolatile memory unit 2 and the write state holding register 3 via the INADR signal line c.

In the case of read access, a read select signal is externally input to the read control circuit 5 via the / RDS signal line f, and data in the nonvolatile memory unit 2 corresponding to the externally input address signal is read. But RDDA
It is output to the outside via the TA signal line j and the DATA signal line g. At this time, since it is not in the write access state, the other signal lines are inactive.

(2) Write state holding register 3: "
1 ", the potential state holding register 4: in the case of write access from the state of" 0 ", the ADR signal line a and / CS
An address and a chip select signal are input from the outside via the signal line b.

When an address and a chip select signal are input to the address control circuit 1, the nonvolatile memory unit 2, the write state holding register 3, and the potential state holding register 4
, An address latch signal is sent via the INADR signal line c.

Next, a write enable signal and write data are externally input to the write state holding register 3 and the write / erase control circuit 6 via the / WE signal line d and the DATA signal line g.

When a write enable signal and an address signal are input to the write state holding register 3, the non-volatile memory section 2 is in a state where data has not yet been written. The erase state “1” is reported to the register cell corresponding to the corresponding address of the potential state holding register 4 as the contents of the register bit of the write holding register 3. In this case, the register cell of the potential holding register 4 is in the erase state "0".

When the erase state is reported to the register cell, it is determined that the write cell corresponding to the address of the nonvolatile memory unit 2 is in the erased state, and the following control is performed.

First, when write data is externally written to the nonvolatile memory unit 2 via the write / erase control circuit 6 and the WERDATA signal line k, a write state indicating that data is written to the nonvolatile memory 2 “0” is set in the write state holding register 3.

Next, the writing state is set in the potential state holding register 4. The flow until the writing state in the potential state holding register 4 is set will be described.

First, when write data is written to the nonvolatile memory unit 2, the / INWE signal line h becomes active, and the write data is input to the potential state holding register 4 via the WERDATA signal line k.

Here, in the write state or the erase state, the state is determined by manipulating the flow of the electric charge. Therefore, the input of the write data means that the electric charge is injected into the potential state holding register 4. It turns out that.

When a charge is injected into the potential state holding register 4, it is detected how many volts the charge is charged.

According to the detection result, the write state is set to "1" when the threshold value exceeds a certain threshold level which is the second threshold value, and the erase state is set to "0" when the threshold level is lower than the threshold level. The write state is set in the corresponding register bit.

FIGS. 2A and 2B are diagrams showing potential regions for judging the write / erase state according to the present invention. FIG. 2A is a diagram in the nonvolatile memory unit 2, and FIG. 2B is a diagram in the potential state holding register 4. It is.

As shown in FIGS. 2A and 2B, if the potential level of the electric charge injected into the nonvolatile memory unit 2 is sufficiently higher than the threshold level which is the first threshold value (in the figure, (Near area B), the potential state holding register 4 determines that the write state is the write state, and the write state “1” is set. In addition, the nonvolatile memory unit 2
If the potential level of the charge injected into the memory cell is sufficiently lower than the threshold level (near area A in the figure), the potential state holding register 4 determines that the write state is the erase state, and sets the erase state "0".

Here, the potential level of the injected charge is
The operation of the potential holding register 4 in the vicinity of the threshold level (around the area C in the figure) will be described.

In the vicinity of the threshold level, even if the potential level exists in the erase area, the write state in the nonvolatile memory section 2 is almost as close as possible to the write state because the potential level is around the threshold. Therefore, when data is written to the write cell of the nonvolatile memory unit 2 in a state where the potential level is around the threshold level, there is a possibility that a state similar to twice writing may occur. Therefore, as shown in FIG. 2B, the threshold level of the potential state holding register 4 which is the second threshold is set to be lower than the threshold level of the nonvolatile memory unit 2 which is the first threshold. Set lower.

Thus, in a state where the potential level exists in the vicinity of the region C in FIG. 2, it is always determined to be the write state.

As described above, when data is written to the nonvolatile memory unit 2, the write state in the write state holding register 3 is the write state "0", and the write state in the potential state holding register 4 is also the write state "1".
"And writing to the nonvolatile memory unit 2 twice is prevented.

(3) Write state holding register 3: "
0 ", the potential state holding register 4: in the case of write access from the state of" 1 ", the ADR signal line a and / CS
An address and a chip select signal are input from the outside via the signal line b.

When an address and a chip select signal are input to the address control circuit 1, the nonvolatile memory unit 2, the write state holding register 3, and the potential state holding register 4
, An address latch signal is sent via the INADR signal line c.

Next, a write enable signal and write data are externally input to the write state holding register 3 and the write / erase control circuit 6 via the / WE signal line d and the DATA signal line g.

At this time, since the write state holding register 3 corresponding to the input address is in the write state "0", data has already been written in the write cell of the nonvolatile memory unit 2 corresponding to the input address. It turns out that.

Therefore, the / INWE signal line h is not activated by the write state holding register 3,
No data is written to the nonvolatile memory unit 2. When the / busy signal line e is set to the active state by the write state holding register 3, it indicates that an address to which data has already been written has been accessed externally.

In this case, the potential state holding register 4 and V
The movement of the alt signal line i is the same as in the case of the write access from the state of the write state holding register 3: “1” and the state of the potential state holding register 4: “0”.

(4) Write state holding register 3: "
1 ", potential state holding register 4: write access from" 1 "state In this state, the potential level of the charge of the write cell corresponding to an arbitrary address in the nonvolatile memory unit 2 is changed to the C area in FIG. This is in the case where it exists around a threshold level as shown in the vicinity.

In this case, the / INWE signal line h is not set to the active state by the potential state holding register 4, and no data is written to the nonvolatile memory unit 2. The / busy signal line e is set to the active state by the potential state holding register 4 to indicate that an address to which data has already been written to the outside has been accessed.

In the above-described embodiment, only the configuration of prohibiting writing to the nonvolatile memory portion to which data is written, which is the gist of the present invention, has been described. However, the nonvolatile memory portion to which data is written is described. When it is recognized that the erase operation is performed, a normal erase operation may be performed, and thereafter, the erase operation may be confirmed by the above-described procedure, and writing may be performed.

The charge information holding register described above can provide the same effect even when it is outside the memory IC.

[0052]

Since the present invention is configured as described above, it has the following effects.

According to the first aspect, the threshold value for determining whether or not data is written in the nonvolatile memory unit is set to a value lower than the threshold value in the nonvolatile memory unit. Because of the configuration including the register, even if the potential level of the detected electric charge is near the threshold value in the nonvolatile memory portion, it is determined that data is being written, and the nonvolatile memory IC that writes data twice is used. Can be prevented from being in an unstable state or element destruction. In addition, the potential state holding register
Is configured with a different element from the nonvolatile memory.
Therefore, the potential state holding register itself stores data twice.
Preventing writing into an unstable state
it can.

According to the second aspect of the present invention, since a potential state holding register similar to the above is provided in an existing architecture, a new device is not designed,
The same effect as that of the first aspect can be obtained. In addition, the potential state holding register is a non-volatile memory.
Since it is composed of different elements,
The register itself is unstable due to writing data twice
Can be prevented from falling into a state.

[0055]

[Brief description of the drawings]

FIG. 1 is an internal block diagram showing one embodiment of a nonvolatile semiconductor memory device of the present invention.

FIGS. 2A and 2B are diagrams showing a potential region for determining a write / erase state according to the present invention, wherein FIG. 2A is a diagram in a nonvolatile memory unit, and FIG. 2B is a diagram in a potential state holding register.

FIG. 3 is a block diagram of a memory IC disclosed in JP-A-5-67758.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Address control circuit 2 Non-volatile memory unit 3 Write state holding register 4 Potential state holding register 5 Read control circuit 6 Write / erase control circuit a ADR (address) signal line b / CS (chip select) signal line c INADR (internal address) ) Signal line d / WE (write enable) signal line e / busy signal line f / RDS (read select) signal line g DATA signal line h / INWE (internal write enable) signal line i Volt signal line j RDDATA (read data) Signal line k WERDATA (write / erase data) signal line

Claims (2)

(57) [Claims] 1. A non-volatile semiconductor memory device in which external data writing is prohibited while data is being written in a non-volatile memory unit, wherein the non-volatile memory unit determines a data writing state. A second threshold having a value lower than the first threshold, which is a threshold value to be set, when the potential level of the electric charge in the nonvolatile memory portion exceeds the second threshold. A potential state holding register for determining that data is being written in the nonvolatile memory unit, wherein the potential state holding register is different from the nonvolatile memory;
A non-volatile semiconductor storage device, comprising: 2. A nonvolatile memory section for writing data, and a potential level of a charge in the nonvolatile memory section is set as a threshold when data is written to the nonvolatile memory section from outside. And determining whether the first threshold value is exceeded, and if the first threshold value is exceeded, a write state holding register for prohibiting writing of data to the nonvolatile memory unit is provided. A second threshold having a value lower than the first threshold, and a potential level of charges in the nonvolatile memory unit when data is written from the outside to the nonvolatile memory unit. A potential state holding register for judging whether the threshold value exceeds the second threshold value, and in the case of exceeding the second threshold value, prohibiting writing of data to the nonvolatile memory portion. , Said potential state holding register is different to the non-volatile memory
A non-volatile semiconductor storage device, comprising: