KR100341424B1 - Microcomputer - Google Patents

Abstract

Only when the protected data is correct, the rewrite of the program command of the first storage area by the rewrite command of the second storage area of the flash memory is permitted. When the program command in the address area A is rewritten in accordance with the result of the decoding of the rewrite command in the address area B of the flash memory 9, the onboard signal OB always becomes the logical value "1". Therefore, when the protection data is not used, as the protection data identification circuit 16 outputs a logic value "0", the control signal WRT falls when the page buffer 14 stores 128 words of program data. The flash memory 9 is in a write inhibit state. Therefore, the flash memory 9 enters the write permission state only when the protected data is correct.

Description

Microcomputers {MICROCOMPUTER}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microcomputer incorporating a nonvolatile memory (flash memory) having characteristics capable of bulk or partial electric erasing of data and recording and reading of data.

9 is a block diagram showing a flash memory device, which is built in and functions in a microcomputer.

In Fig. 9, reference numeral 1 denotes a flash memory, which is nonvolatile capable of electrically erasing data in batches or parts (for example, in units of pages 128 words) and repeatedly recording and reading data. Has the characteristics of. The flash memory 1 functions as a program memory of a microcomputer, and program instructions for executing various logical operations are stored in the internal cells of the address area A, and the program commands of the address area A are rewritten in the internal cells of the address area B. It is remembered that the rewrite command to do so. The flash memory 1 normally jumps from the address area A so that the address area A is designated and the address area B is designated only when an interrupt request for rewriting the program contents of the address area A is generated. The microcomputer executes various logical arithmetic operations in accordance with the decoding result of the program command read out from the address area A of the flash memory 1, while the microcomputer performs the decoding result of the rewrite command read out from the address area B of the flash memory 1; Therefore, the rewrite operation of the contents of the address area A is executed. The rewrite data in the address area A of the flash memory 1 is preliminarily prepared in the microcomputer (method of separately installing a mask ROM and stored as table data) or supplied from the outside of the microcomputer. (Method of supplying from a PROM recorder, etc.) may be sufficient.

Reference numeral 2 is an address decoder which decodes address data for addressing the flash memory 1. Reference numeral 3 denotes a detection circuit, which prevents the problem that the program command in the address area A of the flash memory 1 is incorrectly rewritten against the user's intention. In detail, the detection circuit 3 comprises a plurality of registers 4 and a decoder 5. The plurality of registers 4 store the protection data (AAH, 55H, etc.) prepared in advance by the user in the previous step of rewriting the program command (page unit) of the address area A of the flash memory 2. The decoder 5 decodes whether or not the values of the plurality of registers 4 are intended by the user, and if all the values of the plurality of registers 4 are correct, permits the rewrite operation of the flash memory 1 and In the case where one value of the plurality of registers 4 is wrong, the logical structure is configured to prohibit the rewrite operation of the flash memory 1. Reference numeral 6 is a page buffer (volatile memory such as a static RAM) and has a storage capacity of 128 words for rewriting the program command in the address area A of the flash memory 1 in units of one page. The page buffer 6 has an increment function for addressing itself. The rewrite data is once stored in the page buffer 6 and then written to the designated page of the address area A of the flash memory 1.

As a method for rewriting a program command in the address area A of the flash memory 1, an external control method using a PROM writer and an internal control method using a rewrite command in the address area B of the flash memory 1 can be considered.

Here, in addition to the internal cells of the address area A and the address area B, the flash memory 1 has a protection cell 7 for discriminating the need and the need of the protection data. The protective cell 7 may be 1 bit. The detection circuit 3 is controlled in accordance with the value of the protective cell 7. That is, the detection circuit 3 rewrites the address area A of the flash memory 1 regardless of the presence or absence of protected data when the content of the protective cell 7 is a logic value "0" (reset state). Outputs a signal to allow. On the other hand, the detection circuit 3 prohibits the rewrite operation of the address area A of the flash memory 1 when the protection data does not exist when the content of the protective cell 7 is a logic value "1" (set state). The rewrite operation of the address area A of the flash memory 1 is allowed only when the protected data exists and is correct.

In the case of the external control method using the former PROM recorder, the logic value "0" or the logic value "1" is stored in the protective cell 7 in a state where the operation of the microcomputer is stopped. You can choose. For example, when the PROM recorder prepares fixed protected data in advance, and the PROM recorder supplies the protected data to two different microcomputers, only one of the microcomputers may recognize the protected data. . Therefore, when it is desired to always make compatibility between the PROM recorder and various microcomputers, the logical value "0" may be stored in the protective cell 7. Accordingly, the detection circuit 3 permits the rewrite operation of the address area A of the flash memory 1 regardless of the presence and state of the protected data. In other words, the compatibility is the main factor that allows the selection of the need and need of the protected data. The PROM writer supplies the page buffer 6 with a 128-word program command to be rewritten among the address areas A of the flash memory 1, and then becomes a rewrite target of the address area A of the flash memory 1. Address data in units of pages is sequentially supplied to the address decoder 2. Therefore, the contents of the page buffer 6 are written to the designated page of the address area A of the flash memory 1, and the rewrite operation is completed.

In the case of the internal control method using the rewrite command in the address area B of the latter flash memory 1, the contents of the protective cell 7 cannot be controlled conventionally. In detail, the rewriting of the address area A of the flash memory 1 is performed either in the initial state of the protective cell 7 (usually in the reset state) or in the state of the protective cell 7 after external control is performed using the PROM writer. I was dependent on either side. In the latter internal control method, since it is not necessary to be compatible with other microcomputers, it is preferable to use protected data for prevention of miswriting. However, if the logical value "0" is stored in the protective cell 7 against the user's intention, when the rewrite operation is executed in accordance with the result of the decoding of the rewrite command, the protected data is registered in the wrong state due to the congestion of the program processing. Even in the case of (4), there was a problem that the program command in the address area A was rewritten, whereby the program command in the address area A could not be rewritten correctly.

Therefore, an object of the present invention is to enable a rewrite operation only when the protected data is correct when rewriting a program command of the first storage area using the rewrite command of the second storage area of the nonvolatile memory.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and has a characteristic of being able to erase or collectively erase data, and to record and read data, and to execute program instructions for executing various logical operations on the first storage area. Is stored, a nonvolatile memory in which a rewrite command for rewriting the contents of the first storage area is stored in a second storage area, and protection data for preventing erroneous rewriting of the first storage area of the nonvolatile memory is set. A microcomputer having a register and a decoder for decoding a value of the register to permit or prohibit rewriting of a first storage area of the nonvolatile memory in accordance with a decoding result, wherein the rewrite command of the second storage area of the nonvolatile memory is issued. The register when rewriting the program command of the first storage area by using the Only when the correct protection of data sets, characterized in that a means for permitting a rewriting of the first storage area of the nonvolatile memory.

1 is a circuit block diagram showing a microcomputer of the present invention.

2 is a time chart showing the relative relationship of each waveform;

Fig. 3 is a time chart showing an operation in the case of using protected data in a state in which a protective cell is reset using a PROM writer.

Fig. 4 is a time chart showing an operation when no protection data is used in a state in which a protection cell is reset using a PROM writer.

Fig. 5 is a time chart showing an operation in the case of using protected data in a state where a protective cell is set using a PROM recorder.

Fig. 6 is a time chart showing an operation when no protection data is used in a state in which a protection cell is set using a PROM recorder.

Fig. 7 is a time chart showing an operation when protection data is used by using a rewrite command in the address area B of the flash memory.

Fig. 8 is a time chart showing an operation when protection data is not used by using a rewrite command in the address area B of the flash memory.

9 is a block diagram showing a conventional flash memory device.

<Explanation of symbols for main parts of drawing>

9: flash memory

12: register

13: decoder

14: page buffer

15: protective cell

28: CPU

Details of the present invention will be described in detail with reference to the drawings.

1 is a circuit block diagram showing a microcomputer of the present invention.

In Fig. 1, reference numeral 8 denotes a clock generator, which is supplied with an oscillation clock of an oscillation circuit (either self or other oscillation provided with an oscillation oscillator such as crystal or ceramic). In this case, a system clock for executing various logic operations is generated by performing logic processing such as division into the oscillation clock.

Reference numeral 9 denotes a flash memory (non-volatile memory), which is a nonvolatile memory capable of electrically erasing data in batches or partially (for example, in pages (128 words)) and repeatedly recording and reading data. Has characteristics. The flash memory 9 functions as a program memory of a microcomputer, and program instructions for executing various logical operations are stored in the internal cells of the address area A, and the program commands of the address area A are rewritten in the internal cells of the address area B. The rewrite command for storing is stored. The flash memory 9 usually jumps from the address area A so that the address area A is designated and the address area B is designated only when an interrupt request for rewriting the program contents of the address area A is generated. The microcomputer executes various logical arithmetic operations in accordance with the decoding result of the program command read from the address area A of the flash memory 9, while the decoding result of the rewrite command read from the address area B of the flash memory 9 is executed. In accordance with this, the rewrite operation of the contents of the address area A is executed. In addition, the rewrite data of the address area A of the flash memory 9 is prepared in advance in the microcomputer (method of separately installing a mask ROM and storing it as table data), or is supplied from the outside of the microcomputer. (Method of supplying from a PROM recorder, etc.) may be sufficient.

The flash memory 9 includes the following peripheral circuits in addition to the internal cells for data storage. Reference numeral 10 denotes an address decoder which decodes address data (m bits) for addressing the flash memory 9. Reference numeral 11 is a detection circuit to prevent a problem that a program command in the address area A of the flash memory 9 is incorrectly rewritten against the user's intention. In detail, the detection circuit 11 includes a plurality of registers 12 and a decoder 13. The plurality of registers 12 store the protection data (AAH, 55H, etc.) prepared in advance by the user in the previous step of rewriting the program command (page unit) of the address area A of the flash memory 9. The decoder 13 decodes whether or not the values of the plurality of registers 12 are values intended by the user, and if all the values of the plurality of registers 12 are correct, the decoder 13 permits the rewrite operation of the flash memory 9. In the case where any one of the plurality of registers 12 is wrong, the logical structure is configured to prohibit the rewrite operation of the flash memory 9. Reference numeral 14 is a page buffer (volatile memory such as a static RAM) and has a storage capacity of 128 words for rewriting the program command in the address area A of the flash memory 9 in units of one page. The page buffer 14 has an increment function for addressing itself. The rewrite data is once stored in the page buffer 14 and then written to the designated page of the address area A of the flash memory 9.

Reference numeral 15 is a protective cell, and when a program command in the address area A is rewritten using a PROM writer, a logical value "0" or a logical value "1" is stored in accordance with the control instruction of the PROM writer. When the protective cell 15 is at a logic value "0" (reset state), the detection circuit 11 rewrites the flash memory 9 in a state of allowing rewrite of the flash memory 9 irrespective of the presence or absence of protection data for preventing the miswriting of the address area A. Shall be. On the other hand, when the protective cell 15 is at the logic value "1" (set state), the detection circuit 11 sets the flash memory 9 to the rewrite permission state only when the protection data exists and is correct.

Reference numeral 16 is a protection data identification circuit that outputs a logical value "1" when protection data is set in the plurality of registers 12. Here, the CPU described later outputs the onboard signal OB having the logic value "1" when rewriting the program command in the address area A using the rewrite command in the address area B of the flash memory 9. The value of the protective cell 15 and the onboard signal OB are supplied to the NOR gate 17. That is, when the value of the protective cell 15 is a logic value "0", the output of the NOR gate 17 changes according to the value of the onboard signal OB. In addition, the value of the protection data identification circuit 16 and the output logic value of the NOR gate 17 are supplied to the NOR gate 18. That is, when the value of the protective cell 15 or the onboard signal OB is a logic value "1", the output of the NOR gate 18 changes in accordance with the value of the protection data identification circuit 16. In the D-type flip-flop 19, after the flash memory 9 enters the write operation permission state in accordance with the result of reading the values of the plurality of registers 12, the page buffer 14 stores a program instruction in units of one page. In synchronism with the clock CLK2 generated immediately after, the output logic value of the NOR gate 19 is held.

Reference numeral 20 is a control circuit, which operates in accordance with the result of the decoding of the program command in the address area A of the flash memory 9, and reads the operation permission signal * CE, the write permission signal * WE, and reads the flash memory 9. It supplies the grant signal * OE, the record prohibition signal WI, and the record end signal EOW.

Reference numeral 21 is an identification circuit that outputs a logic value "1" in synchronization with the falling of the operation permission signal * CE and the write permission signal * WE. The output logic value, the write prohibition signal WI, and the write end signal EOW of the D flip-flop 19 are supplied to the OR gate 22. Reference numeral 25 is an RS flip-flop composed of NOR gates 23 and 24, and the output logic value of the identification circuit 21 is supplied to one input terminal (set terminal) of the NOR gate 23, and the OR gate is provided. An output logic value of 22 is supplied to one input terminal (reset terminal) of the NOR gate 24, and outputs a control signal WRT for making an internal cell in the address area A of the flash memory 9 writable. It is. In detail, the control signal WRT rises when the value of the identification circuit 21 becomes the logical value &quot; 1 &quot;, and any one of the value of the D flip-flop 19, the write prohibition signal WI, and the write end signal EOW It descends when the logic value is "1". The control signal WRT is made high active. 2 is a time chart showing the relative relationship between the operation permission signal * CE, the write permission signal * WE, the read permission signal * OE and the write prohibition signal WI. The write prohibition signal WI occurs after a predetermined time after the operation permission signal * CE and the write permission signal * WE change to the low level in accordance with the result of the decoding of the rewrite command in the address area B of the flash memory 9. In detail, the write prohibition signal WI is used for a period from immediately after the operation enable signal * CE and the write enable signal * WE change to the high level until the operation enable signal * CE and the read enable signal * OE change to the low level. Occurs.

The control circuit 20 includes a flag 26. The flag 26 indicates that the forced setting signal PL for forcibly setting the flash memory 9 to the writable state irrespective of the state of the control signal WRT is determined by the decoding result of the rewrite command in the address area B of the flash memory 9. Therefore, it is set. The flag 26 is reset in accordance with the falling WRTDOWN of the control signal WRT at the time when writing from the page buffer 14 to the address area A is finished. The control signal WRT and the force setting signal PL are supplied to the reset terminal of the detection circuit 11 through the OR gate 27, and the values of the plurality of registers 5 change the output of the OR gate 27 to a low level. It is reset at one time. As an effect of the forced setting signal PL, since the values of the plurality of registers 12 are not reset even when the control signal WRT falls, the detection circuit 11 can reliably detect the right and wrong of the protected data.

Reference numeral 28 denotes a CPU which executes various logical arithmetic operations in accordance with the decoding result of the instruction read from the address areas A and B of the flash memory 9, and includes ALUs, ACCs, various registers, and the like. Reference numeral 29 is a program counter that generates address data (m bits) for addressing the flash memory 9. The program counter 29 is used to read a command from the flash memory 9. Reference numeral 30 denotes m latch circuits and addresses for designating a partial region of the address region A generated by the CPU 28 according to the result of the decoding of the rewrite command read from the address region B of the flash memory 9. The data (m bits) is latched in synchronization with the clock CK0. Similarly, reference numeral 31 denotes n latch circuits for latching new program data (n bits) for rewriting in the address area A of the flash memory 9 in synchronization with the clock CK1. The latch circuits 30 and 31 are used to rewrite the program command in the address area A of the flash memory 9. The switching circuit composed of the AND gates 32 and 33 and the OR gate 34 converts and outputs address data of either the program counter 29 or the latch circuit 30 to the flash memory 9. Reference numeral 35 denotes a selection circuit, which supplies a selection signal SELECT for instructing the switching of address data to the switching circuit. That is, the selection signal SELECT is at the high level when the value of the program counter 29 is supplied to the flash memory 9, and is at the low level when the value of the latch circuit 30 is supplied to the flash memory 9. The address data switched from the switching circuit are supplied to the address decoder 10 for addressing the flash memory 9 and also to the detection circuit 11 for selecting the plurality of registers 12, but the address decoder Since there cannot be simultaneous operation of the 10 and the detection circuit 11, there is no problem. Program data output from the latch circuit 31 is supplied to the plurality of registers 12 and the page buffer 14.

When the CPU 28 rewrites the program command in the address area A using the rewrite command in the address area B of the flash memory 9, the CPU 28 outputs a high level on-board signal OB, together with the value of the protective cell 15. It is supplied to the NOR gate 17.

First, a case of rewriting the program command in the address area A of the flash memory 9 using the PROM writer will be described.

3 is a time chart showing an operation in the case where the protective cell 15 is reset and protection data is supplied.

In the state where the operation of the microcomputer is stopped, various signals are supplied from the PROM recorder to the flash memory 9. When the operation permission signal * CE and the write permission signal * WE fall, the control signal WRT rises in accordance with the set of the RS flip-flop 25, and the internal cell of the address area A of the flash memory 9 becomes writable. do. The protection data is set in the register 12 in synchronization with the change of the operation permission signal * CE and the write permission signal * WE. In addition, since the value of the protective cell 15 is a logic value "0", the input of the D-type flip-flop 19 is a logic value "0" regardless of the output of the protection data identification circuit 16. In addition, the write prohibition signal WI does not occur. Therefore, when the write end signal EOW occurs, the control signal WRT falls in accordance with the reset of the RS flip-flop 25. In other words, the control signal WRT continues the high level until the first operation permission signal * CE and the recording permission signal * WE have been generated until the recording end signal EOW occurs. When the set of protected data for the register 12 and the storage of the 128-word program data for the page buffer 14 are terminated, the erase signal ERASE occurs, and the rewrite target page of the address area A of the flash memory 9 is generated. The contents are erased, the write signal PROGRAM is generated, and the contents of the page buffer 14 are written to the address area A of the flash memory 9. Here, when the write signal PROGRAM rises, the protective cell 15 becomes a logic value "1". That is, afterwards, in order to perform rewriting of the address area A of the flash memory 9, protected data is required. If the write signal PROGRAM falls, the write end signal EOW occurs. That is, the control signal WRT falls in accordance with the reset of the RS flip-flop 25.

4 is a time chart showing the operation when the protection cell 15 is reset and no protection data is supplied.

In the state where the operation of the microcomputer is stopped, various signals are supplied from the PROM recorder to the flash memory 9. When the operation permission signal * CE and the write permission signal * WE fall, the control signal WRT rises in accordance with the set of the RS flip-flop 25, and the internal cell of the address area A of the flash memory 9 becomes writable. do. In addition, since the value of the protective cell 15 is a logic value "0", the input of the D-type flip-flop 19 is a logic value "0" irrespective of the output of the protection data identification circuit 16. In addition, the write prohibition signal WI does not occur. Therefore, when the write end signal EOW occurs, the control signal WRT falls in accordance with the reset of the RS flip-flop 25. In other words, the control signal WRT continues the high level until the first operation permission signal * CE and the recording permission signal * WE have been generated until the recording end signal EOW occurs. When the storage of the 128-word program data for the page buffer 14 ends, the erase signal ERASE occurs, the contents of the rewrite target page in the address area A of the flash memory 9 are erased, and the write signal PROGRAM is generated. The contents of the page buffer 14 are written to the address area A of the flash memory 9. Here, the value of the protective cell 15 remains as it is in the logical value "0". If the write signal PROGRAM falls, the write end signal EOW occurs. That is, the control signal WRT falls in accordance with the reset of the RS flip-flop 25.

Fig. 5 is a time chart showing an operation in the case where the protection cell 15 is set and protection data is supplied.

In the state where the operation of the microcomputer is stopped, various signals are supplied from the PROM recorder to the flash memory 9. When the operation permission signal * CE and the write permission signal * WE fall, the control signal WRT rises in accordance with the set of the RS flip-flop 25, and the internal cell of the address area A of the flash memory 9 becomes writable. do. The protection data is set in the register 12 in synchronization with the change of the operation permission signal * CE and the write permission signal * WE. In addition, since the value of the protective cell 15 is logical value "1", the input of the D flip-flop 19 depends on the output of the protection data identification circuit 16. As shown in FIG. That is, since the output of the protection data identification circuit 16 is a logic value "1", the input of the D-type flip-flop 19 is a logic value "0". In addition, the write prohibition signal WI does not occur. Therefore, when the write end signal EOW occurs, the control signal WRT does not fall until the reset of the RS flip-flop 25 occurs. In other words, the control signal WRT continues the high level until the first operation permission signal * CE and the recording permission signal * WE have been generated until the recording end signal EOW occurs. If the result of decryption of the protected data is correct, the write operation of the flash memory 9 is permitted, and 128 words of program data are stored in the page buffer 14. Thereafter, the erase signal ERASE occurs, and the contents of the rewrite target page in the address area A of the flash memory 9 are erased. After that, the write signal PROGRAM is generated, and the contents of the page buffer 14 are written to the address area A of the flash memory 9. When the recording signal PROGRAM falls, the recording end signal EOW is generated. Therefore, the control signal WRT falls in accordance with the reset of the RS flip-flop 25.

Fig. 6 is a time chart showing the operation when the protection cell 15 is set and no protection data is supplied.

In the state where the operation of the microcomputer is stopped, various signals are supplied from the PROM recorder to the flash memory 9. When the operation permission signal * CE and the write permission signal * WE fall, the control signal WRT rises in accordance with the set of the RS flip-flop 25, and the internal cell of the address area A of the flash memory 9 becomes writable. do. In addition, since the value of the protective cell 15 is logical value "1", the input of the D flip-flop 19 depends on the output of the protection data identification circuit 16. As shown in FIG. That is, since the output of the protection data identification circuit 16 is a logic value "0", the input of the D-type flip-flop 19 is a logic value "1". In addition, the write prohibition signal WI does not occur. Accordingly, the D-type flip-flop 19 holds the logic value "1" in synchronization with the clock CLK2 generated after a predetermined time (for example, 300 mu sec) has elapsed from the end of the data storage operation to the page buffer 14. That is, the control signal WRT falls in accordance with the reset of the RS flip-flop 25, and the write operation of the flash memory 9 is prohibited.

Next, a case of rewriting the program command in the address area A using the rewrite command in the address area B of the flash memory 9 will be described.

7 is a time chart showing an operation in the case of supplying protected data.

When an interrupt request for rewriting the program command in the address area A occurs while the microcomputer is executing various logical arithmetic operations in accordance with the decoding result of the program command in the address area A of the flash memory 9, the program counter 29 ) Jumps from the address area A to the address area B. Then, the microcomputer starts the rewrite operation in accordance with the decoding result of the rewrite command in the address area B. FIG. At this time, the CPU 28 always outputs the onboard signal OB having the logic value "1". When the operation permission signal * CE and the write permission signal * WE fall, the control signal WRT rises in accordance with the set of the RS flip-flop 25, and the internal cell of the address area A of the flash memory 9 becomes writable. do. The protection data is set in the register 12 in synchronization with the change of the operation permission signal * CE and the write permission signal * WE. In addition, since the on-board signal OB is a logic value "1", the input of the D flip-flop 19 depends on the output of the protection data identification circuit 16. As shown in FIG. That is, since the output of the protection data identification circuit 16 is a logic value "1", the input of the D-type flip-flop 19 is a logic value "0". The write prohibition signal WI is generated at periodic intervals until the storage of the page buffer 14 ends, but since the forced setting signal PL is a logic value "1", there is no problem in the decoding of the register 12. When the decryption result of the protected data is correct, the erase signal ERASE is generated, and the contents of the rewrite target page in the address area A of the flash memory 9 are erased. Thereafter, the write signal PROGRAM is generated, the control signal WRT rises in synchronization with the operation permission signal * CE and the write permission signal * WE falling, and the contents of the page buffer 14 are changed in the address area A of the flash memory 9. Is written on. When the write signal PROGRAM falls, the write end signal EOW occurs, so that the control signal WRT falls in accordance with the reset of the RS flip-flop 25.

8 is a time chart showing an operation when no protection data is supplied.

When an interrupt request for rewriting a program command in the address area occurs when the microcomputer is executing various logical arithmetic operations in accordance with the decoding result of the program command in the address area A of the flash memory 9, the program counter 29 The value of jumps from the address area A to the address area B. Then, the microcomputer starts the rewrite operation in accordance with the decoding result of the rewrite command in the address area B. FIG. At this time, the CPU 28 always outputs the onboard signal OB having the logic value "1". When the operation permission signal * CE and the write permission signal * WE fall, the control signal WRT rises in accordance with the set of the RS flip-flop 25, and the internal cells of the address area A of the flash memory 9 are in a writeable state. do. The protection data is set in the register 12 in synchronization with the change of the operation permission signal * CE and the write permission signal * WE. In addition, since the onboard signal OB is a logic value "1", the input of the D-type flip-flop 19 depends on the output of the protection data identification circuit 16. That is, since the output of the protection data identification circuit 16 is a logic value "0", the input of the D-type flip-flop 19 is a logic value "1". The write prohibition signal WI is generated at periodic intervals until the storage of the page buffer 14 ends, but since the forced setting signal PL is a logic value "1", there is no problem in the decoding of the register 12. Then, the D flip-flop 19 holds the logic value "1" in synchronization with the clock CLK2 generated after a predetermined time (for example, 300 mu sec) has elapsed from the end of the data storage operation to the page buffer 14. That is, the control signal WRT falls in accordance with the reset of the RS flip-flop 25, and the write operation of the flash memory 9 is prohibited.

As described above, according to the embodiment of the present invention, when the program command in the address area A is rewritten using the rewrite command in the address area B of the flash memory 9, the protection data is independent of the state of the protective cell 15. The rewrite operation of the flash memory 9 is allowed only when the decryption result of the is correct. Therefore, when the program processing of the microcomputer is congested and the protection data is wrong, the rewriting operation of the address area A of the flash memory 9 can be reliably prevented.

According to the present invention, in the case of rewriting the program command of the first storage area using the rewrite command of the second storage area of the nonvolatile memory, the nonvolatile memory only when the result of decryption of the protection data is correct regardless of the state of the protective cell. To allow the rewrite operation. Thus, when the program processing of the microcomputer is congested and the protected data is wrong, an advantage can be reliably prevented from rewriting the first storage area of the nonvolatile memory.

Claims (1)

Having a characteristic that data can be erased collectively or partially, and that data can be written and read, a program instruction for executing various logical operations in a first storage area is stored and the first storage in a second storage area. A nonvolatile memory in which a rewrite command for rewriting the contents of the area is stored, a register in which protection data for preventing erroneous rewriting of a first storage area of the nonvolatile memory is set, and a value of the register is decrypted to decrypt the result. A microcomputer comprising a decoder which permits or prohibits rewriting of a first storage area of the nonvolatile memory according to the present invention, and a protective cell which stores a value for changing conditions for permitting external rewrite and internal rewrite. When rewriting the first storage area by external control, the first storage area of the nonvolatile memory can be rewritten in correspondence to a specific value of the protective cell, and the second memory of the nonvolatile memory is rewritten. When rewriting the program command of the first storage area using the rewrite command of the area, rewriting of the first storage area of the nonvolatile memory only when the correct protected data is set in the register regardless of the value of the protective cell. And a means for authorizing.