JP3695931B2 - Microcomputer - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a microcomputer having a built-in nonvolatile memory (flash memory or the like) that can electrically erase data collectively or partially (page unit or the like) and can repeatedly write and read data.
[0002]
[Prior art]
One-chip microcomputers have a built-in program memory for executing various logical operations, but most one-chip microcomputers have a built-in mask ROM and function as a program memory. This is because the mask ROM has a structural advantage that enables the one-chip microcomputer to be reduced in size and price. However, since the mask ROM requires a new program development if the program content after integration is incorrect, it has a drawback that the development cost increases and the delivery time is delayed.
[0003]
Therefore, recent one-chip microcomputers have built-in a non-volatile memory (flash memory) capable of electrical erasure of data and writing / reading of data in place of the mask ROM to compensate for the disadvantages of the mask ROM.
FIG. 3 is a circuit block diagram showing a conventional microcomputer.
In FIG. 3, reference numeral (1) denotes a clock generator, which is supplied with an oscillation clock of an oscillation circuit (which may be either free-running oscillation or other-running oscillation provided with an oscillation oscillator such as crystal or ceramic), and is divided into oscillation clocks. A system clock is generated for performing various logical operations by performing logical processing such as circumference.
[0004]
(2) is a flash memory (nonvolatile memory), which has the characteristics that data can be electrically erased all at once or partially (for example, in units of pages (128 words)), and data can be repeatedly written and read. The flash memory (2) functions as a program memory of the microcomputer. Program commands for executing various logical operations are stored in the internal cells in the address area A, and the program in the address area A is stored in the internal cells in the address area B. A rewrite instruction for rewriting the instruction is stored. The flash memory (2) normally jumps from the address area A so that the address area A is designated, and the address area B is designated only when an interrupt request for rewriting the program contents of the address area A is generated. The microcomputer executes various logical operation operations according to the result of decoding the program instruction read from the address area A of the flash memory (2), while the rewrite instruction read from the address area B of the flash memory (2). In accordance with the result of decoding, the rewriting operation of the contents of the address area A is executed. The rewrite data in the address area A of the flash memory (2) is supplied from the outside of the microcomputer by a method of preparing in advance inside the microcomputer (a method of separately providing a mask ROM and storing it as table data). Any of the methods (a method of supplying from a PROM writer, etc.) may be used.
[0005]
The flash memory (2) includes the following peripheral circuits in addition to the internal cell for data storage. In other words, (3) is an address decoder, which decodes address data (m bits) for addressing the flash memory (2). (4) is a detection circuit, which prevents inconvenience that the program instruction in the address area A of the flash memory (2) is erroneously rewritten against the intention of the user. Specifically, the detection circuit (4) includes a plurality of registers (5) and a decoder (6). The plurality of registers (5) store protection data (AAH, 55H, etc.) prepared in advance by the user at the stage before rewriting the program instruction (page unit) in the address area A of the flash memory (2). Is. The decoder (6) decodes whether or not the values of the plurality of registers (5) are values intended by the user, and rewrites the flash memory (2) if all the values of the plurality of registers (5) are correct. The logical structure is such that the operation is permitted and the rewrite operation of the flash memory (2) is prohibited when even one of the values of the plurality of registers (5) is incorrect. (7) is a page buffer (volatile memory such as static RAM), and has a storage capacity of 128 words for rewriting program instructions in the address area A of the flash memory (2) in units of one page. The page buffer (7) has an increment function for addressing itself. The rewritten data is temporarily stored in the page buffer (7) and then written to the designated page in the address area A of the flash memory (2).
(8) is an identification circuit for generating a control signal WRT for setting the internal cell in the address A area of the flash memory (2) to a writable state. The flash memory (2) is in a writable state when the control signal WRT becomes high level (logical value “1”). The control signal WRT is also supplied to the detection circuit (4), and the values of the plurality of registers (5) are reset when the control signal WRT becomes low level (logic value “0”).
[0006]
(9) is a control circuit, which operates according to the result of decoding the program instruction in the address area A of the flash memory (2), to the identification circuit (8), an operation permission signal * CE for the flash memory (2), A write enable signal * WE, a read enable signal * OE, and a write inhibit signal WI are supplied. The identification circuit (8) detects that the operation enable signal * CE and the write enable signal * WE have changed to a low level, sets the control signal WRT to a high level, and detects that the write inhibit signal WI has been generated and performs control. The signal WRT is set to low level. The write inhibit signal WI is generated after a predetermined time has elapsed since the operation enable signal * CE and the write enable signal * WE are changed to the low level according to the result of decoding the program instruction in the address area B of the flash memory (2). . Specifically, the write inhibit signal WI is generated in a period from immediately after the operation enable signal * CE and the write enable signal * WE change to the high level until the operation enable signal * CE and the read enable signal * OE change to the low level. To do.
[0007]
(10) is a CPU, which executes various logical operation operations according to the result of decoding the program instructions read from the address areas A and B of the flash memory (2). ALU, ACC, various registers, etc. Including. (11) is a program counter for generating address data (m bits) for addressing the flash memory (2). The program counter (11) is used when reading an instruction from the flash memory (2). (12) is m latch circuits, and designates a partial area of the address area A generated by the CPU (10) according to the result of decoding the rewrite instruction read from the address area B of the flash memory (2). Address data (m bits) is latched in synchronization with the clock CK0. Similarly, (13) is m latch circuits which latch new program data (n bits) for rewriting the address area A of the flash memory (2) in synchronization with the clock CK1. The latch circuits (12) and (13) are used when the program instruction in the address area A of the flash memory (2) is rewritten. The switching circuit comprising AND gates (14) and (15) and an OR gate (16) switches and outputs the address data of either the program counter (11) or the latch circuit (12) to the flash memory (2). is there. (17) is a selection circuit that supplies a selection signal SELECT for instructing the switching circuit to perform switching. That is, the selection signal SELECT becomes high level when the value of the program counter (11) is supplied to the flash memory (2), and low level when the value of the Q terminal of the latch circuit (12) is supplied to the flash memory (2). It becomes.
[0008]
The address data switched from the switching circuit is supplied to the address decoder (3) for addressing the flash memory (2) and also to the detection circuit (4) for selecting a plurality of registers (5). However, there is no problem because the address decoder (3) and the detection circuit (4) do not operate simultaneously. Program data output from the latch circuit (13) is supplied to a plurality of registers (5) and internal cells in the address area A.
[0009]
The relationship between the output of the control circuit (9) and the output of the identification circuit (8) is as shown in the time chart of FIG. In other words, the control signal WRT can be repeatedly set to the high level and the low level by the action of the write inhibit signal WI so that the flash memory (2) can be set to a writable state or a readable state.
[0010]
[Problems to be solved by the invention]
By the way, when the flash memory (2) is in the write state, the address designation is performed when the operation permission signal * CE falls, and the data is written when the operation permission signal * CE rises. Therefore, even if the protection data is stored in the plurality of registers (5), the contents of the plurality of registers (5) are reset each time the control signal WRT changes to the low level. There is no meaning provided. The microcomputer shown in FIG. 3 is only equivalent to one without an erroneous rewrite prevention function.
[0011]
SUMMARY OF THE INVENTION An object of the present invention is to provide a microcomputer that can prevent inconvenience that a program content in a nonvolatile memory is rewritten erroneously.
[0012]
[Means for Solving the Problems]
The present invention has been made to solve the above problems, and is a microcomputer incorporating a nonvolatile memory having characteristics capable of electrical erasing of data and writing / reading of data, wherein the nonvolatile memory Is in the write mode, a holding circuit for storing protection data for protecting the nonvolatile memory from erroneous writing, and a state of a stored value of the holding circuit are detected, and when the stored value is normal, A detection circuit that permits data rewriting of the nonvolatile memory and prohibits data rewriting of the nonvolatile memory when the stored value is abnormal, and states of an operation permission signal, a write permission signal, a read permission signal, and a write prohibition signal When a change is detected and the operation enable signal and the write enable signal become the first logic level, the internal memory of the nonvolatile memory is set. When the non-volatile memory is set to the write mode by outputting a control signal for making the write enable state, and the write inhibit signal is generated when the operation enable signal and the write enable signal are at the first logic level. An identification circuit that prohibits the output of the control signal and resets the stored value of the holding circuit, and sets the nonvolatile memory in the read mode when the operation permission signal and the read permission signal become the first logic level. And a compulsory setting signal for ignoring the control signal and setting the nonvolatile memory in a write mode from when the holding circuit starts storing protection data until the nonvolatile memory finishes data rewriting. And a compulsory setting circuit for outputting.
[0013]
The state of the nonvolatile memory and the holding circuit is controlled by a logical sum output of the control signal and the forced setting signal.
[0014]
DETAILED DESCRIPTION OF THE INVENTION
Details of the present invention will be specifically described with reference to the drawings.
FIG. 1 is a circuit block diagram showing a microcomputer of the present invention. In the description of FIG. 1, the same elements as those of FIG. 3 are denoted by the same reference numerals and the description thereof is omitted.
[0015]
In FIG. 1, (18) is a flag, which is built in the control circuit (9), and a forcible setting signal PL for forcibly setting the flash memory (2) to the write mode regardless of the state of the control signal WRT is It is set according to the result of decoding the rewrite command in the address area B of the flash memory (2). The flag (18) is reset when the control signal WRT falls. The control signal WRT and the forced setting signal PL are supplied to the reset terminal of the detection circuit (4) via the OR gate (19).
[0016]
The operation of FIG. 1 will be described with reference to the time chart of FIG.
First, when an interrupt request for rewriting the program command in the address area A of the flash memory (2) is generated, the address data for the program counter (11) to specify the address area B is sent via the switching circuit to the address decoder (3 ) And the value of the flag (18) becomes high level according to the result of decoding the rewrite instruction read from the address area B. As a result, the output of the OR gate (19) takes priority over the forcible setting signal PL and ignores the change in the control signal WRT, and the detection circuit (4) enters the reset release state. When the operation enable signal * CE and the write enable signal * WE fall, any one of the plurality of registers (5) is addressed, and then the operation enable signal * CE and the write enable signal * WE rise. When the protection data is stored in one of the addressed registers (5), the decoder (6) stores the stored value in the register (5) until the control signal WRT falls. Decipher whether the value is the intended value. A series of operations of address designation, protection data storage, and decryption are repeated by the number of the plurality of registers (5). If even one stored value of the plurality of registers (5) is different from the value intended by the user, the program command in the address area A of the flash memory (2) is erroneously rewritten against the user's intention. Judgment and rewrite operation are prohibited. On the other hand, when all the stored values of the plurality of registers (5) are values intended by the user, the rewrite operation of the program instruction in the address area A of the flash memory (2) is permitted. Accordingly, the page buffer (7) starts an increment operation, and new program data for one page (128 words) is supplied from the internal ROM table or the external PROM writer and written therein. When the writing of the page buffer (7) is completed, the program instruction read from the address area B of the flash memory (2) is decoded during the period when the operation enable signal * CE and the read enable signal * OE are at the low level. According to the result, the operation of writing the contents of the page buffer (7) into the address area A of the flash memory (2) is started. Specifically, when the operation enable signal * CE and the write enable signal * WE fall, the write inhibit signal WI is fixed at a low level, and the control signal WRT specifies the address area A of the flash memory (2) from the page buffer (7). It is fixed at the high level until the page write operation is completed. During this time, the selection signal SELECT is fixed at a low level. The value of the flag (18) is reset at the falling edge of the control signal WRT. Therefore, when the program rewrite operation in the address area A of the flash memory (2) is completed, the flash memory (2) returns to the state controlled by the control signal WRT.
[0017]
As described above, due to the effect of the forcible setting signal PL, a series of operations of address designation, protection data storage, and decryption for all the plurality of registers (5) can be executed, and the program instruction in the address area A of the flash memory (2) is erroneous Inconvenience of being rewritten can be prevented.
[0018]
【The invention's effect】
According to the present invention, a series of operations of address designation, protection data storage, and decryption for all the holding circuits can be executed by the effect of the forcible setting signal, and the program instruction of the nonvolatile memory is affected by some malfunction. There is an advantage that it is possible to prevent inconveniences such as erroneous rewriting against the will of the user.
[Brief description of the drawings]
FIG. 1 is a circuit block diagram showing a microcomputer of the present invention.
FIG. 2 is a time chart showing the operation of FIG. 1;
FIG. 3 is a circuit block diagram showing a conventional microcomputer.
4 is a time chart showing the operation of FIG. 3;
[Explanation of symbols]
(2) Flash memory (4) Detection circuit (5) Register (6) Decoder (7) Page buffer (8) Identification circuit (9) Control circuit (18) Flag (19) OR gate

Claims (1)

A microcomputer having a built-in nonvolatile memory composed of a plurality of blocks having a fixed storage capacity capable of electrical data erasing and data writing / reading,
A register storing protection data for protecting the nonvolatile memory from erroneous writing;
A decoder that detects the protection data and sets the nonvolatile memory in a write-enabled state;
A page buffer circuit having a storage capacity for one block of the plurality of blocks having the constant storage capacity, and temporarily storing write data in the nonvolatile memory in accordance with the write permission state;
While the write data is transferred from the page buffer circuit to one block in the nonvolatile memory, a control signal for resetting the register in which the protection data is stored responds to a result of decoding a command from the microcomputer. And a forcible setting circuit that maintains the protection data stored in the register when the control signal is ignored for the register and is ignored by the forcible setting signal output. Computer.

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