JPH05120891A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To protect a memory without the sacrifice of memory areas by using the combination between protection information and an external signal to determine whether a stop signal should be generated or not. CONSTITUTION:When the address stored in protection information is designated by an address signal 61, an address discriminating circuit 51 registers and discriminates it, and a gate signal is given to latch circuits 52 and 53, and data '1' or '0' is read out from a storage element group 1 through a sense amplifier 3. In the initial state, data is fixed to '1' or '0' by the semiconductor production method. In the case of data '1', a write stop signal is active and an erase stop signal is disabled, and a general data protection area is designated, and the storage element is erased from '1' to '0'. Write from '0' to '1' is started to test whether the protecting function is operated or not.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device having a nonvolatile memory write, erase, and read protection function.

[0002]

2. Description of the Related Art Conventionally, an EEPROM (Electricall)
y Erasable and Programmable Lead Only Nem
ory) is a non-volatile memory and is electrically rewritable, but on the contrary, there is a concern that data to be protected may be rewritten, which has been a problem. Therefore, as a method for inevitable protection of data in a non-volatile memory, a method has been proposed in which a security bit is used and access from outside the memory is prohibited depending on the state of the bit (for example, "Electronic Design" (Electronics).
Desin), March 3, 1983, pp.123-128). That is, a write-only security register, which is separated from a memory block intended for normal rewriting, is prepared, and access to the memory block is prohibited depending on the state of a specific bit of this register. In this case, as a method of configuring the security register with a rewritable memory element, the protection data of the memory block is protected by making the erase operation of the security register possible only when the entire erase operation of the memory block is performed. After the data is written in the register, the memory block cannot be accessed without destroying the data in the memory block.

[0003]

However, in this method, writing is performed once and data is written while permitting reading of the memory.
No consideration was given to the protection function that prevents rewriting of data. In addition, the conditions for erasing and writing the nonvolatile memory that constitutes the security register are
Since it is different from the data storage area, it is necessary to provide an independent erasing / writing circuit, which tends to complicate the circuit. Further, since the above method is a protection function that operates in units of the entire memory, it is not possible to control the protection data in each area by dividing it into partial and small capacities.
As another memory protection method known in the related art, there is a method of designating an area and protection contents by software. However, this method requires a separate storage device for storing these and system software for controlling the storage device, and therefore, the scale becomes large, and the nonvolatile memory such as a nonvolatile memory having a relatively small memory capacity is required. Not suitable for data protection. For example, in a microcomputer applied to a cache card or the like and having a built-in non-volatile memory, the non-volatile memory is used as a program storage area, I
There is a demand to use the areas separately for various different uses such as D code or data. In such a case, it is very important to prevent the functions such as reading and program erasing for each area divided into small areas in order to realize a highly reliable system. The purpose of the present invention is to
These conventional problems are solved, various protection functions are given to a small amount of memory, and only by storing the protection data in a rewritable data storage area, a condition for preventing rewriting is provided. A non-volatile semiconductor memory device that can be set is provided.

[0004]

In order to achieve the above object, a semiconductor memory device of the present invention comprises a plurality of memory element groups arranged in a matrix and at least 1-bit memory protection information arranged in the matrix. Protective data storage element to be stored, first means for accessing a selected one storage element of a plurality of storage element groups according to a specified address signal in a matrix, and contents of the protected data storage element And a second means for reading, the second means determines whether to permit or prohibit each program (write), erase, or read operation for one selected storage element, While determining according to the contents of the protection data storage element, the first means accesses the selected one storage element and the protection data storage element via a common word line, and also the storage element group and the storage element group. Fine protection de - is characterized by data storage device that consists of a storage device capable of respectively electrically rewritten.

[0005]

In the present invention, the protection data is especially applied to the memory element group.
By providing a data storage element and combining the contents stored in the protection data storage element with an external signal,
A blocking signal is generated. By designating an address storing the protection information, a gate signal is given to the latch circuit, and the protection information read from the storage element group through the sense amplifier is stored in the latch circuit. For example, the protection information is formed by a write or erase block signal and a keyword. The mismatch detection circuit compares the external signal of the keyword with the bit pattern of the keyword stored in the latch circuit. When they do not match, signal generation is prohibited, and when they match. Only generate a write or erase inhibit signal. As a result, it is possible to prevent each operation of writing or erasing the storage element group by the pattern of the data written in the specific area of the storage element.
In addition, since the protection information can be stored even in a recursive state, it is possible to realize a flexible write / erasable semiconductor memory device with a protection function.

[0006]

Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 12 is a basic configuration diagram of an electrically writable / erasable semiconductor memory device used in the present invention.
In FIG. 12, 1 is a memory element group and 2 is an address decoder.
3, 3 is a sense amplifier, and 4 is a write / erase voltage control circuit. Address input 6 to address decoder 2
1, the write data 66 is applied to the memory element group 1, and the write start signal 62 is applied to the write / erase voltage control circuit 4 to write data.
Further, by adding the address input 61 and the read start signal 64, the read data 65 can be obtained from the sense amplifier 3. Also, address 6 for address decoder 2
The contents are erased by adding the erase start signal 63 to the write erase voltage control circuit 4 and the erase start signal 63. FIG. 13 is an explanatory diagram of write and erase operations for the storage element of FIG. To rewrite the memory element group 1, as shown in FIG. 13, by supplying an address 61 and inputting an erase start signal 63, the memory element corresponding to the designated address is erased, and then the write start signal 62 and the write start signal 62 are written. By supplying the data 66, writing to the storage element is performed.

FIG. 14 is a circuit diagram of the write / erase voltage control circuit of FIG. The write / erase voltage control circuit 4 is
This is a circuit for applying a high voltage required for writing or erasing to each terminal of the memory element group 1, and as shown in FIG.
It is composed of a transistor (load transistor and on / off transistor), and turns on / off the output OUT by a write start signal 62 and an erase start signal 63. When the present invention is applied to the nonvolatile memory device configured as shown in FIG. 12, various embodiments can be considered. 1 (a)-
FIG. 3D is a configuration diagram of a semiconductor memory device showing a plurality of basic circuits according to the first embodiment of the present invention. First, FIG. 1 (a)
Shows the first basic configuration. That is,
With respect to the storage element group 1 arranged in a matrix, a storage element 1a for storing at least 1-bit memory protection information is arranged for each row in units of the storage element group in the column direction of the matrix, that is, the address direction. , The contents of the protection information storage element 1a are simultaneously read by a control signal designated in the column direction, and the read contents, for example, if it is '1', program (write), erase, or read operations are permitted as they are. , "0", the contents of the memory element group 1 are protected by blocking each of these operations. Next, FIG. 1B shows a matrix-shaped storage element group 1.
Of a part of the address, that is, at least one row in the column direction is set as a storage element 1b for storing protection information. First, the protection information storage element 1b is read out, and if the content is, for example, "1", the storage element group 1 Allows programming, erasing, and reading operations for, and if it is '0',
The contents of the memory element group 1 are protected by blocking these operations.

Next, FIG. 1C is a modification of FIG. 1B, in which at least one row in the column direction of the matrix is a storage element group 1b for storing storage protection information. 1
Same as (b), but in this case, each bit of one row is assigned to each row of the storage element group 1 as indicated by an arrow,
First, depending on the contents of the protection information storage element 1b read out,
For example, if the content of the 1st bit on the right side is '1', the programming, erasing, and reading operations in the lower row of the element group 1 are permitted, and if the content of the second bit from the right is '0', the element is Block each action in the second row from the bottom of group 1, 3 from the right
If the content of the second bit is "1", the contents of the storage element group 1 are protected for each row by permitting each operation of the third row from the bottom. Next, FIG.
(D) is a combination of the protection methods of FIGS. 1 (a) and 1 (b). Half of the matrix in the column direction, that is, half of the address, protects the stored contents by the former protection method. The other half protects the stored contents by the latter protection method.
That is, the element group 1a for storing at least 1-bit protection information is arranged in each row in the storage element group 1A, and the protection information is stored in at least one row in the remaining storage element group 1B. The memory element group 1b is arranged to protect the memory contents with the respective memory protection information according to the selected address. Hereinafter, the operation will be described in detail with reference to examples in the case of FIG. 1A and the case of FIG. In the case of FIGS. 1C and 1D, (a) and (b)
Since this is an application of the operation of, the detailed description of the operation will be omitted.

FIG. 2 is a block diagram of a semiconductor memory device showing the first embodiment. In this embodiment, various protection functions can be given to each small unit of memory. In FIG. 2, reference numeral 31 is an address decorator.
37, a temporary storage register of protection information, 39 an internal control circuit, 41 an address bus, 42 a data bus, 32
1 to 328 are high voltage control circuits, 341 and 342 are sense amplifiers, 351 and 352 are output drivers, 151 and 15
Reference numerals 2, 155 and 156 are transistors that form a memory element, and 153 and 154 are transistors that turn on and off the gate voltage of the memory element. In the conventional semiconductor memory device,
Only the left half of FIG. 2, that is, the address decoder 31, the data
Only the data memory matrices 151 and 155, the data reading sense amplifier 341, the output driver 351, and the high voltage control circuits 321 to 326 and 328 are provided. FIG. 3 is a voltage relationship diagram for the storage element at the time of memory access in FIG. The voltage condition of FIG.
By giving it to 55, read, program, and erase operations are performed. That is, in the case of a read operation, a voltage of Vcc is applied to the word line (W) 21 by the address decoder 31, and a voltage of Vcc is similarly applied to the high voltage word line (WH) 221 by the high voltage control circuit 321. In addition, the voltage of -Vpp is applied from the high voltage control circuit 323 to the well 111 and the well voltage is set to Vcc, whereby the contents of the selected memory element can be erased.

In the present embodiment, the configuration on the right side of FIG. 2 is added to the above-described conventional configuration. That is, one or a plurality of storage elements 152 and 156 for storing protection information are arranged in each word line 221, and access to the data memory is permitted depending on the state of the protection information memory corresponding to the designated address. , Or the function to prohibit is added. As a circuit added for this purpose, a control gate 1 for turning on / off the supply of the gate voltage of the memory element is provided.
53 and 154, a sense information sense amplifier 342, a protection information output driver 352, and a temporary storage register 37. In the present embodiment, a memory for storing memory protection data in units of a series of memory element groups (151, 155, etc.) selected by word lines is arranged on one side of the memory element groups arranged in an array. By disposing the elements 152 and 156, the memory elements 152 and 156 can be read at the same time when the word line is selected to prevent the control of programming, erasing and reading. Storage element 15 for storing protection information
2, 156 can be read, programmed, and erased in the same manner as the conventional data memories 151, 155. However, when the data memories 151 and 155 are programmed and erased, the protection information elements 151 and 1
55 must not lose the stored information. For this reason,
It is necessary to give different conditions to the protected information storage elements 152 and 156 during the programming and erasing operations of the data memories 151 and 155.

FIG. 4 is a voltage relationship diagram for preventing each operation of programming and erasing the protection storage element of FIG. At the time of data programming, as shown in FIG. 3, Vcc is applied to the word line (W) 21, and high voltage word line (WH) 221.
To Vcc, data read line (D) 231 to -Vpp, I line 2
5, -Vpp is applied to the WELL line 111, and -Vp is applied to the WELL line 111. On the other hand, in the protected information storage element, as shown in FIG. Like the data, Vcc and -Vpp are applied to the I line 25 as well as the data, but 0 voltage is applied to the WH line, the D line and the WELL line. This allows the protection information to be programmed. Also, at the time of erasing, WH line, D line, S line, and WELL
Do not erase the protected information by applying 0 voltage to the line. The gates 153 and 154 and the high voltage inverter 361 shown in FIG. 2 are circuits that apply the voltage conditions shown in FIG. 4 in order to prevent the destruction of the protection information. Next, the operations of the read, program, and erase operations having the protection function will be described in detail.

FIG. 5 is a timing chart during the read operation in FIG. When the chip select signal 43 and the address 41 are given, the memory device starts its operation.
The word line 21 corresponding to the designated address is selected, and the contents of the data memory element 151 and the protection information memory element 152 are read by the sense amplifiers 341 and 342, respectively. The output of the sense amplifier 342 is set in the temporary storage register 37. When the output 47 is "1", the output driver 351 for the data memory is driven to read the data on the data bus 42. put out. Further, when the protection information output 47 is "0", the data memory output driver 351 is controlled to prohibit the output from the driver 351 so that the data is not transmitted to the data bus 42. To do. In the case of reading, since the data memory 151 and the protection information element 152 are read simultaneously, the addition of the protection function does not cause a delay in the operation time.

FIG. 6 is a time chart at the time of programming or erasing in FIG. Also in this case, as in the read operation, the chip selection signal 43 and the address 41
Is given to start the operation. The internal control circuit 39 first reads the control mode to the read state (ST
1), the protection information storage element 1 for a specified address
52 is read out and stored in the temporary storage register 37. When the output 47 is "1", the internal control state of the internal control circuit 39 is shifted to the program or erase mode (ST2). In each of the high voltage generation times 321 to 325, the high voltage shown in FIG. 3 is generated during the erase mode (ST2) to perform the program or erase operation. At the same time, the high voltage generation circuit 3
The signal line 49 connected to 26 becomes "0" level, which turns off the gate 153, and the gates 362-36.
Set the output of 4 to 0V. Since the output 491 of the inverter 361 becomes "1", the gate 154 is turned on, the gate 154 of the protection information storage element 152 is turned on, and the gate voltage 222 of the protection information storage element 152 is turned on. To 0V. As a result, the voltage relationship to the protection information storage elements 152 and 156 satisfies the condition shown in FIG. 4, and the data memories 151 and 1
The stored information in the protected information storage elements 152 and 156 is protected during the program or erase operation to 55. During the program and erase operations, the protection information is read and the data is deleted.
The programming and erasing operations are executed in time series, but the programming and erasing times are 10 ³ to 10 times as long as the reading time.
Since it is 10 ⁵ times longer, there is no substantial increase in access operation due to reading of the protection information.

As described above, in this embodiment, the memory matrix for data and the memory matrix for protection information are arranged on the common word line, and at the time of read operation, both are simultaneously accessed and protected. It is possible to control the sending of read data to the data line by the information, and at the time of the program and erase operations, first read the protection information and control the program and erase operations by this information.
As a result, memory protection in word line units can be realized without the help of software, and an increase in access time for memory protection can be eliminated. Moreover, since the memory protection can be performed in units of word lines, it is possible to protect the memory area without waste. Further, in this embodiment, the control circuit of the address decoder 31 and the word line 21 can be shared by the data memory matrix and the protection information line memory matrix, so that an area for realizing the protection function is provided. The increase above can also be minimized.

FIG. 7 is a block diagram of a semiconductor memory device showing a second embodiment of the present invention. The same symbols as those in FIG. 12 represent the same components. The semiconductor memory device shown in FIG.
An address determination circuit 51, a write blocking data latch circuit 52, and an erase blocking data latch circuit 53 are added to the circuit configuration of No. 2 for each blocking signal 671 and 672.
The write inhibit signal 671 is activated by the read data in the written state, and the erase inhibit signal 672 is activated by the read data in the erased state. FIG. 8 is an explanatory diagram showing the relationship between the protection data and the blocking condition of FIG. As shown in FIG. 8, if the read signal in the written state is "1" and the read signal in the erased state is "0",
In the latch circuit 52, the write blocking signal is disabled when the read data is "0", and when the read data is "1",
The write inhibit signal becomes active. In the latch circuit 53, the erase block signal is active when the read data is "0", and the erase block signal is disable when the read data is "1". Next, a method of testing the protection function of the storage device and a method of setting the non-recursive protection function will be described. First, when the address in which the protection information is stored is designated by the address signal 61, the address determination circuit 5
1 judges the registration of this, the latch circuit 52,
A gate signal is applied to 53, and data "1" or "0" is read from the storage element group 1 through the sense amplifier 3. In the initial state, the data is fixed to either "1" or "0" depending on the method of manufacturing the semiconductor device. For example, in the case of the state of “1”, FIG.
According to the condition (1), the write inhibit signal is active and the erase inhibit signal is disabled. Therefore, the storage element can be erased from "1" to "0", that is, erased, by designating a general data protection area other than the protection information storage address.

Furthermore, it is possible to test whether or not the protection function operates by writing the write start from "0" to "1". The erase and write blocking operations can be tested for all storage elements including the protection information storage area without changing the state of the protection function. Next, in the erased state of the protected information area, when this address is designated and read activation is performed, "0" is read to the latch circuits 52 and 53, and the erase inhibit signal is active and the write inhibit signal is in the disable state. .. In this state, as described above, the erase prevention operation can be tested for all storage elements. Next, data is set in the protected information area so that "0" is read by the latch circuit 52 and "1" is read by the latch circuit 53, and this is read. In this state, the storage element group 1 operates as an electrically writable / erasable nonvolatile storage element having no protection function. Conversely, when data is set in the protected information area so that "1" and "0" are read into the latch circuits 52 and 53, respectively, and this is read, this memory device has a write / erase function. Both are blocked, and it is impossible to return from that state to the state in which the write / erase function is activated.
As a result, the data stored in the storage element group 1 will not be destroyed thereafter.

FIG. 9 is a block diagram of a semiconductor memory device showing a third embodiment of the present invention, and FIG.
It is a detailed block diagram of an erase control circuit. In the device of FIG. 9, the write / erase function blocking area and the write function only area or the area blocking only the erase function are separated on the same memory element group. That is, in FIG. 9, compared with FIG. 7, the write block data latch circuits 521, 52
2. The difference is that two sets of erasure prevention data latch circuits 531 and 532 are provided. The write / erase control circuit 4, as shown in FIG.
12, 6721, 6722, and the high voltage Vp is controlled by the write start signal 62 and the erase start signal 63 from the outside,
The outputs 681 to 684 are used as the two areas 11 of the storage element group.
And give to 12. If the protection information storage area is in the area 11, for example, the storage element group 11 can realize the non-recursive write / erase prevention area as described above. Further, by setting the data corresponding to the protection information latch circuits 522 and 532 to the write-inhibit or erase-inhibit state, and setting the region 11 in the non-recursive write / erase-inhibited state, the region 1
With respect to 2, it is possible to specify the write-inhibited state and the erase-inhibited state in a non-recursive form according to the designation of the protection information.
If the memory element area is further divided and a protection information latch circuit is prepared corresponding to the area to configure a write / erase control circuit, different protection conditions can be specified for each area.

FIG. 11 is a block diagram of a semiconductor memory device showing a fourth embodiment of the present invention. FIG. 11 shows a configuration in which the blocking signal is generated by combining the protection information and the external signal. In FIG. 11, 51
Is an address determination circuit, 54 is a protection information latch circuit, 55
Is a combinational circuit, and 69 is an external signal. The other signals are the same as those in FIGS. 7 and 9. For example, if a mismatch detection circuit for the output of the latch circuit 54 and the external signal 69 is used as the combination circuit 55, a keyword detection type protection function can be realized. When the address in which the protection information is stored is designated by the address signal 61, the address determination circuit 51 determines the address, a gate signal is given to the latch circuit 54, and the storage element group 1 passes through the sense amplifier 3. Then, the read protection information is stored in the latch circuit 54. For example, this protection information is composed of the writing or erasing prevention information and the keyword shown in FIG. An external signal 69 of the keyword in the mismatch detection circuit 55.
Is compared with the key word output bit pattern stored in the latch circuit 54, and when they do not match, the generation of 671 and 672 signals is prohibited and they match. Only at this time, the write or erase block signal is generated according to FIG.

As described above, in the embodiments shown in FIGS. 7, 9 and 11, the pattern of data written in a specific area of the electrically writable / erasable memory element group is used. Since the write or erase operation of the memory element group can be prevented and this protection information can be stored even in a recursive state, it is possible to electrically write / erase with a flexible protection function. A semiconductor memory device can be realized.

[0020]

As described above, according to the present invention,
Since various protection functions of the memory can be realized in a small unit, and the pattern of data written in a specific area can prevent the writing or erasing operation of the memory element group, It is possible to protect the memory area without waste.

[0021]

[Brief description of drawings]

FIG. 1 is a configuration diagram of a semiconductor memory device showing the basic principle of the present invention.

FIG. 2 is a configuration diagram of a semiconductor memory device showing a first embodiment of the present invention.

FIG. 3 is a voltage relation diagram when programming and erasing the data storage element of FIG.

FIG. 4 is a voltage relationship diagram in the case of blocking programming and erasing operations for the protection information storage element.

5 is a time chart of the read operation in FIG.

FIG. 6 is a time chart during a program or erase operation of FIG.

FIG. 7 is a configuration diagram of a semiconductor memory device showing a second embodiment of the present invention.

8 is an explanatory diagram showing the relationship between the protection data and the blocking condition of FIG.

FIG. 9 is a configuration diagram of a semiconductor memory device showing a third embodiment of the present invention.

10 is a configuration diagram of a write / erase voltage control circuit in FIG.

FIG. 11 is a configuration diagram of a semiconductor memory device showing a fourth embodiment of the present invention.

FIG. 12 is a configuration diagram of a conventional semiconductor memory device having no memory protection.

13 is an explanatory diagram of erase and write operations in FIG. 12;

14 is a configuration diagram of a write / erase voltage control circuit in FIG.

[Explanation of symbols]

 1 Nonvolatile Memory Element Group 2 Address Decoder 4 Program / Erase Voltage Control Circuit 31 Address Decoder 37 Temporary Storage Register of Protection Information 39 Internal Control Circuit 51 Address Detection Circuit 52, 53 Protection Information Latch Circuit 61 Address Input 62 Write Start signal 63 Erase start signal 64 Read start signal 65 Read data line 66 Write data line 151, 155 Data memory device 152, 156 Protected information storage memory device 341, 342 Sense amplifier 351, 352 Output driver 321 to 328 High voltage control circuit 153,154 Control gate

Claims (7)

[Claims] 1. A plurality of storage element groups arranged in a matrix, a protection data storage element for storing at least 1-bit memory protection information arranged in the matrix, and a designated address in the matrix. It comprises a first means for accessing a selected one storage element of a plurality of storage element groups in accordance with a signal, and a second means for reading the contents of the protection data storage element. The means determines whether to permit or prohibit each of the programming (writing), erasing or reading operations for the selected one storage element according to the contents of the protection data storage element, and The first means accesses the selected one storage element and the protection data storage element via a common word line, and the storage element group and the protection data storage element are electrically connected to each other. A semiconductor memory device comprising a rewritable memory element. 2. The semiconductor memory device according to claim 1, wherein said first means selects one selected memory element when reading out one selected memory element and a protection data memory element. With respect to the above, a semiconductor memory device characterized in that both the one memory element and the protection data memory element are simultaneously accessed. 3. The semiconductor memory device according to claim 1, wherein the first means selects one operation of programming (writing) or erasing when accessing one selected memory element. A semiconductor memory device characterized in that a protection data memory element is accessed with priority over a memory element. 4. The semiconductor memory device according to claim 1, wherein the memory element, the first means and the second means are built in a cache card. 5. The semiconductor memory device according to claim 1, wherein, in addition to the memory element, the first means, and the second means, the contents of the protection data memory element and the contents of the microcomputer. A semiconductor memory device comprising: a third means for generating an inhibition signal according to the content of an external signal input from the outside. 6. The semiconductor memory device according to claim 5, wherein the external signal is a signal for keyword detection, and the third means comprises a mismatch detection circuit. A characteristic semiconductor memory device. 7. The semiconductor memory device according to claim 1, wherein the memory element, the first means, and the second means are built in a microcomputer.