JP2842442B2 - Microcomputer, nonvolatile semiconductor memory device, and method for writing and erasing the same - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile semiconductor memory device that can be protected in word line units, a method for writing and erasing the same, and a microprocessor incorporating the nonvolatile semiconductor memory device. , Relating to cash cards. [Background of the Invention] Conventionally, EEPROM (Electrically Erasable and Prog
A rammable read only memory (NRAM) is a non-volatile memory and electrically rewritable. On the contrary, there is a concern that data to be protected may be rewritten. Therefore, as a method of protecting the secrecy of data in a nonvolatile memory, there has been proposed a method of using security bits and prohibiting access from outside the memory according to the state of the bits (for example, “Electronics Design” (Electronics)). Design), March 3,1983, pp123
~ 128). That is, a write-only security register separate from the memory block for the purpose of ordinary rewriting is prepared, and access to the memory block is prohibited depending on the state of a specific bit of this register. In this case, as a method of configuring the security register with a rewritable memory element, the erasing operation of the security register is made possible only when the entire erasing operation of the memory block is performed. Is written in the security register so that the memory block cannot be accessed without destroying the data in the memory block. However, in this method, while allowing reading of the memory, 1
No consideration has been given to a protection function for preventing rewriting of previously written data. In addition, since the conditions for erasing and writing of the nonvolatile memory constituting the security register are different from those of the data storage area, it is necessary to provide an independent erasing and writing circuit, and the circuit tends to be complicated. In addition, since the above method is a protection function that operates on the entire memory as a unit, it is not possible to control the protection data in each area by dividing the memory into partial and small capacities. As another memory protection method conventionally known,
There is a method to specify the area and the contents of protection by software. However, this method requires another storage device for storing these and system software for controlling the storage device, so that the scale becomes large, and a nonvolatile memory or the like having a relatively small memory capacity is required. Not suitable for data protection. For example, in a microcomputer applied to a cache card or the like and having a built-in non-volatile memory, there is a demand that the non-volatile memory be divided into areas for various different uses such as a program storage area, an ID code, and data. There is. In this case, it is very important to be able to prevent functions such as reading and program erasing for each area divided into small areas in order to realize a highly reliable system. [Object of the Invention] An object of the present invention is to solve these conventional problems and to provide a nonvolatile semiconductor memory element having a protection function such as write / erase permission prohibition for a word line unit nonvolatile semiconductor memory element. Device, nonvolatile semiconductor memory device capable of setting conditions for preventing write / erase only by storing protection data in the same word line, and nonvolatile semiconductor memory capable of memory protection in word line units An object of the present invention is to provide a microprocessor and a cash card having a built-in device. [Summary of the Invention] A microprocessor of the present invention is a microprocessor having a built-in nonvolatile semiconductor memory device arranged on the same semiconductor chip, and the nonvolatile semiconductor memory device is arranged on the semiconductor chip. A protection data storage element is provided in addition to a data storage element on a word line, and a voltage control circuit is controlled by an output of the protection data storage element read out simultaneously with normal data to perform writing or erasing of the nonvolatile semiconductor memory device. For this purpose, a voltage specified for the purpose is controlled (claim 1). Further, a write inhibit signal or an erase inhibit signal is output to the protected data storage element in accordance with the contents of the protected data storage element. Further, the present invention is a cash card incorporating the microcomputer as described above (claim 3). Further, according to the writing method of the nonvolatile semiconductor memory device of the present invention, a voltage for controlling the data storage element and the protected data storage element is generated based on the content of the protected data storage element read simultaneously with the normal data, and the write or write operation is performed. This is a writing method in which writing or erasing is performed on these storage elements when erasing is permitted (claim 4). Further, in the method, only writing or erasing is performed when the content of the protected data storage element permits only writing or erasing (claims 5 and 6). Further, the nonvolatile semiconductor memory device of the present invention has the above-mentioned means for writing and erasing (claim 7). According to the present invention, a compact nonvolatile semiconductor memory device having a configuration for protection on the same semiconductor chip and a microprocessor and a cache card having the same can be obtained by the above-described configuration. Four
In this method, it is possible to obtain a remarkable operation and effect that once the one-word data and the corresponding protection data are written, it is impossible to change the storage contents (recursion impossible). . Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 12 is a basic configuration diagram of an electrically writable / erasable semiconductor memory device used in the present invention. In FIG. 12, 1 is a storage element group, 2 is an address decoder, 3 is a sense amplifier, and 4 is a write / erase voltage control circuit. Address input 61 to address decoder 2,
Data is written by applying write data 66 to the memory element group 1 and a write drive signal 62 to the write / erase voltage control circuit 4, and an address input 61 and a read start signal 64 are applied. Thus, read data 65 is obtained from sense amplifier 3. The contents are erased by applying an address 61 to the address decoder 2 and an erase start signal 63 to the write / erase voltage control circuit 4, respectively. FIG. 13 is an explanatory diagram of the write and erase operations for the storage element of FIG. As shown in FIG. 13, the memory element group 1 is rewritten by giving an address 61 and inputting an erase activation signal 63 to erase the storage element corresponding to the designated address. And write data 66, writing to the storage element is performed. FIG. 14 is a circuit diagram of the write / erase voltage control circuit of FIG. The write / erase voltage control circuit 4 is a circuit for applying a high voltage necessary for writing or erasing to each terminal of the storage element group 1 and, as shown in FIG. 14, from a MOS transistor (a load transistor and an on / off transistor). Composed,
The output OUT is turned on / off by the write start signal 62 and the erase start signal 63. Various modifications may be made to the nonvolatile semiconductor memory device having the configuration shown in FIG. FIG. 1A is a basic configuration diagram of the present invention, and FIGS. 1B to 1D show modified examples thereof. First, FIG. 1 (a) shows a basic configuration of the first invention, and shows a storage element group 1 arranged in a matrix.
In contrast, a storage element 1a for storing at least one bit of memory protection information is arranged for each row in units of storage elements in the matrix direction, that is, in the address direction, and protected by a control signal designated in the column direction. The contents of the information storage element 1a are simultaneously read, and the read contents, for example, if "1", each operation of programming (writing), erasing, or reading is permitted as it is, and if "0", each of these operations is allowed. In order to protect the contents of the storage element group 1. Next, FIG. 1 (b) shows a matrix-like storage element group 1
A part of the address, that is, at least one row in the column direction is a storage element 1b for storing protection information. First, the protection information storage element 1b is read out, and if the content is, for example, "1", the storage element group The program, erase, and read operations for 1 are permitted, and if "0", these operations are blocked, thereby protecting the contents of the memory block group 1. Next, FIG. 1 (c) shows a modification of FIG. 1 (b), wherein at least one row in the column direction of the matrix is a storage element group 1b for storing storage protection information. This is the same as FIG. 2B, but in this case, each bit of one row is allocated to each row of the storage element group 1 as shown by an arrow.
First, according to the content of the read protection information storage element 1b, for example, if the content of one bit on the right side is "1", the respective operations of programming, erasing, and reading of the bottom row of the element group 1 are permitted.
If the content of the second bit from the right is “0”, the element group 1
Block the operation of the second row from the bottom, and if the content of the third bit from the right is "1", permit the operation of the third row from the bottom to enable the storage element. The contents of the group 1 are protected for each line. Next, FIG. 1 (d) shows a combination of both the protection methods of FIGS. 1 (a) and 1 (b). Half of the matrix in the column direction, that is, half of the address, is stored in the former protection method. The other half is to protect the stored contents by the latter protection method. That is, the element group that stores at least one bit of protection information for each row is stored in the storage element group 1A.
1a, and a storage element group 1b storing protection information in at least one row is arranged in the remaining storage element group 1B,
The memory contents are protected by the respective memory protection information according to the selected address. Hereinafter, the operation in the case of FIG. 1A and the case of FIG. 1B will be described in detail with reference to examples. In addition,
The cases of FIGS. 1C and 1D are applications of the operations of FIGS. 1A and 1B, and therefore detailed operations are omitted. FIG. 2 is a configuration diagram of a semiconductor memory device showing an embodiment of the first invention, showing a case where various protection functions can be provided for each small unit of memory. In FIG. 2, 31 is an address decoder, 37 is a temporary storage register for protection information, 39 is an internal control circuit, 41 is an address bus, 42 is a data bus, 321 to 238 are high voltage control circuits,
341,342 are sense amplifiers, 351,352 are output drivers, 151,
152, 155, 156 are transistors constituting a storage element, 153, 1
A transistor 54 turns on and off the gate voltage of the storage element. In the conventional semiconductor memory device, only the left half of FIG. 2, that is, only the address decoder 31, the data memory matrices 151 and 155, the data read sense amplifier 341, the output driver 351, and the high voltage control circuits 321 to 326 and 328 are provided. . FIG. 3 is a diagram showing a voltage relation to a storage element at the time of memory access in FIG. By applying the voltage condition shown in FIG. 3 to the storage elements 151 and 155, each operation of reading, programming, and erasing is performed. That is, in the case of read operation, a voltage of V _CC added by the address decoder 31 to the word line (W) 21, a high pressure word line 221 by 0 ^V, and selecting a storage element, the contents of the elements (D _OUT ) is read out to the data line 231. In the case of a program, the word line (W) 21
To a voltage of V _CC added from the address decoder 31, also the voltage of V _CC added than the high voltage control circuit 321 to the high voltage word line (WH) 221, by adding -V _PP than the high voltage control circuit 323 to the well 111 "1" can be written to the selected storage element. Further, in the case of erasing, a voltage of V _CC is applied from the address decoder 31 to the word line (W) 21,
By applying a voltage of −V _PP from the high voltage control circuit 321 to the high voltage word line 221 and setting the well voltage to V _CC , the contents of the selected storage element can be erased. In the present invention, a configuration on the right side of FIG. 2 is added to the above-described conventional configuration. That is, a function of arranging one or a plurality of storage elements 152 and 156 for storing protection information in each word line 221 and permitting or prohibiting access to the data memory depending on the state of the protection information memory corresponding to the designated address. Is added. Circuits added for this purpose include control gates 153 and 154 for turning on / off the supply of the gate voltage of the storage element, a sense amplifier 342 for protection information, an output driver 352 for protection information, and a temporary storage register 37. According to the present invention, a series of storage element groups (151, 155) selected by a word line is provided on one side of the storage element groups arranged in an array.
Storage element that stores memory protection data in units of
152, 156, and when the word line is selected,
56 can be read at the same time to prevent control of programming, erasing, and reading. The storage elements 152 and 156 that store the protection information include a read program, like the conventional data memories 151 and 155.
And erasure is possible. However, the data memory 151,
During a program or erase operation on 155, the protected information elements 152 and 156 must not lose stored information. For this reason, it is necessary to give different conditions to the protection information storage elements 152 and 156 during the operation of programming and erasing the data memories 151 and 155. FIG. 4 is a voltage relationship diagram for preventing each operation of programming and erasing the protection storage element of FIG. When data of a program, as in the FIG. 3, V _CC to the word line (W) 21, a high pressure word line (WH) 221 to V _CC, the data read lines (D) 231 -V _PP, the I line 25 - V _PP, the -V _P to WELL line 111, while the added respectively, to the protection information storage device, as shown in FIG. 4, for program inhibition,
Word lines (W) 21 to the data and also V _CC, also added -V _PP data in I-line 25, but in WH line and D-line and WELL line, applying 0 voltage. This saves the protection information from being programmed. Also, at the time of erasure, the protection information is not erased by applying 0 voltage to the WH line, the D line, the S line, and the WELL line. The gates 153 and 154 and the voltage inverter 361 in FIG. 2 are circuits that provide the voltage conditions shown in FIG. 4 in order to prevent the protection information from being destroyed. Next, the read, program, and erase operations having a protection function will be described in detail. FIG. 5 is a timing chart at the time of the read operation in FIG. Chitsupuserekuto signal 43, the address 4 ¹ is given,
The storage device starts operating. The word line 21 corresponding to the specified address is selected, and the contents of the data memory element 151 and the protection information storage element 152 are stored in the sense amplifier 3 respectively.
Read by 41,342. The output of the sense amplifier 342 is
When the output 47 is set to the temporary storage register 37 and the output 47 is "1", the output driver 351 for the data memory is driven to read data onto the data bus 42. When the output 47 of the protection information is “0”, the output driver for the data memory is used.
By controlling the 351, output from the driver 351 is prohibited, and data is not sent to the data bus 42. In the case of a read operation, the data memory 151 and the protection information element 152 are read at the same time, so that the addition of the protection function does not cause a delay in the operation time. FIG. 6 is a time chart at the time of programming or erasing in FIG. In this case as well, the operation starts when the chip select signal 43 and the address 41 are applied, as in the read operation. First, the internal control circuit 39 sets the control mode to the read state (ST1), reads the protection information storage element 152 corresponding to the designated address, and stores it in the temporary storage register 37. When the output 47 is "1", the internal control state of the internal control circuit 39 is set to the program or erase mode (ST2).
Transfer to Each of the high voltage generation circuits 321 to 325 generates a high voltage shown in FIG. 3 during the erase mode (ST2), and performs a program or erase operation. At the same time, the high voltage generator 32
The signal line 49 connected to 6 goes to the "0" level, thereby turning off the gate 153 and turning the outputs of the gates 362 to 364 to 0V.
To Further, since the output 491 of the inverter 361 becomes “1”, the gate 154 is turned on, and the gate voltage 222 of the protection information storage element 152 is set to 0V. As a result, the protected information storage elements 152,1
The voltage relation to 56 satisfies FIG. 4, and when programming or erasing the data memories 151 and 155,
The information stored in the protected information storage elements 152 and 156 is protected. During the programming and erasing operations, the protection information reading and the data programming and erasing operations are performed in chronological order, but the program and erasing times are longer than the reading time.
Since the length is 10 ³ to 10 ⁵ times longer, a substantial increase in access operation due to reading of the protection information does not occur. As described above, in the present embodiment, the memory matrix for data and the memory matrix for protection information are arranged on a common word line, and at the time of a read operation, both are accessed simultaneously, and the read data is read based on the protection information. At the time of programming and erasing operations, first, protection information is read out, and the programming and erasing operations can be controlled by this information. As a result,
Memory protection in word line units can be realized without the aid of software, and an increase in access time for memory protection can be eliminated. Further, since memory protection can be performed in word line units, it is possible to protect the memory without wasting the memory area. Further, in the present embodiment, the control circuit for the address decoder 31 and the word line 21 can be shared by the data memory matrix and the protection information reading memory matrix, so that an increase in area when implementing the protection function is minimized. FIG. 7 is a configuration diagram of a semiconductor memory device showing an embodiment of the second invention. The same symbols as those in FIG. 12 represent the same ones. The semiconductor memory device of FIG. 7 is different from the circuit configuration of FIG.
An address determination circuit 51, a write-inhibit data latch circuit 52, and an erase-inhibit data latch circuit 53 are added.
For 2, the setting is made so that the write inhibit signal 671 is activated by the read data in the write state, and the erase inhibit signal 672 is activated by the read data in the erase state. FIG. 8 is an explanatory diagram showing the relationship between protected data and a blocking condition in FIG. 7; As shown in FIG. 8, when the read signal in the write state is "1" and the read signal in the erase state is "0", the latch circuit 52 disables the write inhibit signal when the read data is "0". When the read data is "1", the write inhibit signal becomes active. In the latch circuit 53, when the read data is "0", the erasure prevention signal is active, and when the read data is "1", the erasure prevention signal is disabled. Next, a method of testing the protection function of the storage device and setting the non-recursive protection function will be described. First, when the address where the protection information is stored is specified by the address signal 61, the address determination circuit 51 registers and determines this, whereby gate signals are given to the latch circuits 52 and 53, and the storage element group 1 , The data “1” or “0” is read out via the sense amplifier 3. In the initial state, data is fixed to either “1” or “0” depending on the manufacturing method of the semiconductor element. For example,
In the state of "1", the write inhibit signal is active and the erase inhibit signal is disabled from the condition shown in FIG. Accordingly, the storage element can be changed from "1" to "0", that is, erased, by designating a general data protection area other than the protection information storage address. Furthermore, it is possible to test whether or not the protection function operates by writing and starting from “0” to “1”. The test of the erasure and writing prevention operations can be performed on all storage elements including the protection information storage area without changing the state of the protection function. Next, when the protection information area is in the erased state and this address is designated and read-out is started, "0" is set in the latch circuits 52 and 53.
Is read, and the erase inhibition signal is activated and the write inhibition signal is disabled. In this state, as described above, the erase prevention operation can be tested for all the storage elements. Next, data is set in the protection information area so that "0" is read out by the latch circuit 52 and "1" is read out by the latch circuit 53, and this is read. In this state, the storage element group 1 operates as an electrically writable / erasable nonvolatile storage element having no protection function. Conversely, data is set in the protection information area so that "1" and "0" are read out by the latch circuits 52 and 53, respectively, and when this is read out, both the write and erase functions of this storage device are blocked. This makes it impossible to return to the state where the write / erase function is activated from that state. As a result, the data stored in the storage element group 1 is thereafter
It will not be destroyed. FIG. 9 is a configuration diagram of a semiconductor memory device showing another embodiment of the present invention, and FIG. 10 is a detailed configuration diagram of the write / erase control circuit of FIG. In the apparatus shown in FIG. 9, the block area for the write / erase function and the area for blocking only the write function or only the erase function are separated on the same storage element group. That is, in FIG. 9, the write-inhibit data latch circuits 521 and 522 and the erase-inhibit data latch circuit 53 are different from FIG.
They differ in that two sets of 1,532 are provided. As shown in FIG. 10, the write / erase control circuit 4
6711,6712,6721,6722 and external write start signal 62,
The high voltage _VP is controlled by the erase start signal 63, and this output 68
1 to 684 are given to two areas 11 and 12 of the storage element group.
If the protection information storage area is, for example, in the area 11, the storage element group 11 can realize a non-recursive write / erase prevention area as described above. Also, latch circuits 522 and 53 for protecting information are provided.
By setting the data corresponding to 2 to write-protection or erase-protection, and setting the area 11 to the non-recursive write / erase-prevention state, the area 12 is prevented from writing according to the protection information specification. The erasure prevention state can be specified in a non-recursive manner. If the storage element area is further divided and a protection information latch circuit is prepared corresponding to the area and a write / erase control circuit is configured, different protection conditions can be designated for each area. FIG. 11 is a configuration diagram of a semiconductor memory device showing another embodiment of the present invention. FIG. 11 shows a configuration in which a blocking signal is generated by a combination of protection information and an external signal. 54 is a protection information latch circuit, 55 is a combination circuit, and 69 is an external signal. The other signals are the same as in FIGS. 7 and 9. For example, when a mismatch detection circuit between the output of the latch circuit 54 and the external signal 69 is used as the combination circuit 55, a keyword detection type protection function can be realized. When the address where the protection information is stored is designated by the address signal 61, the address determination circuit 51 determines this by
A gate signal is applied to the latch circuit 54, and the read protection information is stored in the latch circuit 54 from the storage element group 1 via the sense amplifier 3. For example, the protection information is composed of the write or erase prevention information and the keyword shown in FIG. External signal of keyword in mismatch detection circuit 55
The keyword given at 69 is compared with the output bit pattern of the keyword stored in the latch circuit 54, and when they do not match, the generation of the 671,672 signal is prohibited. An erasure prevention signal is generated. As described above, in the embodiments shown in FIGS. 7, 9 and 11, the storage element is controlled by the pattern of data written in a specific area of the electrically erasable / erasable storage element group. Since a write or erase operation of a group can be prevented and this protection information can be stored even in a recursive state, an electrically writable and erasable semiconductor memory device having a flexible protection function can be provided. Can be realized. Also, as is clear from the description in the section of [Background of the Invention], when a nonvolatile semiconductor memory is built in a microprocessor, a memory card, or the like, if the nonvolatile semiconductor memory as in the present invention described above is built, the Protection can be performed in word line units, and program erasure and the like can be completely prevented. [Effects of the Invention] As described above, according to the present invention, various protection functions of a memory can be realized in small units, and a storage element group can be realized by a pattern of data written in a specific area. Can be prevented from being written or erased, so that the memory area can be protected without waste.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a basic configuration diagram of the present invention, FIG. 2 is a configuration diagram of a semiconductor memory device showing one embodiment of the present invention, and FIG. 3 is a data storage element of FIG. FIG. 4 is a voltage relation diagram when programming and erasing are performed, FIG. 4 is a voltage relation diagram when programming and erasing operations to the protection information storage element shown in FIG. 1 are prevented, and FIG. 5 is a reading operation shown in FIG. The time chart of FIG.
Time chart at the time of program or erase operation in the figure,
FIG. 7 is a block diagram of a semiconductor memory device showing one embodiment of the present invention, FIG. 8 is an explanatory diagram showing the relationship between protected data and blocking conditions in FIG. 7, and FIGS. 9 and 10 are diagrams of the present invention. FIG. 11 is a configuration diagram of a semiconductor memory device and a write / erase voltage control circuit showing another embodiment, FIG. 11 is a configuration diagram of a semiconductor memory device showing still another embodiment of the present invention, and FIG. 13 and 14 are explanatory diagrams of the erasing and writing operations of FIG. 12 and a configuration diagram of a writing and erasing voltage control circuit. 31: address decoder, 37: protection information temporary storage register, 39: internal control circuit, 151, 155: data memory element, 1
52,156: Memory element for storing protection information, 341,342: Sense amplifier, 351,352: Output driver, 321 to 328: High voltage control circuit, 153,154: Control gate, 1: Non-volatile memory element group, 2: Address decoder, 4: Write / write Erase voltage control circuit, 51: address detection circuit, 52, 53: protection information latch circuit, 61: address input, 62: write start signal, 63: erase start signal, 64:
Read start signal, 65: read data line, 66: write data line.

Claims (1)

(57) [Claims] A microcomputer incorporating a nonvolatile semiconductor memory device, wherein the nonvolatile semiconductor memory device includes a plurality of word lines, data lines, and electrically writable and erasable storage elements, and is arranged in a matrix. A memory element group, an address decoder for selecting one of the plurality of word lines according to an address signal, and a voltage control circuit for outputting a voltage for writing or erasing; A data storage element for storing normal information and a protected data storage element for storing memory protection information are electrically connected and erasable, and the data storage element is connected to the data storage element by a word line selected by the address decoder. Reads both information from the protected data storage element and permits writing or erasing to the read data storage element Whether to perform or prohibit is performed by controlling the voltage control circuit according to the read information of the protected data storage element, and when the information is written or erased in the data storage element, the protection is performed. A microcomputer wherein writing or erasing of information to a data storage element is prevented. 2. 2. The microcomputer according to claim 1, wherein said voltage control circuit outputs a write inhibit signal or an erase inhibit signal to said protected data storage element in accordance with information of said protected data storage element. 3. A cash card comprising the microcomputer according to claim 1 or 2. 4. A storage element group composed of electrically erasable storage elements and arranged in a matrix, and a storage element group composed of electrically erasable storage elements and arranged in the matrix, A method of writing data in a non-volatile semiconductor storage device, comprising: a protection data storage element for storing memory protection information for each word line, wherein the storage element group and the protection data storage element are electrically connected and erasable. Electrically writing information to the protection data storage element; a data storage element for storing normal information connected to one word line of the storage element group; and protection data corresponding to the word line. Reading both information of the storage element through a common word line, and writing or writing to the read data storage element according to the information of the protected data storage element. Or not to allow the operation of to, or whether to prohibit the steps of generating a voltage for controlling, when the program or erase is permitted, it is the selected 1
Writing information to the data storage element of the word line or erasing the information of the data storage element of the selected one word line; and writing or erasing the information to the data storage element of the selected one word line. A step of preventing writing or erasing of information in the protected data storage element. 5. A storage element group composed of electrically erasable storage elements and arranged in a matrix, and a storage element group composed of electrically erasable storage elements and arranged in the matrix, An erasing method for a non-volatile semiconductor storage device, comprising: a protected data storage element for storing memory protection information for each word line, wherein the storage element group and the protected data storage element are electrically connected and erasable. Electrically writing information to the protected data storage element, a data storage element for storing normal information connected to one word line of the element group, and a protected data storage element corresponding to the word line. Reading out both via a common word line, and, in accordance with the information of the protected data storage element, whether to permit an erasing operation for the read data storage element. Or a step of generating a voltage for controlling whether or not to inhibit, a step of erasing the information of the selected one-word-line data storage element when erasure is permitted, and a step of erasing the information of the data storage element. A step of preventing writing or erasing of the protected data storage element when erasing is performed. 6. A storage element group composed of electrically erasable storage elements and arranged in a matrix, and a storage element group composed of electrically erasable storage elements and arranged in the matrix, A writing method for a non-volatile semiconductor storage device, comprising: a protected data storage element for storing memory protection information for each word line, wherein the storage element group and the protected data storage element are electrically connected to and erasable from each other. Electrically writing information to the protected data storage element, a data storage element for storing normal information connected to one word line of the storage element group, and a protected data storage corresponding to the word line. Reading both information of the elements through a common word line; and performing a write operation on the read data storage element according to the information of the protected data storage element. A step of generating a voltage for controlling whether to permit or prohibit; a step of writing information to the data storage element of the selected one word line when writing is permitted; a step of storing the data A step of preventing writing or erasing of information to the protected data storage element when writing information to the element. 7. A storage element group composed of electrically erasable storage elements and arranged in a matrix, and a storage element group composed of electrically erasable storage elements and arranged in the matrix, A nonvolatile semiconductor memory device comprising a protected data storage element for storing memory protection information for each word line, wherein the storage element group and the protected data storage element are connected in an electrically writable and erasable configuration, Means for electrically writing information to the protected data storage element; both a data storage element for storing normal information connected to one word line of the storage element group and a protected data storage element corresponding to the word line Means for reading the information of the data through a common word line, and permitting a write or erase operation on the read data storage element in accordance with the information of the protected data storage element. Or or or prohibited, and means for generating a voltage for controlling, when the program or erase is permitted, it is the selected 1
Means for writing information to the data storage element of the word line or erasing the information of the selected data storage element for the one word line; and protection for writing or erasing information to the data storage element. Means for preventing writing or erasing of information in the data storage element.