JPH0210451A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To protect stored contents by providing a register which designates permission or inhibition of access for each address space and controlling the access operation in accordance with contents of the register corresponding to the output of a decoder which discriminates the address space where the current address exists. CONSTITUTION:A selector 7 selects information A13 and A14 by a signal PR and outputs them to a decoder 8. The decoder 8 decodes information A13 and A14 to select one of protection registers 9. An input/output controller 10 is controlled by an external signal RD, the signal PR, and the signal from the protection register 9. When the signal of the protection register 9 is in the low level (read inhibition), the output from a sense amplifier/selector 5 is not outputted from the input/output controller 10. When it is in the high level (read permission), the output is outputted through the input/output controller 10.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a semiconductor memory device.

[Conventional technology]

In conventional semiconductor memory devices, it has been impossible to control memory protection within the semiconductor memory device.

[Problem to be solved by the invention]

The above-described conventional semiconductor memory device does not have a built-in circuit for controlling memory protection, and therefore has the disadvantage that if it is desired to protect memory, an external circuit must be provided for this purpose.

In addition, in semiconductor storage devices in which multiple memory planes can be connected to the same address, it is not possible to know from the outside which memory plane is currently selected, so memory protection cannot be performed. There is a drawback.

[Means to solve the problem]

The semiconductor memory device of the present invention includes a register that specifies whether access is allowed for each space in the divided address space, a decoder that determines which memory space is accessed during an access operation, and a decoder that specifies whether access is allowed. and a control circuit that controls access operations according to the contents of registers to be accessed.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention.

Row address buffer 1 is external address terminal Ao-A8
connected to. Row decoder 2 is connected to the output of row address buffer 1. Column address buffer 3 is connected to external address terminals A9 to A-th. Column decoder 4 is connected to column address buffer 3. Sense amplifier/selector 5 is connected to column decoder 4.

The memory cell array 6 includes a row decoder 2 and a sense amplifier/
Connected to selector 5. The selector 7 outputs A O and A l information from the row address buffer 1 and A 13 from the column address buffer 3.

A14 information output and control signal "r" are connected.

The decoder 8 is connected to the address information output from the selector 7.

Protection register 9 is connected to the output from decoder 8.

Input/output control 10 is sense amplifier/selector 5
and protection register input/output control 11 and external input/output terminals l10o to I/O7) knee connections tL, ff terminal, n terminal, Wl''r terminal, and output from protection register 9 are connected through a logic circuit.Protection The register input/output control 11 is controlled by the protection register 9 and external input
It is connected to the terminal, ff terminal, and ff terminal.

The operation when reading data in the memory cell array 6 will be explained.

(2) It is assumed that the W terminal is at a high level, and address information A, -A14 input from the outside is amplified by the row address buffer 1 and the column address buffer 3, respectively. Row decoder 2 decodes the output from row address buffer 1 and selects one word line in memory cell array 6.

The column decoder 4 decodes the output from the column address buffer 3, and the sense amplifier/selector 5 amplifies the output from the memory cell array 6.
1 word) and output.

The selector 7 selects the information of Al3A14 based on the rr multiplied signal and outputs it to the decoder 8. Decoder 8 is A13
A. Decodes the information in 4 and selects one of the protection registers 9. 0 The selected protection register 9 outputs memory protection information.

The input/output control 10 is controlled by the external 1" EW signal and W signal and the signal from the protection register 9. When the signal of the protection register 9 is low level (reading prohibited), the output from the sense amplifier/selector 5 is It is not output from the input/output control 10, and is outputted through the input/output control 10 when it is at a high level (read permission).

Further, writing/reading to the protection register 9 is performed by setting the rr terminal to a low level. At this time, the selector 7 selects the AoA1 signal from the row address buffer 1 and outputs it to the decoder 8.

Decoder 8 selects one of protection registers 9. Protection register input/output control 1
1 electrically connects one of the selected protection registers 9 to the input/output control 10, and performs reading and writing using the ff signal Tr signal.

〔Effect of the invention〕

As explained above, the present invention provides a semiconductor memory device with a register that divides an address space into several parts and specifies whether each address space can be accessed, and a register that determines in which space the current address is located during an access operation. By having a decoder and a control circuit that controls access operations according to the contents of the register selected by the output of the decoder, memory protection (permitting/disabling write and read operations depending on the state at that time) is performed. It has the effect of

[Brief explanation of the drawing]

FIG. 1 is a block diagram of one embodiment of the present invention. 1... Row address buffer, 2... Row decoder, 3... Column address buffer, 4... Column decoder, 5... Sense amplifier/selector, 6...
Memory cell array, 7... Selector, 8... Decoder, 9... Protection register, 10... Input/output control, 11... Protection register input/output control.

Claims (1)

[Claims] Divide the address space in a semiconductor storage device into several parts,
A register for specifying whether each space can be accessed, a decoder that determines which address space the access is to during an access operation, and control of the access operation according to the contents of the register that specifies whether access is possible. What is claimed is: 1. A semiconductor memory device comprising a control circuit that performs the following steps.