JPH10143434A - Semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the secrecy of data by providing more than prescribed number of security cells corresponding to the respective blocks of a divided memory array. SOLUTION: A memory cell 3 is a FLASH memory array constituted of the plural memory cells and divided into the prescribed number of the blocks and is divided into the four blocks of respectively different capacities. More than prescribed number of the security cells 1 corresponding to the respective blocks storing the data for indicating whether or not to perform a security operation to the respective blocks of the memory array are provided. A command decoder 5 stores instructions to the security cell 1 and the memory cell 3, which area of the security cell 1 and the memory cell 3 is to be erased, rewritten and read is entered to the respective areas of the decoder and the instructions are executed through a read circuit 21. Thus, the read, write and rewrite of the data desired to be private are prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor integrated circuit having security means for controlling memory cells divided into blocks.

[0002]

2. Description of the Related Art As memories and microcomputers with embedded memories,
Those with security measures have been developed. Security refers to preventing data leakage, rewriting by disabling commands such as reading, writing, and erasing with respect to the memory. The security means indicates a means for performing security.

[0003] Conventionally, by using a FLASH memory cell which can be electrically written and erased, an ON-
The security of the memory array was controlled on BOAD. Similarly, the EPROM memory and the EPROM-mixed microcomputer also use the EPROM memory cell as a security means, and perform security control of the memory array depending on whether or not to write the cell after ultraviolet erasure.

[0004] The FLASH memory and the FLASH mixed microcomputer include one having a single memory array and one having a plurality of divided arrays. In the former case, only batch erasure is performed, but the number of accompanying circuits is small and the overall area can be reduced. The latter has an advantage that erasing can be performed for each divided array, and user rewriting can be reduced. However, contrary to the former, there is a feature that the area of the associated circuit is increased as a whole.

A conventional semiconductor integrated circuit will be described below with reference to the drawings. FIG. 3 is a block diagram of a semiconductor integrated circuit having a conventional security means. First, the semiconductor integrated circuit includes a FLASH memory array 103 divided into a plurality of blocks for storing data and programs, a security cell 101 storing data relating to data security of the memory array 11 in each block of the memory array 103, Command decoder 105 storing instructions for security cell 101 and memory cell 103
And a block selection circuit 115 for determining whether the address of the instruction from the security cell 101 to the memory array 103 is valid.

A memory array 103 is composed of a plurality of memory cells and is divided into a predetermined number of blocks.
This is an SH memory array, and is divided into four blocks having different capacities in this embodiment. Also, for example, the block NO. 1 and block NO. 2 is a frequently rewritten data area, block No. 3 and block NO. 4
Is a program area with a low rewriting frequency.

[0007] The security cell 101 is composed of a MOS type semiconductor device, performs overall control of each block of the memory array 103, and permits commands such as rewriting, erasing, and reading data of each block of the memory array 103.
Accumulates unauthorized data.

The command decoder 105 accumulates instructions for the security cell 101 and the memory cell 103. Each area of the decoder indicates which area of the security cell 101 and the memory cell 103 is to be erased, rewritten, and read. Have been described. The command decoder 105 has a CE terminal for receiving a control signal for activating the memory cell 103, and a WE terminal for receiving a control signal for enabling the command decoder 105 to perform a write operation and an erase operation on the memory cell 103. By controlling the command decoder 105 from these terminals, the memory cell 103 can be rewritten and erased. Also, in this specification, this state is defined as security being UNLOCK,
A state in which erasing is not possible is defined as a state in which the security is LOCK. The block selection circuit 115 is a circuit for selecting a circuit to be rewritten and erased based on the data of the read circuit 111 and the address decoder 113 (memory cell area and information on whether this area is LOCK or UNLOCK). The block selection circuit 115 includes, for example, an AND circuit having one terminal connected to the read circuit 111 and the other terminal connected to the address decoder 113.

The operation of the conventional semiconductor integrated circuit will be described below. Signal from external or CPU (not shown) (CE / W
E, etc.), the command decoder 105 is instructed which block of the memory cell is to be rewritten and erased. The security cell is rewritten by the command of the command decoder. Here, the security cell 101 stores information as to whether the memory cell 103 is to be locked or UNLOCK collectively. Next, the information related to the security is read by the read circuit 111 and transmitted to the block selection circuit 115. Work is performed on the block based on this information. Here, for example, block NO.
The case of erasing data No. 3 will be described with reference to the flowchart shown in FIG. First, the command decoder 105 sends the block NO. A command to erase the data of No. 3 is issued.
Next, upon receiving the erase command, the security cell 101 is rewritten (security UNLOCK of the memory cell) with respect to the security cell 101. That is, the security cell confirms LOCK or UNLOCK.

[0010] Here, the security of the memory cell is LOC.
In the state of K, the erase command is processed as a wrong command,
The instruction ends. In addition, the security of the memory cell is UN
If the status is LOCK, the block No. of the designated area is set.
3 is erased and confirmed, and the instruction ends.

In this embodiment, the block NO. 3 was erased, but since commands are issued collectively to each block, the same command can be rewritten to other blocks (security UNLOCK). For this reason, when an erroneous command is sent, the confidentiality of data in a block that is not targeted is reduced, and the merit of the security means is reduced by half. Also, since the same command can be rewritten to other blocks (security UNLOCK), if the user malfunctions, data in other blocks may be rewritten or erased. Then, there is a possibility that the data program or the like may be destroyed.

The above-described problem occurs because the instruction system from the security cell to the memory array has only one path, and security is locked to the entire block.
Or, it is caused by the state of UNLOCK.

[0013]

A conventional FLASH memory or a microcomputer with a built-in FLASH memory is rewritable on a BOAD, so that attention must be paid to data security. As shown in the conventional example, when rewriting is enabled (security UNLOCK) and rewriting is performed, the security of other blocks is also in a rewriting enabled (security UNLOCK) state.
For this reason, when an erroneous command is sent, the confidentiality of data that is a block that is not a target is reduced, and the merit of the security means is reduced by half. Further, when the user malfunctions, not only data in other blocks is rewritten and erased, but also data in other blocks may be destroyed. This is because there is only one security cell for the memory array and there is only one security instruction system.

SUMMARY OF THE INVENTION It is an object of the present invention to provide security means for each divided array in a FLASH memory and a FLASH mixed microcomputer in which a memory array is divided into a plurality of parts, and to enhance the confidentiality of the held data.

[0015]

In order to solve the above-mentioned problems, a semiconductor integrated circuit according to the present invention comprises a memory array composed of a plurality of memory cells and divided into a predetermined number of blocks, and each block of the memory array. There is a predetermined number or more of security means corresponding to each block, in which data on whether or not to perform a security operation is stored. In addition, it has a command decoder for controlling reading, writing and erasing of data of the memory cell and the security means, and a predetermined number of block selection circuits for selecting each block and controlling the data of the security means. . Corresponding to each block of the memory array,
Because of the security cell, reading, writing, and rewriting of data to be kept secret can be prevented.

[0016]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a semiconductor integrated circuit having the security means shown in the present embodiment, which has a security cell corresponding to each divided block of the memory array.

First, in this semiconductor integrated circuit, a FLASH memory cell 3 (NO. 1 to NO. 4 in this embodiment) divided into a plurality of blocks for storing data, and rewriting of data in each block of the memory cell 3 Security cell 1 storing data of permitted and non-permitted data, a command decoder 5 storing commands to the security cell 1 and the memory cell 3, and determining whether the address of the command from the security cell 1 to the memory cell 3 is valid. And a plurality of block selection circuits 15 corresponding to individual blocks.

The command decoder 5 accumulates instructions for the security cell 1 and the memory cell 3, and each area of the decoder indicates which area of the security cell 1 and the memory cell 3 is to be erased, rewritten and read. The instruction is executed via the readout circuit 21.

The memory cell 3 is a FLASH memory array composed of a plurality of memory cells and divided into a predetermined number of blocks. In this embodiment, the memory cell 3 is divided into four blocks having different capacities. Security cell N
O. 0 is UNLOC for all blocks regardless of the state of other security cells.
Can be K. Further, for example, blocks 1 and 2 are a data area with a high rewriting frequency, and blocks 3 and 4 are a program area with a low rewriting frequency. The erase potential switching circuit 17 and the program potential switching circuit 19 of each block are connected. The command decoder 5 and the memory cell 3 are connected to the read circuit 21.

The security cell 1 is composed of a MOS type semiconductor device, and has a security cell corresponding to each block of the memory cell 3 (in this embodiment, a security cell NO.
1 to NO. 4) and a security cell NO. It consists of 0. Circuit 7 for switching data rewrite potential of security cell 1
And a command decoder 5 via a data erasing potential switching circuit 9. Further, it is connected to a block selection circuit 15 via a read circuit 11 for reading data of the security cell 1.

The block selection circuit 15 is a circuit for judging whether or not the address of the area instructed by the command decoder 5 is valid by checking the security cell 1.
It is composed of circuits and is composed of the same number of circuits as the divided blocks. For example, block NO. Security No. 1 is input to the input terminal of the AND circuit portion of the block selection circuit corresponding to No. 1. 1 and security NO. 0 is connected. The address decoder 13 is connected to one input terminal of the OR circuit portion, and the output terminal of the AND circuit is connected to the other input terminal.

This semiconductor integrated circuit has a plurality of terminals connected to external elements. The command decoder 5 has a CE terminal for receiving a signal for activating the memory cell 3, and the command decoder 5 has a WE terminal for receiving a signal for enabling a write operation to the memory cell 3. Further, an output control signal receiving terminal OE for receiving a signal from the readout circuit 21
And a 16-bit data terminal DT connected to the readout circuit 21 and a 24-bit address terminal AD connected to the address decoder 13, for example. The operation of the semiconductor integrated circuit shown in this embodiment will be described below. First, a signal such as CE / WE is transmitted to the command decoder 5 and an instruction is sent to which block of the memory cell 3 to work (for example, rewrite or erase). Next, the command decoder 5 responds to the instruction by the rewriting potential switching circuit 7 (signal PRG).
SC-D) or erasing potential switching circuit 9
(Control by the signal ERSSC-D) to control the security cell 1. Next, information of the security cell 1 (information of LOCK or UNLOCK) is read by the read circuit 11. For example, block NO. 3, the output signal SCOUT from the read circuit 11
The value of 3 becomes 0 and the state becomes UNLOCK. Security cell NO. 0 is used for batch UNLOCK, and the value of the signal SCOUT0 becomes 0. When security control is performed on other individual blocks, the signal SC
The value of OUT is 1, which makes the values of the signals SCOUT1 to SCOUT4 valid. Signal SCOUT from read circuit 11
0 and the signal SCOUT3 correspond to the circuit N of the block selection circuit 15.
O. 3 is connected to both input terminals of the
The output is 0.

From the command decoder 5, the circuit NO. When a signal is transmitted to the block selection circuit 1,
No. 5 The signal BSEL3 is transmitted to the block selection circuit 15 (the signal value is 0 because the block No. 3 is designated). 3 is connected to the input terminal of the OR circuit part. OR of block selection circuit 15
Since 0 is input to the input terminal from the address decoder of the circuit portion and 0 is input to the input terminal on the AND circuit side, the NO. 3 becomes 0, and the output of block NO. The security of No. 3 is in the UNLOCK state. Therefore, the block NO. 3, a rewrite command (controlled by signal BS3 from address decoder 13) is executed, and block NO. 3 is rewritten.

The operation for the other blocks will now be described. Block NO. No. 2 is in a write-protected state. First, in response to an instruction from the command decoder 5, the security cell changes the block number. 2 is set in a write-protection (LOCK) state.
The output signal (SCOUT2) read out from the terminal becomes 1.
Similarly, security NO. Output signal from 0 (SC0)
Therefore, the output signal (SCO) from the read circuit 11
UT0) 1. The output from the address decoder 13 is output from the block NO. Since the designated address is 1, the output signal (signal BSEL2) becomes 0, and the block selection circuit 1
No. 5 3 OR circuit. For this reason, the NO. The output of the OR circuit of No. 3 is 1, and the output of the block NO. No. 3 is in a state of rewriting inhibition (LOCK), and rewriting and erasing cannot be performed. Also, the security cell 1 NO. 0 is allowed to be rewritten (UNLOC
In the state of K), UNLO is applied to all blocks.
Since the state is CK, rewriting and erasing can be performed.

FIG. 2 is a diagram showing the operation timing of the command decoder, and is a clock diagram (a) showing the timing of the address and data input and a diagram (b) showing the data input to each area. In one cycle of operation of the semiconductor integrated circuit of the present invention, a data area storing a first instruction of a command decoder is designated, an address is designated, and the instruction is executed. The address is an area for data, that is, an area for executing a command of a cell (memory cell, security cell), and the CE is a CE for controlling a command decoder.
OE indicates a signal output from a memory cell to be output, WE indicates a waveform of a WE signal for controlling a command decoder, data indicates an area in which a command decoder instruction is stored, and D1 indicates a signal in a first cycle. The area where the instruction is stored, and D2 indicates the area where the instruction of the second cycle is stored.

For example, rewriting and erasing of a security cell (PRGSC-D / ERSSC-D) will be described. First, in the first cycle, an area for storing a command decoder erasing instruction is specified. Next, the erase area (BA: block address in this example) of the memory cell is designated, and the second
In the cycle (1), an instruction area for erasure is input, and each block is erased. Next, an operation for rewriting a memory cell will be described. First, in the first cycle, an area for storing a rewrite instruction is input, and an area of a cell for executing the instruction (in this example, BA: block address) is input. Next, data to be rewritten in the second cycle (in this example, PD: program data) is input. Next, a read operation of the security cell and the memory cell will be described. First, an area for storing a read instruction of the command decoder is designated. The execution area is optional for a security cell,
In the case of a memory cell, it is a designated area (in this example, BA: block address). Next, an output area or data to be rewritten is input in the second cycle, and the instruction is executed.

As described above, in this embodiment, the ON state of the FLASH EPROM cell is used as security means.
And OFF switching, the resistance value and RA
The value of M and the FUSE cell may be used. Further, only the data area can be opened to the user, and the area (for example, the program area) which wants to maintain security can be kept private or unanalysable.

[0028]

The semiconductor integrated circuit according to the present invention has at least the predetermined number of security means corresponding to each block of the divided memory array. Since each memory array has a security means, security is operated for a memory array to be prohibited from being read or rewritten, thereby preventing erroneous reading of data, erroneous rewriting, destruction of data, etc. in response to user misuse. I can do it. In addition, since the number of security cells is large, the confidentiality of data stored in the memory array can be increased.

[Brief description of the drawings]

FIG. 1 is a block diagram of a semiconductor integrated circuit according to an embodiment of the present invention.

FIG. 2 is a conceptual diagram showing data writing to a command decoder according to the present invention.

FIG. 3 is a block diagram of a semiconductor integrated circuit according to a conventional example of the present invention.

FIG. 4 is a flowchart showing an operation of a semiconductor integrated circuit according to a conventional example of the present invention.

[Explanation of symbols]

Reference Signs List 1 security cell 3 memory cell 5 command decoder 7 9 17 19 voltage switching circuit 11 21 read circuit 13 address decoder 15 block selection circuit ERSSC-D PRGSC-D RDSC-D output signal ERS-D PRG-D RD-D output signal SC0 To SC4 output signal SCOUT0 to SCOUT4 output signal BSEL1 to BSEL4 output signal DATA ADDRESS OE CE WE terminal

Claims (11)

[Claims] 1. A memory array divided into a plurality of blocks, security means for storing selection data corresponding to each block of the memory array, and data of each block of the memory array based on data of the security means. And a block selecting circuit for determining whether to rewrite or erase the data. 2. The semiconductor integrated circuit according to claim 1, wherein said security means comprises a MOS transistor corresponding to each of said blocks and a MOS transistor for controlling said memory array collectively. circuit. 3. The semiconductor integrated circuit according to claim 1, wherein said block selection circuit has a configuration corresponding to each of said blocks. 4. An AND circuit having one input terminal connected to the security means, one input terminal connected to the output terminal of the AND circuit, and another input terminal connected to an address decoder. 2. The semiconductor integrated circuit according to claim 1, comprising: 5. The semiconductor integrated circuit according to claim 1, wherein said security means and said memory array are connected via said block selection circuit. 6. A memory array divided into a predetermined number of blocks, and selection data corresponding to each block of the memory array are stored, and the predetermined number of first security means corresponding to each of the blocks, and A security unit configured by a second security unit that controls the memory array collectively; a command decoder that controls reading, writing, and erasing of data in the memory array and the security unit; and a command to the memory array. An address decoder for controlling a region to be executed; an address decoder connected to the address decoder; and a block for selecting the block and determining whether to rewrite or erase data in the memory array based on data of the security unit. And a block selection circuit that performs Conductor integrated circuit. 7. An AND circuit having one input terminal connected to the first security means and another input terminal connected to the second security means, and one input terminal connected to the output of the AND circuit. 7. The semiconductor integrated circuit according to claim 6, further comprising a terminal and an OR circuit having another input terminal connected to the address decoder. 8. The first security means is connected to one input terminal of each of the corresponding block selection circuits, and
7. The semiconductor integrated circuit according to claim 6, wherein said security means is connected to another input terminal of all the block selection circuits. 9. The semiconductor integrated circuit according to claim 6, wherein said first security means and said second security means comprise MOS transistors. 10. The semiconductor integrated circuit according to claim 6, wherein a plurality of said block selection circuits are provided, and each of said block selection circuits corresponds to each of said blocks. 11. The semiconductor integrated circuit according to claim 6, wherein said security means and said memory array are connected via said block selection circuit.