JP2002007372A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device capable of performing direct access to an incorporated non-volatile memory and preventing data stored in the non- volatile memory from being illegally read. SOLUTION: Most of a large number of memory cells provided in a memory cell array 11 form an ordinary data storage area 12 and a part of these memory cells forms a lock bit 13, on the other hand. When lock data are not stored in the lock bit 13, an input/output control circuit 21 permits the read of ordinary data, which are stored in the ordinary data storage area 12, from the outside and when the lock data are stored in the lock bit 13, on the other hand, the input/output control circuit 21 inhibits the read of the ordinary data, which are stored in the ordinary data storage area 12, from the outside.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device,
In particular, a system LSI (Large Scale Integrated circuit) or an ASIC (Application Specific Integrated Circuit) incorporating a nonvolatile memory such as a flash memory.
t) and the like.

[0002]

2. Description of the Related Art In a semiconductor device such as a system LSI or an ASIC in which a nonvolatile memory such as a flash memory is embedded, data stored in the nonvolatile memory is stored in an RO.
In order to easily perform rewriting with an M writer or the like and test by direct access, it is necessary to connect the input / output terminal of the nonvolatile memory directly to the input / output terminal of the chip or to connect via a buffer or the like. There were many.

[0003]

However, in such a conventional semiconductor device, rewriting of data stored in the nonvolatile memory and reading from the outside are not restricted. There has been a problem that unauthorized rewriting of stored serial numbers and unauthorized reading of encrypted programs are easily performed.

For this reason, in recent years, a general-purpose flash memory having a function of locking a sector or the entire chip to prevent unauthorized rewriting of stored data has been provided. However, this flash memory still has a disadvantage that stored data is easily read illegally.

In view of the above, the present invention provides a semiconductor device capable of directly accessing a built-in nonvolatile memory and preventing illegal reading of data stored in the nonvolatile memory. Aim.

[0006]

In order to solve the above problems, a semiconductor device according to the present invention comprises a normal data storage area formed of a plurality of memory cells for storing normal data and at least one memory cell. A non-volatile memory cell array including a lock bit for storing lock data for prohibiting external reading of normal data stored in the normal data storage area and having two input / output systems, and one of the input / output systems A logic circuit connected to the non-volatile memory cell array to read normal data from the normal data storage area, and a control circuit connected to the non-volatile memory cell array through the other input / output system. If it is not stored, the normal data stored in the normal data storage area is output to the outside While allowing the to the, if the lock data is stored in the lock bit is typically data that is stored in the normal data storage area and a control circuit for inhibiting from being outputted to the outside.

According to the above invention, unless lock data is stored in the lock bit, reading of the normal data stored in the normal data storage area from the outside is permitted. Therefore, direct access to the normal data storage area is performed. Test normal data. On the other hand, if the lock data is stored in the lock bit, the normal data stored in the normal data storage area is prohibited from being read from the outside, so that the normal data is data to be kept secret (for example, an encryption program). However, it is possible to prevent such secret data from being illegally read. It is to be noted that the input / output system connecting the nonvolatile memory cell array and the logic circuit is not shut off regardless of whether or not the lock data is stored in the lock bit. Therefore, the logic circuit can always read the normal data stored in the normal data storage area.

In the above invention, it is preferable that the normal data storage area and the lock bit are erased collectively by a common erase command. In this case, after the lock bit is erased, normal data is not illegally read, and the OTPROM (One Time Pro
Unlike a grammable read only memory, new normal data can be stored in the normal data storage area after erasing, so that a program in the normal data storage area can be easily updated.

It is preferable that the normal data storage area and the lock bit are included in the same nonvolatile memory unit. In this case, the normal data storage area and the lock bit are formed by the memory cells included in the same non-volatile memory unit, and the configuration of the semiconductor device can be prevented from becoming unnecessarily complicated.

[0010]

Embodiments of the present invention will be described below with reference to the accompanying drawings. FIG. 1 is a block diagram showing a schematic configuration of a semiconductor device according to one embodiment of the present invention. The semiconductor device shown in FIG. 1 is a system LSI or an ASIC in which a flash memory unit 10, a CPU (Central Processing Unit) 20 and the like are mixed, and the flash memory unit 10 includes a memory cell array 11 and an input / output control circuit 21. Have been. The input / output control circuit 21
May not be included in the flash memory unit 10.

The memory cell array 11 includes a large number of memory cells. Most of the memory cells form the normal data storage area 12, while some of the memory cells form the lock bit 13. The lock bit 13 is constituted by one or a plurality of bits.

The normal data storage area 12 has a CPU 20
Is stored. On the other hand, the lock bit 13 stores lock data for inhibiting normal data from being read out. Therefore, when the lock data is stored in the lock bit 13, reading out the normal data from the outside is prohibited.

The memory cell array 11 has a word line driver 16 for selecting one of the word lines 14 of a large number of memory cells and applying a prescribed voltage, and a prescribed voltage for a source line 15 of a large number of memory cells. Is connected to a source line driver 17 for applying a voltage.

When normal data is stored in the normal data storage area 12, the word line driver 16 that has received the program command for the normal data storage area operates in the plurality of word lines 14 connected to the normal data storage area 12. 1
One is selected, a specified voltage is applied, and normal data is stored bit by bit. Similarly, when storing the lock data in the lock bit 13, the word line driver 16 receiving the lock bit program command selects one of the plurality of word lines 14 connected to the lock bit 13 and A specified voltage is applied and lock data is stored.

On the other hand, when the normal data is erased from the normal data storage area 12 or the lock data is erased from the lock bit 13, the word line driver 16 and the source line driver 17 which receive the common erase command are used.
Applies a specified voltage to all the word lines 14 and the source lines 15 to collectively erase normal data and lock data from the normal data storage area 12 and the lock bits 13.

The data bus 1 is connected to the memory cell array 11.
8 (one input / output system) is connected to the CPU 20. The CPU 20 has an input terminal 22 and an output terminal 24 for a logic circuit other than the memory cell array 11 (hereinafter, referred to as a controlled circuit). The CPU 20 generates a control command based on data input from the controlled circuit via the input terminal 22 and normal data read from the normal data storage area 12 via the data bus 18, and generates a control command via the output terminal 24. The control command is output to the controlled circuit.

The data bus 1 is connected to the memory cell array 11.
An input / output control circuit (for example, a multiplexer) 21 is connected via 9 (the other input / output system). The input / output control circuit 21 has an input terminal 23 and an output terminal 25 connected to an input terminal and an output terminal of the chip. The input / output control circuit 21 is a logic circuit for controlling data input / output between the memory cell array 11 and the outside.

Here, the input / output control circuit 21 will be described in detail. The input / output control circuit 21 supplies normal data and lock data externally input via the input terminal 23 to the memory cell array 11 via the data bus 19. When the lock data is not stored in the lock bit 13, the input / output control circuit 21 outputs
The output of the normal data to the outside via the output terminal 25 is prohibited when the lock data is stored in the lock bit 13 while the normal data is permitted to be output to the outside via the terminal 5.

Therefore, according to the present embodiment, unless lock data is stored in the lock bit 13, the input / output control circuit 21 permits output of the normal data stored in the normal data storage area 12 to the outside. Therefore, normal data can be tested by directly accessing the normal data storage area 12. On the other hand, if the lock data is stored in the lock bit 13, the input / output control circuit 21
Since the output of the normal data stored in the external data to the outside is prohibited, even if the normal data is data to be concealed (for example, an encryption program), it is necessary to prevent such confidential data from being illegally read from the outside. Can be prevented. Regardless of whether or not the lock data is stored in the lock bit 13, the data bus 18 is not shut off.
0 indicates that the normal data stored in the normal data storage area 12 can always be read.

Further, according to the present embodiment, since the normal data storage area 12 and the lock bit 13 are set to be erased collectively by the common erase command, the normal data is illegally erased after the lock bit 13 is erased. Unlike the OTPROM, new normal data can be stored in the normal data storage area 12 after erasure, so that updating of the program in the normal data storage area 12 can be easily performed.

[0021]

As described above, according to the present invention,
It is possible to directly access the built-in non-volatile memory and to prevent illegal reading of data stored in the non-volatile memory.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a schematic configuration of a semiconductor device according to an embodiment of the present invention.

[Explanation of symbols]

 Reference Signs List 10 Flash memory section 11 Memory cell array 12 Normal data storage area 13 Lock bit 16 Word line driver 17 Source line driver 18, 19 Data bus 20 CPU 21 I / O control circuit 22, 23 Input terminal 24, 25 Output terminal

Claims (3)

[Claims] 1. A normal data storage area formed of a plurality of memory cells and storing normal data, and normal data formed of at least one memory cell and stored in the normal data storage area are externally read. A non-volatile memory cell array including a lock bit for storing lock data for prohibiting the non-volatile memory cell and having two input / output systems, and connected to the non-volatile memory cell array via one of the input / output systems, A logic circuit for reading normal data from an area, and a control circuit connected to the nonvolatile memory cell array via the other input / output system, wherein when lock data is not stored in the lock bit, While permitting normal data stored in the data storage area to be output to the outside, A control circuit for prohibiting output of normal data stored in the normal data storage area to the outside when the lock bit is stored in the lock bit. apparatus. 2. The semiconductor device according to claim 1, wherein said normal data storage area and said lock bit are erased collectively by a common erase command. 3. The semiconductor device according to claim 1, wherein the normal data storage area and the lock bit are included in the same nonvolatile memory unit.