JP2003203012A - Microcomputer device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a microcomputer device capable of surely protecting data in a nonvolatile memory from the leak to a third person with unknown internal data by preventing the illicit read of data from the nonvolatile memory. <P>SOLUTION: This microcomputer device comprises a prohibiting flag 94 for prohibiting the read or write verify of the nonvolatile memory 92, for example, in the input of a power supply, and controls the read or write verify of the nonvolatile memory 92 to be released only when it is confirmed that the prohibiting flag 94 is eliminated by an eliminating verify. Accordingly, the microcode or data in the nonvolatile memory 92 cannot be externally indirectly accessed by the third person with unknown internal data, or decoded by use of any means by such a third person. The nonvolatile memory 92 is divided to blocks, and no prohibiting flag is provided for a block which does not need the read prohibition. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microcomputer device equipped with a non-volatile memory and having a leakage prevention function for data such as microcode written in the non-volatile memory. .

[0002]

2. Description of the Related Art Conventionally, a microcomputer device having a nonvolatile memory has a function of preventing leakage of data such as microcode written in the nonvolatile memory in order to protect the data from being leaked to a third party. Had.

In order to make such a leak prevention function effective, when accessing the non-volatile memory in order to read data such as microcode written in the non-volatile memory in the microcomputer device, As an access method, a circuit that allows the user to give an ID code unique to the product is used to check the match with the ID code when in use. There is a method of inputting the data from the outside and making it accessible if the matches can be confirmed.

In order to enable the leakage prevention function of the conventional microcomputer device as described above,
An access method for reading data such as microcode written in the nonvolatile memory will be described below.

FIG. 16 is a block diagram showing the structure of a conventional microcomputer device. This microcomputer device is provided with an ID code memory 45 for storing a product-specific ID code, for example, as shown in FIG. 16, and a user writes a unique code in advance in the ID code memory 45. In addition, when reading and writing to the nonvolatile memory 42, be sure to use the ID from the outside.
A code is input, and this ID code is matched with the ID code of the product ID code memory 45 by the comparator 49 through the data bus, and if it does not match, the nonvolatile memory 42 cannot be accessed. .
In such a system, there is less risk that the data such as the microcode written in the non-volatile memory 42 will be leaked to a third party whose product-specific ID code is unknown.

On the other hand, as another access method, when the non-volatile memory is rewritten, the data in the memory is not output to the outside at all, but only the result of matching or non-matching by comparison with the data input from the outside is obtained. Is output. In such a system, data such as microcode written in the non-volatile memory is not output to the outside at all, so that the risk of leaking the contents of the memory to a third party who does not know the contents of the memory is reduced.

As described above, in the conventional microcomputer device, the data such as the microcode written in the non-volatile memory cannot be understood by the third party whose product-specific ID code is unknown, or the contents of the memory. I try to protect it from leakage to a third party.

[0008]

However, in the conventional microcomputer device as described above, the risk that the contents of the memory will be leaked to a third party whose ID code or contents of the memory cannot be known is reduced. Enter the code or data over and over until they match,
If they finally match, the non-volatile memory can be accessed at the time of detection, and data may be illegally read from the non-volatile memory.

Therefore, it is impossible to completely prevent the leakage of the memory contents to a third party whose ID code or the contents of the memory are unknown, and the micro-program written in the non-volatile memory from such leakage to the third party. There is a problem that it is difficult to reliably protect data such as codes.

The present invention solves the above-mentioned problems of the prior art by preventing unauthorized reading of data from a non-volatile memory and leaking memory contents to a third party whose ID code or memory contents are unknown. There is provided a microcomputer device capable of completely eliminating the above, and reliably protecting data such as a microcode written in a non-volatile memory from such leakage to a third party.

[0011]

In order to solve the above-mentioned problems, a microcomputer device of the present invention is a microcomputer device equipped with a non-volatile memory for storing various data such as a microcode for operating various functions. There is a flag for granting the access permission when controlling the access to the non-volatile memory, and the access to the non-volatile memory is controlled according to the state of the flag, and the contents of the non-volatile memory are erased. And a control unit for controlling the flag so as to permit access to the nonvolatile memory only later.

From the above, for example, with respect to the flag for prohibiting the read or write verification of the memory when the power is turned on, the prohibition of the read or write verify of the memory is not released unless the erase of the memory is confirmed by the erase verify of the memory. By controlling the above, the indirect access from the outside to the microcode and the data in the non-volatile memory by the third party whose ID code or the contents of the memory is unknown is also impossible. Decryption by any means by the three can be made impossible.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A microcomputer device according to claim 1 of the present invention is a microcomputer device equipped with a non-volatile memory for storing various data such as a microcode for operating various functions. A flag for granting the access permission when controlling the access to the non-volatile memory, and controlling the access to the non-volatile memory according to the state of the flag, and the flag only after erasing the contents of the non-volatile memory. And a control unit for controlling so as to permit access to the nonvolatile memory.

A microcomputer device according to a second aspect divides the entire area of the nonvolatile memory according to the first aspect into a plurality of erase unit blocks, and a flag is provided for each of the plurality of erase unit blocks. The control unit erases the contents of each of the plurality of erase unit blocks individually, and then the flag corresponding to the erase unit block is associated with the erase unit block. Configure to control to allow access.

According to a third aspect of the present invention, there is provided a microcomputer device, wherein when the data to be written in the non-volatile memory by the control section according to the first aspect is a test pattern for inspection, a flag permits access to the non-volatile memory. It is configured to control so that

According to a fourth aspect of the present invention, there is provided a microcomputer device in which the control section according to the first aspect is constituted by an FPGA using a Vt control type memory. The microcomputer device according to claim 5 only permits access to the nonvolatile memory by a control signal that stores the flag according to claim 1 in a chip-specific information area.
Depending on the state of access to the non-volatile memory, access to the non-volatile memory is not permitted.

According to a sixth aspect of the present invention, the microcomputer device of the second aspect enables the control unit according to the second aspect to enable the access restriction flag only for blocks that require access restriction and permit access for other blocks. It is configured to control.

According to a seventh aspect of the present invention, there is provided a microcomputer apparatus according to the sixth aspect, which is provided with an access restriction flag only for a block that requires access restriction, and has the flag for other blocks. If not provided, the control unit is configured to control access to the block not provided with the flag without confirming the flag.

The microcomputer device according to claim 8 is the microcomputer device according to any one of claims 1 to 7, wherein an access prohibition flag is provided on the same substrate or the same package when the power is turned on. Power-on-clear means for enabling and prohibiting memory access is provided, and the power-on-clear means is configured to control the prohibition flag to be effective at power-on regardless of the operation of the microcomputer.

According to a ninth aspect of the present invention, there is provided a microcomputer device according to any one of the first to seventh aspects, wherein the access prohibition flag is enabled based on a system reset signal for the microcomputer. Thus, means for prohibiting memory access is provided, and the memory access prohibition means is configured to be controlled to prohibit the flag by the system reset signal.

According to a tenth aspect of the present invention, there is provided a microcomputer device according to any one of the first to seventh aspects, which is designed so that the logical value of its output is always the same when the power is turned on. Means for prohibiting memory access by enabling the access prohibition flag by using the latch, flip-flop, etc., so that the memory access prohibition means always has the same logical value when the power is turned on to prohibit the flag. It is configured to control.

According to these configurations, for example, with respect to the flag for prohibiting the reading or writing verification of the memory when the power is turned on, the reading or writing verification of the memory is prohibited unless the erasing of the memory confirms the erasing of the memory. By controlling so as not to be released, indirect access from outside to the microcode and data in the non-volatile memory by a third party whose ID code or the contents of the memory is unknown is also impossible. It makes it impossible for a third party to decipher by any means.

A microcomputer device showing an embodiment of the present invention will be specifically described below with reference to the drawings. (Embodiment 1) A microcomputer device according to Embodiment 1 of the present invention will be described.

FIG. 1 is a block diagram showing the configuration of the microcomputer device according to the first embodiment. As shown in FIG. 1, the microcomputer device of the present embodiment includes a microcomputer (CPU) 1 and a non-volatile memory 2.
An interface 3, an inhibition flag 4 for indicating inhibition of reading from the non-volatile memory 2, a power-on-clear signal generating means 5, and a control circuit for inhibiting the reading from the non-volatile memory 2 by receiving the inhibition flag 4. 6 and
It comprises a control signal input buffer 7 into which a control signal for the non-volatile memory 2 is input, and an address input buffer 8 into which an access address for the non-volatile memory 2 is input.

The operation of the microcomputer device configured as described above will be described below. In the microcomputer device according to the first embodiment, in the normal operation mode in which the device normally incorporated by the user executes the functional operation, the data from the non-volatile memory 2 is sent to the same chip through the data bus. While transferring to the internal microcomputer (CPU) 1
The microcomputer (CPU) 1 executes a program for the above functional operation.

However, when the non-volatile memory 2 is rewritten, it is possible to use the built-in device or the chip itself as a unit.
It is possible to rewrite the data in the non-volatile memory 2 by connecting to a dedicated rewriting device, and in this state, the data in the non-volatile memory 2 can be directly output to the outside. In this case, the rewriting mode for the nonvolatile memory 2 is different from the normal operation mode by the user.

In this special rewrite mode, the prohibition flag 4 is set to indicate, for example, a read prohibition state and a write verify prohibition state with respect to the nonvolatile memory 2 when the power is turned on. The write verify refers to a special read for confirming that the data after writing to the non-volatile memory 2 has a margin such that sufficient reliability can be obtained at the time of reading.

By the prohibition flag 4 as described above, a comparison is performed to confirm the coincidence after the data is read from the nonvolatile memory 2 or the data is input to the nonvolatile memory 2 by the write verify even in the rewrite mode. It becomes impossible to operate. When read or write verify is performed in a state in which the inhibition by the inhibition flag 4 is applied, all the data read from the nonvolatile memory 2 is arbitrary except the logic "1" regardless of the state of the nonvolatile memory 2. The control circuit 6 controls to output the value of.

If all the output data are logic "1", it may be erroneously determined whether the current state is prohibited or erased. Therefore, all data which is logic "1" should not be output. I have to. Even when the output data in each prohibited state is other than logic "1", controlling all data to logic "0" is particularly compatible with a general-purpose memory rewriting device because the load on the circuit is small.

Next, the prohibition state of the prohibition flag 4 is released, but only when it is confirmed that all the data in the nonvolatile memory 2 is erased and rewritable, that is, the erased state is confirmed. Cancel. for that reason,
Erase verify is performed on the nonvolatile memory 2. The erase verify is a special read for confirming that the erased data in the nonvolatile memory 2 has a reliable margin at the time of read. Unlike write, read data usually has a logic 1 Show.

In the erase verify, if the verify result is OK, an OK signal is received to release the prohibition state in the prohibition flag 4, but if the verification result is NG, the prohibition state in the prohibition flag 4 is not released. In order to remove this prohibition state, the erase verify must be OK by erasing the nonvolatile memory 2.

That is, if the non-volatile memory 2 is erased in order to make the erase verify OK for the purpose of canceling the prohibition state in the prohibition flag 4, the microcode etc. stored in the non-volatile memory 2 up to that time will naturally be erased. The data will be erased, and as a result, the data will not be decrypted by an unrelated third party other than the user.

FIG. 2 is a flowchart showing the sequence of the rewriting operation in the microcomputer device of the first embodiment. In the sequence shown in the flowchart of FIG. 2, first, when the power is turned on, the signal from the power-on-clear signal generating means 5 is used to set the data indicating the inhibition of reading in the inhibition flag 4 (step 201). Next, erase verify is executed to confirm whether the content of the nonvolatile memory 2 is in the erased state (step 202).
If it is not in the erased state, the memory erase of the nonvolatile memory 2 is executed (step 203), and the erase verify is executed again (step 202).

When the erase verify of the nonvolatile memory 2 is OK (step 202), the inhibition flag 4
Turns off and cancels the read prohibition (step 20).
4). After that, the erased nonvolatile memory 2 is subjected to normal access such as writing or reading, and the necessary microcode is written (step 205).
finish.

As described above, according to the present embodiment, since the code and the memory data cannot be indirectly accessed from the outside, the repeated data matching can be performed as in the conventional case. It is impossible to decipher by such means. Further, a memory for setting an ID code for each chip can be dispensed with. (Second Embodiment) A microcomputer device according to a second embodiment of the present invention will be described.

FIG. 3 is a block diagram showing the configuration of the microcomputer device according to the second embodiment. In FIG. 3, reference numeral 11 denotes a CPU, which controls the entire microcomputer device. Reference numeral 12 denotes a non-volatile memory, the entire area of which is divided into a plurality of erasing unit blocks, and non-volatile memory array blocks (0) to (4) for storing a microcode for each erasing unit block, a writing circuit and a reading circuit. And an input / output buffer for buffering input / output of data with respect to the data bus, and a decoder for decoding the access address. An interface 13 serves as an interface for inputting a microcode from the outside and outputting an internal signal to the outside. Reference numeral 14 is a prohibition flag, which is composed of prohibition flags (0) to (4) corresponding to the nonvolatile memory array blocks (0) to (4) and a decoder. Reference numeral 15 is a power-on-clear signal generating means, which resets the prohibition flags (0) to (4) when the power is turned on. 1
Reference numeral 6 denotes a control circuit, which performs control for determining the directionality of the input / output buffer and the presence / absence of data output. A control signal input buffer 17 buffers a control signal from the outside. An address input buffer 18 buffers an access address.

The operation of the microcomputer device configured as described above will be described below. In the microcomputer device of the second embodiment, the decoder of the non-volatile memory 12 and the decoder of the prohibition flag 14 decode the address, thereby recognizing the block for each erase unit of the non-volatile memory array and prohibiting it. Only the block prohibited by the flag 14 is prohibited from being read, and the block in which the prohibit flag 14 is released enables reading and writing.

FIG. 4 is a flowchart showing the sequence of the rewriting operation in the microcomputer device of the second embodiment. In the sequence shown in the flowchart of FIG. 4, first, when power is turned on, a signal from the power-on-clear signal generating means 15 is used to set data indicating read inhibition to all of the inhibition flags 14 (step 40).
1). Next, erase verification (confirmation) is executed in order to confirm whether the content of the block to be written in the nonvolatile memory 12, for example, the block (0) is in the erased state (step 402).

If the block (0) of the nonvolatile memory 12 is not in the erased state and it is desired to write to the block (0) (step 405), the block (0) is erased (step 406), erase verify is executed again, and erase verify of block (0) is OK.
When this happens (step 402), the inhibition flag (0) corresponding to the block (0) is turned off, and the read inhibition for the block (0) is released (step 403).

Thereafter, the erased block (0) of the non-volatile memory 12 is subjected to normal access such as writing and reading, and the necessary microcode is written to the block (0) (step 404). Next, for example, erase verify of the block n to be written is performed.

As described above, the procedure performed for the block (0) of the nonvolatile memory 12 is repeated to access the last block (steps 407, 408, 41).
0, 411), the necessary microcode is written to the last block (step 409), and the process is terminated.

As described above, the inhibition flag is provided for each block of the non-volatile memory to enable reading and writing to the already erased block, so that, for example, all areas of the non-volatile memory are By rewriting only the necessary blocks without rewriting again, writing of microcode during debugging is facilitated, and only the necessary parts need to be written, so the rewriting time of the non-volatile memory is shortened. be able to.

In the present sequence, writing is performed so that it happens to sequentially start from the block (0), but the access order of the blocks can be arbitrarily selected and executed. (Third Embodiment) A microcomputer device according to a third embodiment of the present invention will be described.

The microcomputer device of the third embodiment is structurally similar to the case shown in FIG. 1, and includes a microcomputer (CPU) 1, a non-volatile memory 2, an interface 3, and a read prohibition flag 4. , A power-on-clear signal generating means 5, a control circuit 6 for inhibiting reading by receiving the inhibition flag 4, an input buffer 7 for a control signal of a non-volatile memory, and an address buffer 8.

In the microcomputer device of the third embodiment, in order to release the prohibition flag 4, not only the erased state of the non-volatile memory 2 but also the content of data necessary for the inspection, for example, all logic "0". In the case of a special test pattern such as a checker pattern in which a logical "1" and a logical "0" are alternately output by an address like a checker pattern, the prohibition flag 4 is released. .

FIG. 5 is a flowchart showing the sequence of the rewriting operation in the microcomputer device of the third embodiment. In the sequence shown in the flowchart of FIG. 5, first, when the power is turned on, a signal from the power-on-clear signal generating means 5 is used to set data indicating the read prohibition in the prohibition flag 4 (step 501). next,
In order to confirm whether the content of the non-volatile memory 2 is in the erased state, erase verify is executed (step 50).
2).

If the data is not in the erased state, the data in the non-volatile memory 2 is the All "0" pattern state (step 503), the checker pattern state (step 504), or another test pattern state (step 505). ) And the like are confirmed to be in a special repeated pattern state used for inspection, and if they do not match, the nonvolatile memory 2 is erased (step 506) and the erase verify is performed again (step 502).

When the erase verify is OK or coincides with the various inspection patterns, the inhibition flag 4 is turned off and the readout inhibition is released (step 507). After that, the erased nonvolatile memory 2 is subjected to normal access such as writing and reading, and the necessary microcode is written (step 508), and the process is terminated.

As described above, in the case of a test pattern or the like in which there is no problem even if it is read out, it is opened, and the cost performance can be improved by shortening the inspection time. (Fourth Embodiment) A microcomputer device according to a fourth embodiment of the present invention will be described.

FIG. 6 is a block diagram showing the configuration of the microcomputer device according to the fourth embodiment. As shown in FIG. 6, the microcomputer device of the present embodiment has a microcomputer (CPU) 21, a non-volatile memory 22, an interface 23, and a prohibition flag 24.
The power-on-clear signal generating means 25 and the prohibition flag 24 are used to prohibit reading, and the nonvolatile memory 22
A control circuit 26 including an FPGA for controlling the threshold value of, a control signal input buffer 27 for inputting a control signal to the non-volatile memory 22, and an address input buffer 28.
Composed of and.

The operation of the microcomputer device configured as described above will be described below. In the microcomputer device of the fourth embodiment, the control circuit 26 is an FPGA that is controlled by the threshold value Vt of the non-volatile memory 22, and its control logic is FP.
Since it exists in the memory which constitutes the GA, it becomes impossible to read the data in the memory in the control circuit 26 by the chip analysis, and the sequence of opening the memory in the special test mode cannot be decoded. .

Therefore, it is possible to prevent the contents of the non-volatile memory 22 from being read by the memory opening sequence decoded from the control circuit 26. The memory that constitutes the FPGA is a non-volatile memory or a memory cell in which the threshold voltage is higher than the gate voltage when reading the memory by changing the concentration of impurities that control the threshold Vt in the manufacturing process of the memory cell. By creating two states of the lowered memory cell,
Alternatively, "0" can be recognized. (Fifth Embodiment) A microcomputer device according to a fifth embodiment of the present invention will be described.

FIG. 7 is a block diagram showing the configuration of the microcomputer device according to the fifth embodiment. As shown in FIG. 7, the microcomputer device of the present embodiment has a microcomputer (CPU) 31, a non-volatile memory 32, an interface 33, and an initial information register 3.
4, a control circuit 35, a control signal input buffer 36 for inputting a control signal to the nonvolatile memory 32,
It is composed of an address input buffer 37.

The operation of the microcomputer device configured as described above will be described below. In the microcomputer device of the fifth embodiment, in the nonvolatile memory 32, redundant address information on the initial information register 34, trimming information of the internally generated power source, etc.
By assigning the setting information of the read prohibition flag to the area for storing the initial setting information, the exclusive prohibition flag and the power-on-clear signal generating means are unnecessary.

The prohibition flag is set in the initial setting sequence, and the subsequent operation is the same as in the case of FIG. FIG. 8 is a flowchart showing the sequence of the rewriting operation in the microcomputer device of the fifth embodiment.

In the sequence shown in the flowchart of FIG. 8, the power is first turned on to read the data from the initial information storage area in the nonvolatile memory 32 and set it in the initial information register 34 (step 801). Since an arbitrary bit of the initial information register 34 is assigned to read prohibition, the reading of the nonvolatile memory 32 is prohibited (step 802).

Next, erase verify is executed to confirm whether the contents of the non-volatile memory 32 are in the erased state (step 803). If it is not in the erased state, the nonvolatile memory 32 is erased (step 804) and the erase verify is performed again (step 803). When the erase verify is OK, the read prohibition bit of the initial information register 34 is turned off and the read prohibition is released (step 805).

After that, the erased non-volatile memory 32 is subjected to normal access such as writing and reading,
The necessary microcode is written (step 806) and the process ends.

As described above, by storing the prohibition flag in the information area peculiar to the chip and invalidating it by the control signal, the degree of freedom of the inspection is increased and the data is destroyed in the analysis in case of any problem. It can be executed without any (Sixth Embodiment) A microcomputer device according to a sixth embodiment of the present invention will be described.

FIG. 9 is a block diagram showing the structure of the microcomputer device according to the sixth embodiment. In FIG. 9, reference numeral 51 denotes a microcomputer (CPU), which controls the entire microcomputer device. Reference numeral 52 denotes a non-volatile memory, the entire area of which is divided into a plurality of erase unit blocks, and a non-volatile memory array block (0) to (n) which stores a microcode for each erase unit block.
A write circuit and a read circuit, an input / output buffer for buffering data input / output with respect to a data bus, and a decoder for decoding an access address. Reference numeral 53 is an interface, which serves as an interface for inputting a microcode from the outside and outputting an internal signal to the outside. Reference numeral 54 is a prohibition flag, which is a nonvolatile memory array block (0) to
It is composed of prohibition flags (0) to (n) corresponding to (n) and a decoder. Reference numeral 55 is a power-on-clear signal generating means, which generates a signal for resetting the prohibition flag when the power is turned on. Reference numeral 56 denotes a control circuit, which performs control for determining the directionality of the input / output buffer and the presence / absence of data output. Reference numeral 57 is a control signal input buffer, which buffers a control signal from the outside. An address input buffer 58 buffers an access address. Reference numeral 59 denotes a set signal setting circuit, which includes, among the memory array blocks (0) to (n), the prohibition flags (0) to (1) of the memory array blocks (0) to (1) that need to be prohibited. A signal for generating a prohibition setting by a power-on-clear signal and for canceling prohibition, for example, for prohibition flags (2) to (n) of unnecessary memory array blocks (2) to (n). To occur. In this way, it is possible to select the prohibition flag for any block that needs to be prohibited. As a selection method, the signal fixation of the set signal of the prohibition flag is set by a hard wire or a fuse means.

The operation of the microcomputer device configured as described above will be described below. In the microcomputer device of the sixth embodiment, the decoder of the non-volatile memory 52 and the decoder of the prohibition flag 54 decode the address to recognize the block for each erase unit of the non-volatile memory array and prohibit it. Reading of only the block prohibited by the flag 54 is prohibited, and the block in which the prohibition flag 54 is released enables reading and writing. In the blocks corresponding to the prohibition flags (2) to (n), the prohibition is always released, so that reading and writing can be performed without erasing.

FIG. 10 is a flowchart showing the sequence of the rewriting operation in the microcomputer device of the sixth embodiment. In the sequence shown in the flowchart of FIG. 10, first, when power is turned on, a signal from the power-on-clear signal generating means 55 is used to set data indicating read prohibition in a prohibition flag corresponding to a block that restricts access to the prohibition flag 54 (step). 110
1). Next, with respect to the block of the non-volatile memory 52 for which access is not restricted (step 1102), erase, write and read are executed (step 110).
3). Erase verify (confirmation) is executed in order to confirm whether the contents of the block whose access is restricted and which is desired to be written, for example, the block (0) is in the erased state (step 1104).

If the block (0) of the nonvolatile memory 52 is not in the erased state and it is desired to write to the block (0) (step 1107), the block (0) is set.
Is erased (step 1108), the erase verify is performed again, and when the erase verify of the block (0) is OK (step 1104), the inhibition flag (0) corresponding to the block (0) is turned off. , Read protection for block (0) is released (step 11
05).

Thereafter, the erased block (0) of the non-volatile memory 52 is subjected to normal access such as writing and reading, and the necessary microcode is written to the block (0) (step 1106). Next, for example, the erase verify of the block (1) whose access is restricted and is desired to be written is performed similarly to the case of the block (0) (steps 1109, 1112, 11).
13, 1110, 1111).

As described above, the procedure for the block (0) of the non-volatile memory 52 is repeated, the last block is accessed, and the necessary microcode is written to the last block ( Steps 1109 and 111 similar to the erase verify operation of block (1)
(2, 1113, 1110, 1111 are repeated), and the process ends.

As described above, the prohibition flag is provided so as to correspond only to the block of the non-volatile memory in which access restriction is required, and reading and writing can be performed in the block in which access restriction is not required, thereby canceling the prohibition flag. Since it suffices to perform this procedure only for blocks that require the procedure, the rewriting time of the nonvolatile memory can be shortened. (Embodiment 7) A microcomputer device according to Embodiment 7 of the present invention will be described.

FIG. 11 is a block diagram showing the configuration of the microcomputer device according to the seventh embodiment. In FIG. 11, 61 is a microcomputer (CPU),
Controls the entire microcomputer device. Reference numeral 62 denotes a non-volatile memory, the entire area of which is divided into a plurality of erase unit blocks, and a non-volatile memory array block (0) to (4) for storing a microcode for each erase unit block.
A write circuit and a read circuit, an input / output buffer for buffering data input / output with respect to a data bus, and a decoder for decoding an access address. Reference numeral 63 denotes an interface, which serves as an interface for inputting a microcode from the outside and outputting an internal signal to the outside. Reference numeral 64 is a prohibition flag, which is a nonvolatile memory array block (0) to
Blocks (0) to (4) whose access is restricted
It is composed of prohibition flags (0) to (1) corresponding to (1) and a decoder. Reference numeral 65 is a power-on clear signal generating means, which is a prohibition flag (0) when the power is turned on.
~ Reset (1). The signal for clearing the inhibit flag depends on the circuit design. Reference numeral 66 denotes a control circuit, which performs control for determining the directionality of the input / output buffer and the presence / absence of data output. A control signal input buffer 67 buffers a control signal from the outside. 68 is an address input buffer for buffering access addresses.

The operation of the microcomputer device configured as described above will be described below. In the seventh embodiment, the difference from the sixth embodiment is that the prohibition flags corresponding to the access prohibition blocks are added only to those requiring (prohibition flags (0) and (1)), and unnecessary circuits (prohibition flags are prohibited). The flags (2) to (4) are deleted, and the operation is the same as in the sixth embodiment.

As described above, the prohibition flag is provided so as to correspond only to the block of the non-volatile memory where access restriction is required, and reading and writing can be performed by eliminating the prohibition flag to the block where access restriction is not required. Since it is only necessary to perform the procedure for releasing the prohibition flag for the blocks that require the non-volatile memory, the rewriting time of the non-volatile memory is shortened, and the chip area and unnecessary circuits are deleted to reduce the manufacturing cost (small chip area, improved yield). ) Can be reduced. (Embodiment 8) A microcomputer device according to Embodiment 8 of the present invention will be described. Here, in the microcomputer devices of the above-described first to seventh embodiments, the prohibition flag is controlled to be effective when the power is turned on, regardless of the operation of the microcomputer.

The above control will be described below. FIG. 12 shows an example of the power-on clear circuit. Figure 1
In FIG. 2, reference numeral 71 is a resistor for delaying the rise when the level of the node 73 is raised to the power supply voltage when the power supply voltage is turned on, and 72 is a resistor that rises when the level of the node 73 is raised to the power supply voltage when the power supply voltage is turned on. And 74 is an inverter for shaping the waveform of the node 73.

The operation of the power-on-clear circuit configured as above will be described below. FIG. 13 shows the operation timing of the power-on-clear circuit. Power 81
Is turned on and the power supply voltage rises, but the signal 82 at the node 73 rises with a delay due to the resistor 71 and the capacitor 72. This signal is shaped as a prohibition flag set signal 83 by the waveform shaping circuit 74 which receives the signal, and the prohibition flag is enabled in the section of logic "L" to prohibit the memory access. In addition, the prohibit flag set signal 84 is generated by erasing, erasing verify operation, etc.
The prohibition flag is released during the period of T3.

As described above, by enabling the prohibition flag when the power is turned on, it is possible to prohibit the reading of the memory to the outside even if the microcomputer does not operate normally. (Ninth Embodiment) A microcomputer device according to a ninth embodiment of the present invention will be described. Here, in the microcomputer devices of the above-described first to seventh embodiments, the prohibition flag is controlled so as to be prohibited by the system reset signal for the microcomputer.

The above control will be described below. FIG. 14 shows the microcomputer device described in the seventh embodiment, which uses a system reset signal for the microcomputer as a signal for enabling the prohibition flag 94. The system reset signal is an initial state setting signal for the microcomputer to start operating in a normal state after the power is turned on. If the system reset signal is not input, external memory access under the control of the microcomputer is also impossible. Become.

As described above, by enabling the prohibition flag by using the system reset signal, it becomes possible to prohibit normal reading of the memory at the same time as the normal operation of the microcomputer. This is an effective means when the memory cannot be read out to the outside unless the microcomputer operates normally. (Embodiment 10) A microcomputer apparatus according to Embodiment 10 of the present invention will be described. Here, in the microcomputer device of the above-described first to seventh embodiments, the prohibition flag is controlled so that the prohibition flag is enabled without using the power-on-clear means regardless of the operation of the microcomputer when the power is turned on. To do.

The above control will be described below. FIG. 15 shows an example of the inhibition flag latch circuit.
In FIG. 15, 101 is a NAND constituting a latch,
Reference numeral 102 is an inverter forming a latch, 103 is a capacitance for setting the read prohibition signal 105 to the logic "L" when the power is turned on, and 104 is for setting the output of the latch to the logic "H" when the read prohibition state is released. Is a set signal of.

The operation of the latch circuit of the prohibition flag circuit configured as described above will be described below. The prohibition flag set signal 104 for releasing the read prohibition state and setting the output of the latch to the logic "H" is logic "H" when the power is turned on. On the other hand, the read inhibit signal 105 has a capacitance added by the output of the latch. Therefore, when the power is turned on, the read prohibition signal 105 rises slowly, and the output of the latch inverter 102 is set to logic "H".
By doing so, the read inhibit signal 105, which is a latch output when the power is turned on, can be set to the logic “L”.

As described above, by enabling the prohibition flag without having the power-on clear circuit when the power is turned on,
Even if the microcomputer does not operate normally, it is possible to prohibit the reading of the memory to the outside, which makes it difficult to reduce the size of the circuit and analyze it from the outside.

By combining the above-described second, fourth, and fifth embodiments, it becomes possible to debug each erase block, and since the security against reading the circuit by opening the package is high, the degree of freedom of handling for the user is high. It becomes a product with high security and high security. By diverting part of the initial information storage area as a prohibition flag and freely rewriting in the test mode, it is possible to realize a product with high flexibility for the manufacturer. it can.

[0079]

As described above, according to the present invention, for example, in response to a flag that prohibits read or write verify of the memory when the power is turned on, unless the erase of the memory is confirmed by the erase verify of the memory, the read of the memory is performed. Alternatively, by controlling so that the prohibition of write verify is not released, microcode and data in the non-volatile memory can be indirectly accessed by a third party whose ID code or memory contents are unknown. Can be made impossible, and decryption by any means by such a third party is impossible.

Therefore, it is possible to prevent illegal reading of data from the non-volatile memory and completely prevent the leakage of the memory contents to a third party who does not know the ID code or the contents of the memory. Data such as microcode written in the non-volatile memory can be reliably protected from being leaked to a person.

Further, the memory for setting the ID code for each chip becomes unnecessary, and the circuit scale can be reduced.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a microcomputer device according to a first embodiment of the present invention.

FIG. 2 is a flowchart showing a sequence of a rewriting operation in the microcomputer device of the first embodiment.

FIG. 3 is a block diagram showing a configuration of a microcomputer device according to a second embodiment of the present invention.

FIG. 4 is a flowchart showing a sequence of a rewriting operation in the microcomputer device of the second embodiment.

FIG. 5 is a flowchart showing a sequence of rewriting operation in the microcomputer device according to the third embodiment of the present invention.

FIG. 6 is a block diagram showing a configuration of a microcomputer device according to a fourth embodiment of the present invention.

FIG. 7 is a block diagram showing a configuration of a microcomputer device according to a fifth embodiment of the present invention.

FIG. 8 is a flowchart showing a sequence of a rewriting operation in the microcomputer device of the fifth embodiment.

FIG. 9 is a block diagram showing a configuration of a microcomputer device according to a sixth embodiment of the present invention.

FIG. 10 is a flowchart showing a rewriting operation sequence in the microcomputer device of the sixth embodiment.

FIG. 11 is a block diagram showing a configuration of a microcomputer device according to a seventh embodiment of the present invention.

FIG. 12 is a circuit diagram showing a configuration of a power-on-clear circuit in a microcomputer device according to an eighth embodiment of the present invention.

FIG. 13 is a timing chart showing the operation of the power-on-clear circuit in the microcomputer device of the eighth embodiment.

FIG. 14 is a block diagram showing a configuration of a microcomputer device according to a ninth embodiment of the present invention.

FIG. 15 is a circuit diagram showing a configuration of an inhibition flag latch circuit in a microcomputer device according to a tenth embodiment of the present invention.

FIG. 16 is a block diagram showing a configuration of a conventional microcomputer device.

[Explanation of symbols]

1, 11, 21, 31, 31, 51, 61, 91 Microcomputer (CPU) 2, 12, 22, 32, 52, 62, 92 Non-volatile memory 3, 13, 23, 33, 53, 63, 93 Interface 4, 14, 24, 54, 64, 94 Prohibition flag 34 Initial information register 5, 15, 25, 55, 65 Power-on-clear signal generating means 6, 16, 26, 35, 56, 66, 96 Control circuit 45 ID code memory 7, 17, 27, 36, 57, 67, 97 Control signal input buffer 8, 18, 28, 37, 58, 68, 98 Address input buffer 59 Set signal setting circuit 49 Comparator

Claims (10)

[Claims] 1. A microcomputer device equipped with a non-volatile memory for storing various data such as a microcode for operating various functions, wherein the access permission is given when controlling access to the non-volatile memory. And a control unit for controlling access to the non-volatile memory according to the state of the flag and for permitting the flag to access the non-volatile memory only after erasing the contents of the non-volatile memory. And a microcomputer device provided with. 2. The entire area of the nonvolatile memory is divided into a plurality of erase unit blocks, and a flag is configured to exist independently for each of the plurality of erase unit blocks in a one-to-one manner and control is performed. A part of the plurality of erase unit blocks is erased individually, and then the flag corresponding to the erase unit block is controlled to permit access to the erase unit block. The microcomputer device according to claim 1. 3. The control unit is configured to control the flag so as to permit access to the non-volatile memory when the data to be written in the non-volatile memory is a test pattern for inspection. 1. The microcomputer device according to 1. 4. The microcomputer device according to claim 1, wherein the control unit is composed of an FPGA using a Vt control type memory. 5. The flag is only permitted to access the non-volatile memory by a control signal stored in the chip-specific information area, and depending on the state of access to the non-volatile memory, access to the non-volatile memory is permitted. The microcomputer device according to claim 1, wherein the microcomputer device is configured so as not to cause a problem. 6. The control unit is configured so as to enable the access restriction flag only for blocks that require access restriction and to permit access for other blocks. The described microcomputer device. 7. A flag for access restriction is provided only for a block requiring access restriction, the flag is not provided for other blocks, and a control unit sets a flag for a block not provided with the flag. 7. The microcomputer device according to claim 6, wherein the microcomputer device is configured to be controlled to allow access without confirmation. 8. A power-on-clear means is provided on the same substrate or on the same package to prohibit the memory access by enabling an access prohibition flag when the power is turned on,
8. The microcomputer according to claim 1, wherein the power-on-clear means is configured to control the prohibition flag to be effective when the power is turned on regardless of the operation of the microcomputer. Computer equipment. 9. A means for prohibiting memory access by enabling an access prohibition flag based on a system reset signal for a microcomputer is provided, and the memory access prohibition means is adapted to prohibit the flag by the system reset signal. The microcomputer device according to any one of claims 1 to 7, wherein the microcomputer device is configured to be controlled by the above. 10. A means for inhibiting a memory access by enabling an access inhibition flag by using a latch, a flip-flop or the like designed such that the logical value of its output is always the same when the power is turned on is provided. 8. The microcomputer device according to any one of claims 1 to 7, wherein the access prohibiting unit is configured to control so that the flag always has the same logical value when the power is turned on to prohibit the flag.