JP3840510B2 - Micro computer - Google Patents

Description

  The present invention is a single-chip type having a built-in ROM that can be electrically written or erased, such as micro computer technology, and also an EEP-ROM (electrically erasable and programmable read only memory). The present invention relates to a technology that is effective when applied to a microcomputer. For example, the present invention relates to a technology that is effective when used for a microcomputer built in an IC card.

  Recently, so-called IC cards have attracted attention as an alternative to magnetic cards. This IC card is, for example, a P-ROM (ultraviolet erasable programmable ROM) in which data such as an ID (identification code) is stored, as described in Patent Document 1 (Japanese Patent Publication No. 56-19665). ) Can be made to function as an identification card instead of a key, for example.

  Here, the present inventor has studied an EEP-ROM built-in type single chip microcomputer suitable for being built in an IC card as described above, for example. The following is not a publicly known technique, but is a technique examined by the present inventor, and its outline is as follows.

  FIG. 6 shows a configuration of the microcomputer 10 examined by the present inventor. The microcomputer 10 shown in the figure is a single chip type with a built-in EEP-ROM, and includes a CPU (central processing unit) 1, a RAM (random access memory) 2, a mask ROM (fixed storage ROM) 3, and an EEP-ROM. ROM 41, 42, I / O (input / output unit) 5, peripheral circuit 6, EEP-ROM write control circuit 7 and the like are provided in the same semiconductor chip. Each part (1-7) is mutually connected by the address bus LA and the data bus LD.

  This single-chip type microcomputer 10 is used by being built in, for example, an IC card. As shown in FIG. 7, the exchange of data Dx with the outside is all performed via the CPU 1. FIG. 7 shows the microcomputer 10 shown in FIG. 6 while paying attention to the flow of data Dx. The microcomputer 10 can be configured such that the built-in software cannot be known unless a “key” by appropriate software is used, so that the microcomputer 10 is appropriate as a single-chip microcomputer incorporated in the IC card. ing.

  Here, two equivalent EEP-ROMs 41 and 42 are provided independently of each other. As shown in FIG. 8, one EEP-ROM 41 is used as a so-called user program area (M1). Here, a program arbitrarily created by the user is written in advance. The program is written to the EEP-ROM 41 directly from the outside by stopping the CPU 1 under the control from the outside. Such a P-ROM programming method is known, for example, from Non-Patent Document 1 (Hitachi, Ltd., August 1984 "Hitachi Microcomputer Data Book 8-bit Single Chip" pages 823-865). This eliminates the need to rewrite the mask ROM in the manufacturing process, and can immediately respond to various applications of the user. Furthermore, if a configuration having a means for prohibiting rewriting or reading of the EEP-ROM after the EEP-ROM 41 is programmed is effective in protecting the built-in software. The other EEP-ROM 42 is used as a data area (M2). Here, of the input / output data managed by the CPU 1, data Dx that needs to be saved is written as needed. Writing to the EEP-ROM 42 is performed via a write control circuit 7 controlled by the CPU 1. Generally, the time required for writing to the EEP-ROM is about 1000 times the average instruction execution time of the CPU. During this writing period, the EEP-ROM 42 is electrically disconnected from the CPU 1 and Both reading and writing are impossible.

  On the other hand, the CPU 1 executes a predetermined processing operation while reading the user program Ix2 written in the program storing EEP-ROM 41 one instruction at a time. When it is necessary to write the storage-required data Dx to the data storage EEP-ROM 42 in the course of the processing operation, the writing to the EEP-ROM 42 is performed via the EEP-ROM write control circuit 7. I do. When executing this processing operation, a program routine (or program module) prepared as a standard program Ix1 in advance in the mask ROM 3 is appropriately referred to. The program routine is, for example, a software timer or division program, and useful programs are prepared for many uses or applications. In general, a mask ROM can be realized with a smaller area than an EEP-ROM having the same capacity. For this reason, it is possible to reduce the size of the entire semiconductor chip by using the ROM 3 without storing all the programs in the EEP-ROM 41.

  However, the overall processing is performed according to the user program written in the EEP-ROM 41.

  The EEP-ROM write control circuit 7 as shown in FIG. 7 performs a write operation to the other EEP-ROM 42 while receiving control based on a program written to one EEP-ROM 41, for example. The other EEP-ROM 42 is disconnected from the CPU 1 while writing is being performed.

As described above, the microcomputer 10 that can immediately respond to various specification requirements and various uses of the user and can semi-permanently store the data Dx in the EEP-ROM as necessary. It is configured.
Japanese Patent Publication No.56-19665 Hitachi, Ltd., August 1984 "Hitachi Microcomputer Data Book 8-bit Single Chip" pages 823-865

  However, the inventor has revealed that the above-described technique has the following problems.

  That is, in the microcomputer 10 described above, two EEP-ROMs 41 and 42 that are independent from each other are required to write the user program Ix2 and to store the necessary data Dx. This is because if there is only one EEP-ROM, read access to the EEP-ROM cannot be performed while writing to the EEP-ROM, and instructions to be executed by the CPU 1 cannot be read. Therefore, as described above, the program and data are stored in the two independent EEP-ROMs 41 and 42, and the instruction is read from one EEP-ROM 41, while the other EEP-ROM 42 is based on the read instruction. Had to be configured to perform write control.

  However, in order to do so, two EEP-ROMs 41 and 42 that are independent from each other are required, and each EEP-ROM 41 and 42 can cope with various specification requirements from users in various directions. It must be possible to prepare sufficiently large storage areas M1 and M2. For example, in order to be able to cope with any of two types of requests such as a small data size but a large program size, or a small program size but a large data size, 2 Both the storage capacities of the two EEP-ROMs 41 and 42 must be increased. Furthermore, even if both the storage capacities of the two EEP-ROMs 41 and 42 are both increased, it is easy to waste that either one of them has a large storage capacity and cannot be used effectively.

  Each of the EEP-ROMs 41 and 42 has a memory array and a peripheral circuit including a circuit for data input / output, such as a sense amplifier and a driver circuit, and a circuit for selecting an address. Therefore, when a plurality of EEP-ROMs are independently formed, peripheral circuits such as a sense amplifier and a driver are provided in each EEP-ROM, so that many circuit elements are required. Accordingly, the entire size of the EEP-ROM has to be increased.

  Therefore, the inventor stores a program for controlling the EEP-ROM 42 in the EEP-ROM 41 and stores data to be referred to by the program in the EEP-ROM 42, and stores the data in the EEP-ROM 42 in the EEP-ROM 42. It was also considered to store data referred to by the program of the EEP-ROM 41 together with the control program. In this way, the program storage area and the data storage area in each of the EEP-ROMs 41 and 42 can be made variable. In this case, the memory area or size problem as described above is somewhat mitigated. However, even in this case, each EEP-ROM 41 and 42 has a peripheral circuit such as a sense amplifier and a decoder circuit independent from each other. The disadvantage is not fully eliminated.

  As described above, the above-described microcomputer can immediately respond to various specification requirements and various uses of the user, and can store the data Dx semi-permanently in the EEP-ROM as necessary. However, two independent EEP-ROMs 41 and 42 each having a sufficiently large storage capacity are required. For this reason, the hardware configuration burden is large, especially in the case of a single chip type, the semiconductor chip size is inevitably large, and the utilization efficiency of hardware resources is not necessarily good. It has been clarified for the first time by the present inventor that there is a problem. In particular, when the semiconductor chip is built in an IC card, there is a strong demand for reducing the size of the semiconductor chip in order to improve the card strength, and the above semiconductor chip is contrary to this.

  The object of the present invention is to provide the above-mentioned advantages of the microcomputer, that is, to meet the various specification requirements and various uses of the user immediately and to store the data semi-permanently in the EEP-ROM as needed. It is an object of the present invention to provide a technology that allows the hardware configuration scale to be reduced and the utilization efficiency of hardware resources to be increased while retaining the advantage of being able to perform the above-described process. In particular, as in the case of incorporating a ROM that can be electrically written (or erased) such as an EEP-ROM that has a longer writing or erasing time than the processing speed of the CPU or a large variation in element characteristics, The present invention provides a technique capable of realizing high-speed and reliable writing suitable for element characteristics, and shortening the writing time and further shortening the response time.

  Of the inventions disclosed in this application, the outline of typical ones will be briefly described as follows.

  That is, the microcomputer of the present invention includes a central processing unit (CPU), a mask ROM having an area for storing a first program executed by the central processing unit, a second program and data executed by the central processing unit. And an electrically writable and erasable ROM (EEP-ROM or the like) having a region for storing the data, and a RAM, and the first program writes data prepared in the RAM into the ROM. The second program has an instruction to jump to the first program.

  Further, according to another microcomputer of the present invention, the second program shifts to a process for the central processing unit to write data to the electrically writable and erasable ROM by the first program. After the first program having the instruction has completed the process of writing data to the electrically writable and erasable ROM, the central processing unit proceeds to the execution of the second program. The central processing unit having an instruction to return or having a flag determines completion of writing of data into the electrically writable and erasable ROM based on the flag In addition, the central processing unit has a combination of features such as returning to the execution of the second program based on the determination result.

  Another microcomputer of the present invention is an electrically writable and erasable memory having a central processing unit (CPU), a storage area for programs executed by the central processing unit, and a data storage area. ROM (EEP-ROM, etc.), storage means (mask ROM, RAM, etc.) having an area for storing a write control program for writing to the electrically writable and erasable ROM, and input / output The central processing unit is provided in a storage area for the program in the electrically writable and erasable ROM based on the write control program. The program received from outside the microcomputer is written via the entry / output means and stored in the electrically writable / erasable ROM. Program is one that the central processing unit has an instruction to shift to the processing for writing a program to the electrically writing and erasable ROM by the write control program.

  Furthermore, another microcomputer of the present invention is configured so that the central processing unit performs the electrical control after the write control program has completed the process of writing the program to the electrically writable and erasable ROM. The central processing unit having a flag having an instruction for returning to the execution of the program stored in the ROM that can be written to and erased from is electrically written based on the flag. And determining completion of the program writing process to the erasable ROM, and the central processing unit returns to the execution of the program stored in the electrically writable and erasable ROM based on the determination result. The storage means is a RAM which has received the transfer of the write control program from the electrically writable and erasable ROM, or the electrically writable and erasable It has a combination of features such as writing a program or data in the program storage area or data storage area of the ROM, and having an instruction to shift to processing for writing the program or data. is there.

  Therefore, according to the microcomputer, when data is written in the writable ROM, only when that is the case, the CPU jumps to another storage device and executes a predetermined write control program stored in the CPU. By doing so, it is possible to cause the CPU to execute a predetermined write control process even during a write operation to the writable ROM. As a result, the user program area and the data area can be placed in one writable ROM, and the ratio of the size of each area can be arbitrarily selected. As a result, the hardware configuration scale can be reduced while maintaining the advantages of being able to immediately respond to various specifications requirements of the user and storing data in the ROM semi-permanently as needed. The objective of enabling and improving the utilization efficiency of hardware resources is achieved. In particular, by controlling the writing (or erasing) of the ROM by manipulating the flag by the control program, high-speed and reliable writing suitable for the element characteristics can be realized, shortening the writing time and further response Time can be shortened.

  The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

  In other words, the microcomputer with built-in EEP-ROM can immediately respond to various specifications requirements and various uses of users.

  DESCRIPTION OF EXEMPLARY EMBODIMENTS Hereinafter, preferred embodiments of the invention will be described with reference to the drawings. In each figure, the same numerals indicate the same or corresponding parts.

  FIG. 1 shows an embodiment of the main part of a microcomputer 10 to which the technology according to the present invention is applied.

  The microcomputer 10 which shows the main part in the figure is of a single chip type, and is provided with an EEP-ROM 4 in which both the user program Ix2 and required storage data are written at an arbitrary ratio together with the CPU 1. Along with this, a so-called mask ROM 3 in which a write control program for writing to the EEP-ROM 4 is fixedly stored in advance as a part of the standard program Ix1 is provided.

  The mask ROM 3 may store only the write control program, or may further store the standard program routine described above. Here, the write control program includes, for example, a program for starting up the write control circuit 7 or a program for detecting the end of writing. Further, when there is a large amount of write data, data prepared in a predetermined area in the RAM 2 may be sequentially transferred to the EEP-ROM 4 for writing. Further, the EEP-ROM 4 and the mask ROM 3 are arranged at different address positions on the address space of the CPU 1. Here, the switch in FIG. 1 is virtual, and when the execution program of the CPU 1 is written to the EEP-ROM 4, it is transferred to the mask ROM 3 by a call command, and after returning to the EEP-ROM 4 by a return command. It is shown.

  In this case, a call instruction to a specific routine in the mask ROM 3 is written in the EEP-ROM 4 instead of the write control program for the EEP-ROM 4. On the other hand, in the mask ROM 3, a return command to the EEP-ROM 4 is written at the end of the write control program together with a write control program for the EEP-ROM 4.

  FIG. 2 shows an embodiment of the overall configuration of the microprocessor 10 shown in FIG.

  As shown in the figure, in addition to the above-described components, that is, the CPU 1, the mask ROM 3, and the EEP-ROM 4, the microcomputer 10 receives the RAM 2 that provides the work area of the CPU 1, and the data Dx to the outside. An I / O (input / output unit) 5, a peripheral circuit 6, an EEP-ROM write control circuit 7 and the like are built in. By incorporating these, the suitability of a single-chip microcomputer incorporated in, for example, an IC card is given. Each part (1-7) in the microcomputer 10 is mutually connected by an address bus LA and a data bus LD. Control signals for each memory and peripheral circuit are omitted.

  FIG. 3 shows the microcomputer 10 shown in FIG. 2 focusing on the flow of data Dx. As shown in the figure, the exchange of data Dx with the outside is all performed via the CPU 1. Thus, it is possible to adopt a configuration in which the built-in software cannot be known unless a “key” by appropriate software is used.

  FIG. 4 shows three examples of the state of the address space of the CPU 1 by a memory map. As shown in the figure, both the user program area M1 and the data area M2 are allocated at an arbitrary ratio in the storage area M of the EEP-ROM 4.

  FIG. 5 is a flowchart showing an example of processing operation when the CPU 1 controls writing to the EEP-ROM 4.

  In FIG. 2, the CPU 1 executes a predetermined processing operation while reading the program Ix2 written in the user program area M1 one instruction at a time (step S6).

  Here, if it is necessary to write the required storage data Dx into the EEP-ROM 4 in the course of the processing operation (step S1), the CPU 1 writes in the standard program area Ix1 stored in the mask ROM 3 by a call instruction. Jump to the start address of the control program (step S2). Then, the writing control process of the EEP-ROM 4 is executed according to the writing control program (step S3). As a result, writing to the EEP-ROM 4 is performed via the EEP-ROM write control circuit 7. While this writing is being performed, the EEP-ROM 4 is disconnected from the CPU 1.

  Thereafter, when the writing is completed, the CPU 1 determines the completion of the writing based on, for example, a flag or an interrupt request issued from the write control circuit 7 side (step S4). Then, the CPU 1 returns from the mask ROM 3 to the program area M1 of the EEP-ROM 4, and resumes reading of the user program from the address next to the address at the time of jump (step S5). Then, the user program in the EEP-ROM 4 is executed until the end of processing or the next data write request is generated (step S6).

  As described above, the user program area M1 and the data area M2 can be placed in one EEP-ROM 4. At the same time, since the ratio of the sizes of both areas M1 and M2 can be arbitrarily selected, even if the size of the storage area M of the entire EEP-ROM is not so large, for example, as shown in FIG. The storage area M can be interchanged, such as increasing the size of the program area M1 instead of reducing the size of the data area M2, or increasing the size of the data area M2 instead of reducing the size of the program area M1. It can be used efficiently.

  As a result, it is possible to immediately respond to various uses of the user, and to maintain the advantage that the data Dx can be stored semi-permanently in the EEP-ROM 4 as necessary, while having a hardware configuration scale. The purpose of enabling the reduction of the hardware resources and improving the utilization efficiency of the hardware resources is achieved.

  Here, the return to the user program when the writing of the EEP-ROM is completed may not be based on the flag or the interrupt request issued from the write control circuit 7 as in the embodiment. For example, an appropriate work register in the CPU 1 is used as a kind of counter or timer which starts operating simultaneously with the start of the writing operation to the EEP-ROM and is updated at a constant period during the operation. The return operation may be executed when the content of the file reaches a predetermined value. That is, the CPU 1 may measure a predetermined required write time that is expected in advance, and check the completion of the writing operation to the EEP-ROM by software when the time is completed. In this case, the setting of the writing time and the control of the subsequent return operation may be performed in hardware by a dedicated circuit such as a timer circuit.

  In the example described above, the user program is not particularly limited, but is configured to stop the CPU 1 by external control and directly write to the user program area M1 of the EEP-ROM 4 from the outside.

  The user program may be written in such a manner that the CPU 1 receives the program from the outside via the I / O unit 5 according to the program in the mask ROM 3 and sequentially writes it in the user program area M 1 of the EEP-ROM 4. In this example, since there is no means for directly accessing the built-in EEP-ROM 4 from the outside, the security protection function is strengthened, and the suitability as a single-chip type microcomputer built in the IC card can be increased. it can.

  In this case, whether or not writing to the user program 4 has already been performed may be determined in a state having a flag in the EEP-ROM 4. The start address after resetting the CPU 1 may be changed according to the state of the flag.

  As a writable ROM, not only an electrically writable and erasable ROM such as an EEP-ROM but also an ultraviolet erasable EP-ROM can be used.

  In the above example, although not particularly limited, writing is performed by the writing control circuit 7 and writing is performed for a predetermined time.

  In the case of EP-ROM, writing time is generally longer than that of EEP-ROM. For this reason, when the writing time is constant as described above, if the IC card is built in, the response time increases. Here, since the process variation of the EP-ROM element is large, the writing time is set in consideration of the worst case, and in many cases, the writing time is consumed more than necessary.

  Therefore, the present inventor has considered that the CPU 1 is activated with respect to the write control circuit 7 and can be stopped. That is, a flag PGM is provided in the write control circuit 7, and writing is started when the flag PGM is set by the CPU 1, and writing is ended when the flag is reset. The write time may be measured by software, for example, as described above, or may be used if a timer circuit is incorporated.

  FIG. 9 is a flowchart showing an embodiment of a write control program to be stored in the mask ROM 3 in the above case.

  First, the CPU 1 sets write address data for the EP-ROM, and the EP-ROM latches them (step S1). Next, the CPU 1 clears the contents of the specific register N (step S2), adds +1 to the register N (step S3), and then sets the flag PGM (step S4). Time is measured for a predetermined unit time, for example, 1 ms (step S5), after which the flag PGM is reset (step S6), and the writing of the unit time is terminated.

  Thereafter, it is determined whether or not writing has been correctly performed (step S7). This determination is performed by reading the EP-ROM and comparing the read contents with the write data. Although not particularly limited, the latched data is not destroyed at the time of reading. If the comparison result does not match, the CPU 1 determines the value of the register N (step S11), and if it is 24 or less, the CPU 1 returns to step S3 and executes unit time writing again. Even if the writing of the unit time is performed 25 times, that is, even if N = 25, if it does not match, it is determined as defective (step S12), and the process ends.

  If the result of the determination is coincident, the CPU 1 sets the flag PGM (step S8), further measures the time of 3 × Nms (step S9), clears the flag PGM (step S10), and ends. . That is, the overwriting is performed for a time three times the time Nms required until the above determination results match.

  As a result, high-speed and reliable writing suitable for the element characteristics can be realized, and the writing time can be shortened and further the response time can be shortened.

  With the above-described method, it is possible to immediately respond to various specification requirements and various uses of the user, and to have the advantage that the data Dx can be semi-permanently stored in the EP-ROM as necessary. The hardware configuration scale can be reduced, the utilization efficiency of hardware resources can be increased, and the response time can be shortened.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the above embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say. For example, a write control program is stored in advance in the mask ROM 3 or EEP-ROM 4, and when the write operation of the EEP-ROM 4 is performed, the stored write control program is transferred to the RAM 2 and executed by the CPU 1. It may be configured.

  Further, the case where the present invention is applied to a single chip type microcomputer for IC card has been described, but the present invention is not limited thereto, and can be applied to, for example, a board type microcomputer.

  The present invention can be applied at least to a condition where both the program and data are stored in the EEP-ROM.

1 is a block diagram showing a main part of an EEP-ROM built-in microcomputer to which a technique according to the present invention is applied; FIG. FIG. 2 is a block diagram showing an overall configuration of the microcomputer shown in FIG. 1. FIG. 3 is a block diagram showing the microcomputer shown in FIG. 2 focusing on the data flow. 3 is an address map illustrating three states of the address space of the CPU in the microcomputer shown in FIG. 3 is a flowchart showing an operation example of the microcomputer shown in FIG. 2. 1 is a block diagram showing a configuration of an EEP-ROM built-in type microcomputer studied prior to the present invention. FIG. FIG. 7 is a block diagram showing the microcomputer shown in FIG. 6 focusing on the data flow. 7 is an address map illustrating the state of the address space of the CPU in the microcomputer illustrated in FIG. 6. It is a flowchart which shows the write-in control program at the time of incorporating EP-ROM.

Explanation of symbols

1 CPU
2 RAM
3 Mask ROM
4, 41, 42 EEPROM-ROM
5 I / O
6 Peripheral circuit 7 Write control circuit 10 Microcomputer

Claims (4)

A central processing unit;
A non-volatile memory having a program area and a data area for storing a program executed by the central processing unit, and electrically writable and erasable;
RAM,
An input / output circuit capable of inputting / outputting data from / to the outside;
The nonvolatile memory and the RAM are arranged in different address spaces,
The nonvolatile memory stores a write control program for performing writing,
The write control program can be transferred to the RAM,
The central processing unit can write data input via the input / output circuit to the nonvolatile memory by executing the write control program transferred to the RAM. Micro computer. The central processing unit is further capable of writing the data stored in the RAM into the nonvolatile memory by executing the write control program transferred to the RAM. 2. The microcomputer according to 1 . A central processing unit;
An input / output circuit capable of inputting and outputting data from the outside;
Storing a program and data executed by the central processing unit, and having a memory allocated to an address space accessible by the central processing unit,
The memory has a first address space to which a nonvolatile memory is allocated, and a second address space to which a volatile memory is allocated,
The first address space stores a write control program for performing write control of data and programs to the nonvolatile memory,
When performing a write operation of the nonvolatile memory, the write control program is stored in the second address space, and the central processing unit executes the write control program stored in the second address space The central processing unit executes the write control program stored in the second address space by performing the write operation of the data input via the input / output circuit. A microcomputer capable of writing data stored in an address space into the first address space . A central processing unit;
An input / output circuit capable of inputting and outputting data from the outside;
A non-volatile memory having a program area and a data area for storing a program executed by the central processing unit, and electrically writable and erasable;
RAM,
The nonvolatile memory and the RAM are arranged in an address space accessible by the central processing unit,
The nonvolatile memory stores a writing control program for performing writing control of the nonvolatile memory,
Data or a program written to the nonvolatile memory based on the execution of the write control program is data input via the input / output circuit or stored in the RAM,
When performing write control on the nonvolatile memory, the write control program is stored in the RAM, and the central processing unit executes the write control program stored in the RAM, thereby writing the data. A microcomputer characterized in that it is possible to carry out the control of the recording .

Images