JP2004094981A - Microcomputer - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a microcomputer, which responds immediately to various specification requirements and various applications from a user, has an advantage of storing data in an EEP-ROM almost permanently as needed, reduces a structure and scale of hardware in use, improves usability of a hardware resource, securely performs high-speed writing according to an element characteristic, and reduces writing time and response time. <P>SOLUTION: The microcomputer 10 of a single chip type has a CPU1, and an EEP-ROM4 in which a user program and data needed to be stored are written in an arbitrary rate, in the main part. The microcomputer 10 further includes a mask ROM3 previously storing a write control program for writing in the EEP-ROM4 as a part of a standard program. <P>COPYRIGHT: (C)2004,JPO

Description

The present invention relates to a microcomputer technology and a single-chip type having a built-in electrically erasable or erasable ROM such as an EEP-ROM (Electrically Erasable and Programmable Read Only Memory). The present invention relates to a technology that is effective when applied to a microcomputer, for example, a technology that is effective to be used for a microcomputer built in an IC card.

Recently, so-called IC cards have been attracting attention as an alternative to magnetic cards and the like. This IC card is a P-ROM (ultraviolet erasable programmable ROM) storing data such as an ID (identification code) as described in, for example, Patent Document 1 (Japanese Patent Publication No. 56-19665). ) Can function as, for example, an identification card instead of a key.

Here, the present inventor has studied a single-chip microcomputer with an EEP-ROM built-in suitable for being built in an IC card as described above, for example. The following is not a known technique, but is a technique studied by the present inventor, and its outline is as follows.

FIG. 6 shows the configuration of the microcomputer 10 studied by the present inventor. The microcomputer 10 shown in FIG. 1 is a single-chip type with a built-in EEP-ROM, and includes a CPU (central processing unit) 1, a RAM (random access memory) 2, a mask ROM (fixed storage ROM) 3, and an EEP-ROM. ROMs 41 and 42, an I / O (input / output unit) 5, a peripheral circuit 6, an EEP-ROM write control circuit 7, and the like are provided in the same semiconductor chip. Each part (1 to 7) is mutually connected by an address bus LA and a data bus LD.

This single-chip microcomputer 10 is used, for example, built in an IC card. As shown in FIG. 7, the exchange of data Dx with the outside is all performed via the CPU 1. FIG. 7 shows the microcomputer 10 shown in FIG. 6 focusing on the flow of data Dx. This microcomputer 10 can be configured so that the built-in software cannot be known unless a "key" made of appropriate software is used, so that the microcomputer 10 is suitable as a single-chip microcomputer built in an IC card. ing.

Here, two EEP-ROMs 41 and 42 are provided independently of each other. Then, as shown in FIG. 8, one EEP-ROM 41 is used as a so-called user program area (M1). Here, a program arbitrarily created by the user is written in advance. The writing of this program is performed by stopping the CPU 1 by external control and directly writing to the EEP-ROM 41 externally. Such a P-ROM programming method is known, for example, from Non-Patent Document 1 (Hitachi, Ltd., "Hitachi Microcomputer Data Book 8-bit Single Chip", pp. 823-865, issued August 1984). This eliminates the need to rewrite the mask ROM in the manufacturing process, and can immediately respond to various applications of the user. Furthermore, if a configuration is provided which enables prohibition of rewriting or reading of the EEP-ROM after the program for the EEP-ROM 41 has been executed, there is an effect as protection of the built-in software. The other EEP-ROM 42 is used as a data area (M2). Here, of the input / output data managed by the CPU 1, data Dx that needs to be stored is written as needed. Writing to the EEP-ROM 42 is performed via a write control circuit 7 controlled by the CPU 1. Generally, the time required for writing to the EEP-ROM is about 1000 times as long as the average instruction execution time of the CPU. During this writing period, the EEP-ROM 42 is electrically disconnected from the CPU 1 and Both reading and writing are disabled.

On the other hand, the CPU 1 executes a predetermined processing operation while reading the user program Ix2 written in the program storage EEP-ROM 41 one instruction at a time. Then, when it becomes necessary to write the storage-necessary data Dx into the data storage EEP-ROM 42 in the course of the processing operation, the data is written into the EEP-ROM 42 via the EEP-ROM write control circuit 7. I do. When executing this processing operation, a program routine (or a program module) prepared in advance as a standard program Ix1 in the mask ROM 3 is referred to as appropriate. The program routine is, for example, a software timer or a division program, and useful programs are prepared for many uses or applications. Generally, a mask ROM can be realized with a smaller area than an EEP-ROM having the same capacity. Therefore, by using the ROM 3 without storing all programs in the EEP-ROM 41, the size of the entire semiconductor chip can be reduced.

However, the overall processing is performed according to the user program written in the EEP-ROM 41.

(7) The EEP-ROM write control circuit 7 as shown in FIG. 7 performs a write operation to the other EEP-ROM 42 while receiving control based on a program written in one EEP-ROM 41, for example. The other EEP-ROM 42 is disconnected from the CPU 1 while writing is being performed.

As described above, the microcomputer 10 which can immediately respond to various specification requirements and various applications of the user and can semi-permanently store the data Dx in the EEP-ROM as necessary is provided. It is configured.
JP-B-56-19665 Hitachi, Ltd., "Hitachi Microcomputer Data Book 8-bit Single Chip," August 1984, pp. 823-865.

However, it has been clarified by the present inventors that the above-described technology has the following problems.

That is, in the above-described microcomputer 10, two independent EEP-ROMs 41 and 42 are required for writing the user program Ix2 and for storing the storage required data Dx. This is because if only one EEP-ROM is used, read access to the EEP-ROM cannot be performed while writing to the EEP-ROM, and the instruction to be executed by the CPU 1 cannot be read. Therefore, as described above, the program and the data are stored in the two independent EEP-ROMs 41 and 42, and while the instruction is read from one EEP-ROM 41, the other EEP-ROM 42 is read based on the read instruction. Must be configured to execute the write control.

However, for this purpose, two EEP-ROMs 41 and 42 independent of each other are required, and each EEP-ROM 41 and 42 needs to be capable of responding to various requirements from users in various fields. The storage areas M1 and M2 must be able to be prepared in each case. For example, in order to be able to cope with any of two kinds of requests such as a small data size and a large program size, or a small program size and a large data size, after all, 2 The storage capacity of each of the two EEP-ROMs 41 and 42 must be increased. Further, even if both of the storage capacities of the two EEP-ROMs 41 and 42 are both increased, it is easy to cause a waste that one of the storage capacities is too large to be used effectively.

Each of the EEP-ROMs 41 and 42 has a memory array as well as peripheral circuits including a circuit for data input / output such as a sense amplifier and a driver circuit and a circuit for selecting an address. Therefore, when a plurality of EEP-ROMs are independently formed, peripheral circuits such as a sense amplifier and a driver are provided in each EEP-ROM, so that many circuit elements are required. Accordingly, the overall size of the EEP-ROM has to be increased.

Therefore, the present inventor stores a program for controlling the EEP-ROM 42 in the EEP-ROM 41 and stores data to be referred to by the program in the EEP-ROM 42, and stores the program of the EEP-ROM 41 in the EEP-ROM 42. It has been considered to store data referred to by the program of the EEP-ROM 41 together with the control program. This makes it possible to change the program storage area and the data storage area in each of the EEP-ROMs 41 and 42. In this case, the above-mentioned problems regarding the memory area or size are somewhat alleviated. However, even in this case, since each of the EEP-ROMs 41 and 42 has a peripheral circuit such as a sense amplifier and a decoder circuit which are independent of each other, the size of the entire EEP-ROM or the size of the entire semiconductor chip can be reduced. The disadvantages are not fully eliminated.

As described above, in the above-described microcomputer, it is possible to immediately respond to various specification requirements and various applications of the user, and to semi-permanently store the data Dx in the EEP-ROM as necessary. However, two independent EEP-ROMs 41 and 42 each having a sufficiently large storage capacity are required. For this reason, the hardware configuration burden is large, especially in the case of a single chip type, the semiconductor chip size is inevitably increased, and the utilization efficiency of hardware resources is not always good for that. The present inventor has clarified for the first time that there is a problem. In particular, when the semiconductor chip is incorporated in an IC card, there is a strong demand to reduce the size of the semiconductor chip in order to improve the card strength, and the above-mentioned semiconductor chip is contrary to this.

SUMMARY OF THE INVENTION An object of the present invention is to provide an advantage of the microcomputer described above, that is, it is possible to immediately respond to various specification requirements and various applications of a user, and to store data in an EEP-ROM semi-permanently when necessary. It is an object of the present invention to provide a technique capable of reducing the size of a hardware configuration and increasing the use efficiency of hardware resources while maintaining the advantage that the hardware resources can be used. In particular, as in the case where an electrically writable (or erasable) ROM such as an EEPROM such as an EEP-ROM having a large variation in element characteristics is built in, the writing or erasing time is longer than the processing speed of the CPU. An object of the present invention is to provide a technique capable of realizing high-speed and reliable writing suited to element characteristics, shortening the writing time, and shortening the response time.

の う ち The following is a brief description of an outline of typical inventions disclosed in the present application.

That is, a microcomputer according to the present invention includes a central processing unit (CPU), a mask ROM having an area for storing a first program executed by the central processing unit, a second program executed by the central processing unit, and data. An electrically writable and erasable ROM (such as an EEP-ROM) having an area for storing data and a RAM, and the first program is for writing data prepared in the RAM to the ROM. The second program has an instruction to jump to the first program.

Further, in another microcomputer of the present invention, the second program shifts to processing for the central processing unit to write data in the electrically writable and erasable ROM by the first program. After the first program has completed the process of writing data to the electrically writable and erasable ROM, the central processing unit starts executing the second program. The central processing unit having an instruction for returning, or having a flag, determines, based on the flag, completion of the process of writing data to the electrically writable and erasable ROM. The central processing unit has a combination of features such as returning to the execution of the second program based on the determination result.

Another microcomputer according to the present invention includes a central processing unit (CPU), a storage area for a program executed by the central processing unit, and a storage area for data. ROM (EEPROM, etc.), storage means (mask ROM, RAM, etc.) having an area for storing a write control program for writing in the electrically writable and erasable ROM, Means (I / O), the central processing unit stores the program in a storage area of the program in the electrically writable and erasable ROM based on the write control program. Writes the program received from outside the microcomputer via the entry / output means and stores it in the electrically writable / erasable ROM Programs are those in which the central processing unit has an instruction to shift to the processing for writing a program to the electrically writing and erasable ROM by the write control program.

Further, in another microcomputer of the present invention, after the write control program completes the process of writing the program into the electrically writable and erasable ROM, the central processing unit executes A central processing unit having an instruction for returning to the execution of a program stored in a writable and erasable ROM, the central processing unit having a flag, And the completion of the process of writing the program into the erasable ROM is determined, and the central processing unit returns to the execution of the program stored in the electrically rewritable ROM based on the determination result. The storage means is a RAM that receives the transfer of the write control program from the electrically writable and erasable ROM, or the electrically writable and erasable ROM is A combination of features such as writing a program or data in a storage area of the above-mentioned program or the above-mentioned data in a simple ROM and having an instruction to shift to processing for writing the program or data. It is.

Therefore, according to the microcomputer, when writing data to the writable ROM, the CPU is jumped to another storage device only at that time, and the predetermined write control program stored in advance is executed. This allows the CPU to execute a predetermined write control process even during a write operation to the writable ROM. Thus, the user program area and the data area can be placed in one writable ROM, and the size ratio of each area can be arbitrarily selected. As a result, it is possible to immediately respond to various specification requirements of the user, and to maintain the advantage that data can be semi-permanently stored in the ROM as needed, while reducing the hardware configuration scale. The object of the present invention is made possible, and the utilization efficiency of hardware resources can be improved. In particular, by controlling the writing (or erasing) of the ROM by operating the flag by the control program, it is possible to realize high-speed and reliable writing according to the element characteristics, shorten the writing time, and further reduce the response time. Time can be reduced.

効果 Of the inventions disclosed in the present application, the effects obtained by typical ones will be briefly described as follows.

That is, in the microcomputer with the built-in EEP-ROM, it is possible to immediately respond to various specification requirements and various applications of the user.

Hereinafter, preferred embodiments of the present invention will be described with reference to the drawings. In the drawings, the same reference numerals indicate the same or corresponding parts.

FIG. 1 shows an embodiment of a main part of a microcomputer 10 to which the technology according to the present invention is applied.

The microcomputer 10 whose main part is shown in FIG. 1 is of a single-chip type, and includes a CPU 1 and an EEP-ROM 4 in which both a user program Ix2 and data to be stored are written at an arbitrary ratio. In addition, a so-called mask ROM 3 in which a write control program for writing to the EEP-ROM 4 is fixedly stored in advance as a part of the standard program Ix1 is provided.

The mask ROM 3 may store only the write control program, or may store the standard program routine described above. Here, the write control program includes, for example, a program for starting the write control circuit 7 or a program for detecting the end of writing. Further, when the amount of write data is large, data prepared in a predetermined area in the RAM 2 may be sequentially transferred to the EEP-ROM 4 for writing. Further, the EEP-ROM 4 and the mask ROM 3 are respectively arranged at different address positions in the address space of the CPU 1. Here, the switch in FIG. 1 is virtual, and it is assumed that the execution program of the CPU 1 moves to the mask ROM 3 by a call command when writing to the EEP-ROM 4 and returns to the EEP-ROM 4 by a return command after the writing is completed. It is shown.

In this case, in the EEP-ROM 4, a call instruction to a specific routine in the mask ROM 3 is written instead of the write control program for the EEP-ROM 4. On the other hand, in the mask ROM 3, together with a write control program for the EEP-ROM 4, a return command to the EEP-ROM 4 is written at the end of the write control program.

FIG. 2 shows an embodiment of the overall configuration of the microprocessor 10 shown in FIG.

As shown in FIG. 1, in addition to the above-mentioned components, that is, the CPU 1, the mask ROM 3, and the EEP-ROM 4, the RAM 2, which provides a work area for the CPU 1, and the transfer of data Dx to the outside, (Input / output unit) 5, a peripheral circuit 6, an EEP-ROM write control circuit 7, and the like. By incorporating them, for example, it is made suitable as a single-chip microcomputer incorporated in an IC card. Each section (1 to 7) in the microcomputer 10 is mutually connected by an address bus LA and a data bus LD. Control signals for each memory and peripheral circuits are omitted.

FIG. 3 shows the microcomputer 10 shown in FIG. 2 focusing on the flow of data Dx. As shown in FIG. 1, the exchange of data Dx with the outside is all performed via the CPU 1. This makes it possible to adopt a configuration in which the built-in software cannot be known unless a “key” made by appropriate software is used.

FIG. 4 shows three examples of the state of the address space of the CPU 1 by a memory map. As shown in the figure, in the storage area M of the EEP-ROM 4, both the user program area M1 and the data area M2 are allocated at an arbitrary ratio.

FIG. 5 is a flowchart showing an example of a processing operation when the CPU 1 controls writing to the EEP-ROM 4.

2, in FIG. 2, the CPU 1 executes a predetermined processing operation while reading the program Ix2 written in the user program area M1 one instruction at a time (step S6).

Here, when it becomes necessary to write the storage required data Dx to the EEP-ROM 4 in the course of the processing operation (step S1), the CPU 1 writes the data in the standard program area Ix1 stored in the mask ROM 3 by a call instruction. Jump to the start address of the control program (step S2). Then, a write control process of the EEP-ROM 4 is executed according to the write control program (step S3). Thus, the writing to the EEP-ROM 4 is performed via the EEP-ROM writing control circuit 7. While this writing is being performed, the EEP-ROM 4 is disconnected from the CPU 1.

After that, when the writing is completed, the CPU 1 determines the completion of the writing based on, for example, a flag or an interrupt request issued from the write control circuit 7 (step S4). Then, the CPU 1 returns from the mask ROM 3 to the program area M1 of the EEP-ROM 4, and resumes reading the user program from the address next to the address at the time of the jump (step S5). Then, the user program of the EEP-ROM 4 is executed until the processing is completed or the next data write request is issued (step S6).

As described above, the user program area M1 and the data area M2 can be stored in one EEP-ROM 4. At the same time, the size ratio between the two areas M1 and M2 can be arbitrarily selected. Therefore, even if the size of the storage area M of the entire EEPROM is not so large, for example, as shown in three examples in FIG. The storage area M is flexibly accommodated by increasing the size of the program area M1 instead of reducing the size of the data area M2, or increasing the size of the data area M2 instead of reducing the size of the program area M1. It can be used efficiently.

Thereby, the hardware configuration scale is maintained while maintaining the advantage that the user can immediately respond to various uses of the user and that the data Dx can be semipermanently stored in the EEP-ROM 4 as necessary. The object of the present invention is to achieve the reduction of the size of the hardware and the efficiency of using the hardware resources.

Here, the return to the user program when the writing of the EEP-ROM is completed may not be based on the flag or the interrupt request issued from the write control circuit 7 as in the embodiment. For example, an appropriate work register in the CPU 1 is used as a kind of counter or timer that is started at the same time as the start of the writing operation to the EEP-ROM and is updated at a constant period during the operation. May be configured to execute the above-mentioned return operation when the content of the item reaches a predetermined value. In other words, a configuration may be employed in which the CPU 1 measures a predetermined required write time which is expected in advance, and when the time measurement is completed, the completion of the writing operation to the EEP-ROM is checked by software. In this case, the setting of the writing time and the control of the return operation thereafter may be performed by a dedicated circuit such as a timer circuit in hardware.

In the example described above, the user program is configured to stop the CPU 1 by external control and to directly write to the user program area M1 of the EEP-ROM 4 from the outside, although there is no particular limitation.

The writing of the user program may be configured so that the CPU 1 receives the program from the outside via the I / O unit 5 according to the program in the mask ROM 3, and sequentially writes the program into the user program area M1 of the EEP-ROM 4. In this example, since there is no means for directly accessing the built-in EEP-ROM 4 from the outside, the security function is strengthened and the suitability as a single-chip microcomputer built in the IC card is increased. it can.

In this case, whether or not writing to the user program 4 has already been performed may be determined by having a flag in the EEP-ROM 4 and in that state. The configuration may be such that the start address after reset of the CPU 1 is changed according to the state of this flag.

(4) As a writable ROM, not only an electrically writable and erasable ROM such as an EEP-ROM but also an ultraviolet-erasable EP-ROM can be used.

In the above example, although not particularly limited, writing is performed by the write control circuit 7 and writing is performed for a fixed time.

(4) In the case of an EP-ROM, writing time is generally longer than that of an EEP-ROM. For this reason, the above-described method with a fixed writing time causes an increase in response time when the IC card is incorporated in an IC card. Here, due to the large process variation of the EP-ROM element, the writing time is set in consideration of the worst case, so that in many cases, the writing time is spent more than necessary.

Therefore, the present inventor has considered a configuration in which the CPU 1 activates the write control circuit 7 and can also stop it. That is, a flag PGM is provided in the write control circuit 7, and when the CPU 1 sets the flag PGM, the writing is started, and when the flag is reset, the writing is ended. The writing time may be measured by software, for example, as described above, or may be used when the timer circuit is built in.

FIG. 9 is a flowchart showing an embodiment of a write control program to be stored in the mask ROM 3 in the above case.

First, the CPU 1 sets write address data for the EP-ROM, and the EP-ROM latches them (step S1). Next, the CPU 1 clears the contents of the specific register N (step S2), adds +1 to the register N (step S3), and sets a flag PGM (step S4). A predetermined unit time, for example, 1 ms is measured (step S5), and thereafter, the flag PGM is reset (step S6), and the writing of the unit time is completed.

Then, it is determined whether or not the writing has been correctly performed (step S7). For this determination, the EP-ROM is read, and the read contents are compared with the write data. Although there is no particular limitation, it is configured such that the latched data is not destroyed during this reading. If the comparison results do not match, the CPU 1 determines the value of the register N (step S11). If the comparison result is 24 or less, the CPU 1 returns to step S3 and executes the unit time writing again. Even if the writing in the unit time is performed 25 times, that is, even if N = 25, if they do not match, it is determined to be defective (step S12), and the process ends.

If the result of the determination is a coincidence, the CPU 1 sets the flag PGM (step S8), further measures the time of 3 × Nms (step S9), clears the flag PGM (step S10), and ends the process. . That is, overwriting is performed for a time three times as long as the time Nms required until the determination results match.

(4) Thereby, high-speed and reliable writing suitable for the element characteristics can be realized, and the writing time and the response time can be shortened.

According to the above-described method, there is an advantage that it is possible to immediately respond to various specification requirements and various applications of the user, and to store the data Dx in the EP-ROM semi-permanently as needed. It is possible to reduce the scale of the hardware configuration, increase the utilization efficiency of hardware resources, and further reduce the response time.

As described above, the invention made by the inventor has been specifically described based on the embodiment. However, the present invention is not limited to the above embodiment, and various modifications can be made without departing from the gist of the invention. Needless to say. For example, a write control program is stored in the mask ROM 3 or the EEP-ROM 4 in advance, and when a write operation of the EEP-ROM 4 is performed, the stored write control program is transferred to the RAM 2 and executed by the CPU 1. A configuration may be used.

Also, the case where the present invention is applied to a single-chip microcomputer for an IC card has been described. However, the present invention is not limited to this. For example, the present invention can be applied to a board-type microcomputer.

At least, the present invention can be applied to the condition that both the program and the data are stored in the EEP-ROM.

FIG. 1 is a block diagram showing a main part of an EEP-ROM built-in microcomputer to which the technology according to the present invention is applied. FIG. 2 is a block diagram showing an overall configuration of the microcomputer shown in FIG. FIG. 3 is a block diagram showing the microcomputer shown in FIG. 2 focusing on data flow. FIG. 3 is an address map illustrating three states of an address space of a CPU in the microcomputer illustrated in FIG. 2; 3 is a flowchart illustrating an operation example of the microcomputer illustrated in FIG. 2. FIG. 1 is a block diagram showing a configuration of an EEP-ROM built-in microcomputer studied prior to the present invention. FIG. 7 is a block diagram showing the microcomputer shown in FIG. 6 focusing on the flow of data. 7 is an address map illustrating a state of an address space of a CPU in the microcomputer illustrated in FIG. 6. 9 is a flowchart illustrating a write control program when an EP-ROM is built-in.

Explanation of reference numerals

1 CPU
2 RAM
3 Mask ROM
4,41,42 EEP-ROM
5 I / O
6 Peripheral circuit 7 Write control circuit 10 Microcomputer

Claims (4)

A central processing unit;
A mask ROM having an area for storing a first program executed by the central processing unit;
An electrically writable and erasable ROM having an area for storing a second program executed by the central processing unit;
RAM,
An IO circuit to which data is input from the outside,
The RAM and the electrically writable and erasable ROM are arranged in different address spaces,
The central processing unit, when writing data input from the IO circuit into the electrically writable and erasable ROM, stores the data input from the IO circuit into the RAM based on the first program. And by writing the data prepared in the RAM to the electrically writable and erasable ROM,
The said 2nd program has the instruction | indication which jumps to the said 1st program, The microcomputer characterized by the above-mentioned. A central processing unit;
A mask ROM having an area for storing a first program executed by the central processing unit;
An electrically writable and erasable ROM having an area for storing a second program executed by the central processing unit;
RAM,
An IO circuit to which data is input from the outside,
The RAM and the electrically writable and erasable ROM are arranged in different address spaces,
The central processing unit, when writing data input from the IO circuit into the electrically writable and erasable ROM, stores the data input from the IO circuit into the RAM based on the first program. And by writing the data prepared in the RAM to the electrically writable and erasable ROM,
The second program is characterized in that the central processing unit has an instruction for shifting to processing for writing data to the electrically writable and erasable ROM by the first program. Micro computer. A central processing unit;
A mask ROM having an area for storing a first program executed by the central processing unit;
An electrically writable and erasable ROM having an area for storing a second program executed by the central processing unit;
RAM,
An IO circuit to which data is input from the outside,
The RAM and the electrically writable and erasable ROM are arranged in different address spaces,
The central processing unit, when writing data input from the IO circuit into the electrically writable and erasable ROM, stores the data input from the IO circuit into the RAM based on the first program. And by writing the data prepared in the RAM to the electrically writable and erasable ROM,
The second program has an instruction for causing the central processing unit to shift to a process for writing data in the electrically writable and erasable ROM by the first program,
The first program has an instruction for causing the central processing unit to return to the execution of the second program after the data writing process to the electrically writable and erasable ROM is completed. A microcomputer. A central processing unit;
An electrically writable and erasable ROM having a storage area for a program executed by the central processing unit;
Storage means having an area for storing a write control program for writing to the electrically writable and erasable ROM;
RAM,
A microcomputer having input / output means,
The RAM and the ROM are arranged in different address spaces,
The central processing unit stores data received from outside the microcomputer via the input / output means in the RAM based on the write control program, and writes data prepared in the RAM into the ROM.
The program stored in the electrically writable and erasable ROM is used by the central processing unit to write a program or data into the electrically writable and erasable ROM by the write control program. Have an order to migrate,
The write control program is stored in the electrically writable and erasable ROM by the central processing unit after the process of writing the program or data to the electrically writable and erasable ROM is completed. A computer having instructions for returning to execution of a programmed program.

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