JP2008171565A - Nonvolatile semiconductor memory device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To achieve a nonvolatile semiconductor memory device in which data requiring security can be stored like the identification number being intrinsic to a chip. <P>SOLUTION: Information indicating the number of times of erasure of the erasion unit region is present in the management information region of the erasure unit region in a part of region or a whole region of a memory region, and when the information is the prescribed value, voltage required for erasure is not applied to the word line or the data line or the source line of part of the region or the whole region, Also, the same control is performed for writing. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a nonvolatile semiconductor memory device that can store data requiring security.

  With the spread of portable information devices such as digital still cameras, the demand for flash memory cards as external storage devices is increasing. A flash memory card is a PC card or a storage device of a size smaller than that, which is equipped with a flash memory as a storage medium.

  A flash memory is an electrically rewritable nonvolatile semiconductor memory suitable for high integration. The main use of the flash memory is used for storing a BIOS of a PC (Personal Computer), a program of a mobile phone and data (such as an address book) in addition to a storage medium in a flash memory card.

  Various cell array structures such as an AND type and a NOR type have been proposed for flash memories according to their use, and each has its own characteristics.

  An AND flash memory is a flash memory suitable for high integration and low voltage, and is often used as a storage medium for file storage. As a known example of the AND type flash memory, there is Patent Document 1 (Japanese Patent Laid-Open No. 6-77437). Erasing is performed by applying a high voltage to the control gate, grounding the source, drain, and substrate, and injecting electrons from the channel to the floating gate with a Fowler-Nordheim current. As a result, the threshold value of the flash memory cell increases. Writing is performed by applying a negative voltage to the control gate and applying a low voltage to the drain, opening the source, and grounding the substrate. At this time, electrons are extracted from the floating gate to the drain by the Fowler-Nordheim current, and the threshold value of the memory cell is lowered. In the AND type flash memory, a state in which the threshold value of the memory cell is high is an erased state, and the value stored in the memory cell at this time is “1”. Further, a state in which the threshold is low is a write state, and the value stored in the memory cell at this time is '0'.

  In recent years, with the increase in capacity of flash memory chips, there is an increasing expectation for uses for storing music data and electronic book data. A problem in storing these data in the flash memory is copyright protection for the content stored in the flash memory card.

As one method for realizing copyright protection of content, there is a method in which a unique identification number is provided in the flash memory chip and this identification number is used. In other words, to prevent unauthorized copying in such a way that content cannot be copied to a flash memory chip with another identification number, or it cannot be reproduced correctly even if it can be copied to a flash memory chip with another identification number. it can.
JP-A-6-77437

  The identification number provided in the same chip as the flash memory must be rewritable. If the identification number is stored in the mask ROM area, the identification number cannot be written on the user side after the chip is shipped. On the other hand, when the identification number is stored in the conventional flash memory area, it is freely tampered with by erasing or overwriting.

  The issues when storing data that requires security, such as identification numbers, in the flash memory area are: (1) can be erased at least once before writing the identification number; (2) after writing once It is to realize a flash memory that cannot be written again, or (3) cannot read or write other data when overwriting of an identification number is detected.

  An object of the present invention is to realize a nonvolatile semiconductor memory device having a storage area that cannot be erased again after being erased a predetermined number of times.

  Another object of the present invention is to realize a nonvolatile semiconductor memory device having a storage area in which writing cannot be performed again after writing once.

  Still another object of the present invention is to realize a nonvolatile semiconductor memory device that cannot read / write other data when overwriting of data is detected.

To achieve the above objective,
A storage area composed of a plurality of erasing unit areas, and having a normal data area for each erasing unit area and a management information area for storing management information of the entire erasing unit area;
A selection device that selects a word line, a data line, or a source line according to an address value input from the outside and applies a predetermined voltage;
An operation control device for controlling operations such as erasing, writing, and reading;
In a nonvolatile semiconductor memory device having a temporary storage device that stores a state of the nonvolatile semiconductor memory device,
In the management information area of the erase unit area in a part or all of the storage area, there is information indicating that the erase unit area has been erased once. When this information is a predetermined value, Under the control of the operation control device, means for suppressing application of a voltage necessary for erasing is provided to a word line, data line or source line in a part or all of the region.

In order to achieve another object of the present invention,
In the management information area of the erase unit area in a part or all of the storage area, there is information indicating that data has been written once in the erase unit area, and this information is selected when it is a predetermined value. Means for suppressing application of a voltage necessary for writing to a word line, a data line, or a source line in a part or all of the region is provided by control of the operation control device for the device.

In order to achieve yet another object of the present invention,
It has a device that generates data having a one-to-one mapping relationship with each bit of normal data, and the normal data and mapping relationship are stored in the same writing unit area for a part or all of the storage area. It has an area for writing data, and when writing and reading to other data areas, it is verified in advance whether normal data and mapping-related data are in a mapping relationship with each other. Means are provided for making writing to and reading from impossible.

  According to the present invention, it is possible to provide an area that cannot be erased a predetermined number of times or more and can be written only once in the storage area of the nonvolatile semiconductor memory device.

  Further, by writing normal data and its inverted data in the same write unit area in the re-erasure prohibition area, it becomes possible to easily detect alteration of normal data. By utilizing this, when alteration of normal data is detected, it becomes possible to make an application in which other data in the chip cannot be accessed.

  As described above, there is an effect that data requiring security such as an identification number unique to the chip can be stored in the flash memory chip.

(First embodiment)
First, a first embodiment of the present invention will be described. FIG. 2 shows a block configuration of the AND type flash memory chip 201. Hereinafter, each block constituting the AND flash memory chip 201 will be described.

  The cell array group 202 of the AND type flash memory is composed of eight cell arrays. Data erasing / writing / reading is performed in parallel in an 8-sided cell array. The cell array has flash memory cells arranged in a plane. FIG. 3 shows the structure of the cell array of the AND type flash memory. Select transistors (301, 302, 303, and 304, 305, 306) are provided on the drain side and the source side, respectively, and M flash memory cells are connected in parallel between the two select transistors. The storage area sandwiched between the set of select transistors, that is, the storage area surrounded by a dotted line in FIG. 3, is hereinafter referred to as a memory block. A ground voltage Vss is applied to the common source line.

  The AND flash memory performs erasing, writing, and reading with respect to all the flash memory cells connected to the selected word line. For example, consider the case where the memory cell group M2 connected to the word line W2 is selected in FIG.

  The erase operation is performed by applying the power supply voltage Vcc to the gates SD and SS of the selection transistors on the drain side and the source side, the high voltage Vpp to the word line W2, and the ground voltage Vss to the data lines D1 to D528. The write operation is performed by applying the power supply voltage Vcc to the gate SD of the selection transistor on the drain side, the ground voltage Vss to the gate SS of the selection transistor on the source side, the negative voltage Vnn to the word line W2, and the power supply voltage Vcc to the data line. The read operation is performed by applying a power supply voltage Vcc to the gates SD and SS of the selected transistor on the drain side and the source side, a power supply voltage Vcc to the word line W2, and a predetermined positive voltage to the data lines D1 to D528.

  528 flash memory cells are connected to one word line (Wn) in the cell array. In this embodiment, 1-bit data is stored for each flash memory cell. Since the cell array group 202 is composed of eight cell arrays, the unit of erasing, writing, and reading is 528 bytes.

  FIG. 32 shows the data structure of the cell array group 202. An address is assigned to each word line. The 528-byte data corresponding to one address is composed of a 512-byte sector data area and a 16-byte management information area for storing information for managing the sector data. The reason why the sector data is 512 bytes is to make it the same as the sector size of the magnetic disk. Row address 0 is an erase prohibited area. Row addresses 1 to 16383 are erasable areas.

  The row decoder 203 in FIG. 2 selects a word line in the cell array group 202 and applies a predetermined voltage. As shown in FIG. 33, the row decoder 203 includes a word line selection circuit 100 in an erasure prohibited area, a word line selection circuit 101 in an erasable area, and memory block selection circuits 102 and 103.

  The word line selection circuit 100 in the erasure prohibited area and the word line selection circuit 101 in the erasable area select the word line by decoding the row address, and control the voltage applied to the word line. Although not shown in FIG. 33, the row address is input to the row decoder 203 via the row address buffer 204. When the row address is 0, the word line selection circuit 100 in the erase prohibition area selects a word line. When the row address is from 1 to 16383, the word line selection circuit 101 in the erasable area selects the word line corresponding to the row address. Only the word line voltage Vw and the ground voltage Vss are supplied to the word line selection circuit 101 in the erasable area, and only the ground voltage Vss is supplied to the word line selection circuit 100 in the erasure prohibited area from the internal power generation circuit 213 shown in FIG. Is done.

  FIG. 34 shows an internal configuration of the word line selection circuit 100 in the erasure prohibition area, and FIG. 35 shows a circuit corresponding to one word line in the word line selection circuit 101 in the erasable area. When 0 is input as a row address from the outside of the chip, a word line in the erase prohibition area is selected. At this time, the voltage applied to the word line changes according to the control signal ERS from the control circuit 211. That is, when the control signal ERS is at the “H” level, the ground voltage Vss is applied to the word line, and when the control signal ERS is at the “L” level, the word line voltage Vw is applied to the word line. Further, since the word line in the erasable area is not selected, the ground voltage Vss is applied.

  On the other hand, when 1 to 16383 is input as the row address, the word line corresponding to the row address in the erasable area is selected. At this time, the word line selection circuit 101 in the erasable region applies the word line voltage Vw to the selected word line. In addition, the ground voltage Vss is applied to unselected word lines in both the word line selection circuit 100 in the erasure prohibited area and the word line selection circuit 101 in the erasable area.

  Memory block selection circuits 102 and 103 select a memory block by decoding the row address. Although not shown in FIG. 33, the row address is input to the memory block selection circuits 102 and 103. Further, the power supply voltage Vcc and the ground voltage Vss are supplied. The memory block selection circuits 102 and 103 control the voltage applied to the gates of the selection transistors on the drain side and the source side in accordance with a control signal from the control circuit 211. In the erase operation and the read operation, the memory block selection circuits 102 and 103 apply the power supply voltage Vcc to the gates of the drain side and source side selection transistors. In the write operation, the memory block selection circuits 102 and 103 apply the power supply voltage Vcc to the gate of the drain-side selection transistor and apply the ground voltage Vss to the gate of the selection transistor on the source side.

  The latch circuit 205 has a role of holding write data at the time of writing and amplifying and holding a read voltage as a sense amplifier at the time of reading. The column address counter 206 becomes a buffer for a column address inputted from the outside of the chip, and increments the column address by a control signal from the control circuit 211 to change the accessed column address. The column decoder 207 decodes the column address and outputs a signal for selecting a data line to be accessed. The column gate 208 selects a data line to be accessed based on the output of the column decoder 207.

  The input data control circuit 209 controls the voltage applied to the data lines in the cell array group 202 in accordance with a control signal from the control circuit 211 in the erase operation or the read operation. In the case of a write operation, the input data from the multiplexer 210 is transmitted to the column gate 208 as it is. The multiplexer 210 performs bus switching according to a control signal from the control circuit 211. The control circuit 211 is a circuit that controls the operation inside the chip. The control circuit 211 inputs various control signals from outside the chip. The control circuit 211 outputs a control signal to each block in the chip at a predetermined timing for each operation.

  The status register 212 indicates the operation state or operation result of the flash memory chip 201. The bit configuration of the status register 212 is shown in FIG. The status register is composed of 8 bits. When the 0th bit (R_B) is “0”, the chip is busy, and when it is “1”, the chip is ready. Bit 2 (EER) indicates an erase error when it is "1". Bit 3 (PER) indicates a write error when “1”. Bit 4 (EIH) indicates that an error occurs because the erase command is issued to the erase-inhibited area when “1”. The other bits are reserved bits.

  The internal power generation circuit 213 receives the power supply voltage Vcc and the ground voltage Vss from the outside of the chip. The power supply voltage Vcc is, for example, a single power supply of 3.3V. The ground voltage Vss is 0V. The internal power supply generation circuit 213 performs step-up from the power supply voltage Vcc to the high voltage Vpp or step-down to the negative voltage Vnn in accordance with a control signal from the control circuit 211, and outputs it as the word line voltage Vw. Here, the high voltage Vpp is 12 V, for example, and the negative voltage Vnn is -7 V, for example. Internal power supply generation circuit 213 outputs power supply voltage Vcc and ground voltage Vss to each block, and outputs word line voltage Vw to row decoder 203.

  Hereinafter, input / output signals of the AND type flash memory chip 201 will be described with reference to FIG.

  I / O is a data signal bus composed of eight lines. Command input and data input / output are performed byte by byte via the data input / output signal terminal I / O. ADDR is an address signal bus, and is composed of a row address and a column address. / CE is a chip selection signal. '/' In front of the signal name indicates that the signal is negative logic. / OE is a signal to be asserted when reading memory data or a status register.

  / WE is a signal for latching an externally input command or address. SC is a signal for latching data byte by byte in writing and reading. R / B outputs “0” when the flash memory chip 201 is busy during erasing or writing. On the other hand, high impedance is output in the ready state.

  Hereinafter, the erase operation, write operation, and read operation of the AND flash memory chip 201 will be described.

  First, the erase operation procedure will be described.

  (1) After / CE is asserted from outside the chip, an erase command is input. The erase command is input to the control circuit 211 via the multiplexer 210.

  (2) An address (row address + column address) is input from outside the chip. Of the inputted addresses, the row address is inputted to the row address buffer 204 and the control circuit 211, and the column address is inputted to the column address counter 206.

  (3) The control circuit 211 sets the control signal ERS to “1”.

  (4) An erase start command is input from outside the chip.

  (5) Regardless of whether or not the input row address is 0, the ground voltage Vss is applied to the word line of the row address 0. That is, since no potential difference is generated between the word line and the substrate, erasing cannot be performed.

  For write operations, the negative voltage Vnn is applied to the selected word line and the unselected word line is grounded regardless of whether the word line specified by the row address is in the erasure prohibited area or the erasable area. Apply voltage Vss. Therefore, data can be written without distinction between the erasure prohibited area and the erasable area.

  In the read operation, the power supply voltage Vcc is applied to the selected word line and the unselected word line is grounded regardless of whether the word line specified by the row address is in the erasure prohibited area or the erasable area. Apply voltage Vss. Therefore, data can be read without distinction between the erasure prohibited area and the erasable area.

  According to this embodiment, it is possible to provide an erase prohibition area that cannot be erased even once. However, the erasing operation is generally performed in the sorting process after manufacturing the flash memory chip.

  Therefore, as a second embodiment, an AND flash memory that can be erased only once will be described.

(Second embodiment)
The following description will focus on the points different from the first embodiment.

  FIG. 4 shows the data structure of the cell array group 202.

  Row address 0 is a re-erasure prohibited area. The management information area of the re-erasure prohibited area stores 1 byte of erased bytes. This byte cannot be read or written from outside the chip 201. Row addresses 1 to 16383 are erasable areas. The management information area of the erasable area also has an area for storing erased bytes, but is not used.

  FIG. 1 shows details of the cell array and its periphery in the second embodiment.

  The word line selection circuit 100 in the re-erasure prohibited area and the word line selection circuit 101 in the erasable area shown in FIG. 1 select a word line by decoding the row address, and control the voltage applied to the word line. Although not shown in FIG. 1, the row address is input to the row decoder 203 via the row address buffer 204. When the row address is 0, the word line selection circuit 100 in the re-erasure prohibited area selects a word line. When the row address is from 1 to 16383, the word line selection circuit 101 in the erasable area selects the word line corresponding to the row address. The word line voltage Vw and the ground voltage Vss are supplied from the internal power supply generation circuit 213 to the word line selection circuit 100 in the re-erasure prohibited area and the word line selection circuit 101 in the erasable area.

  FIG. 5 shows an internal configuration of the word line selection circuit 100 in the re-erasure prohibition area, and FIG. 6 shows a circuit corresponding to one word line in the word line selection circuit 101 in the erasable area. When 0 is input as a row address from the outside of the chip, a word line in the re-erasure prohibited area is selected. At this time, the voltage applied to the word line corresponding to the row address 0 by the word line selection circuit 100 in the re-erasure prohibited area differs depending on the control signal EPH from the outside. As shown in FIG. 1, when all the values stored in the latches corresponding to the data line D528 of each cell array are ‘1’, the control signal EPH is ‘1’. When EPH is ‘0’, the word line voltage Vw is applied to the word line, and when EPH is ‘1’, the ground voltage Vss is applied to the word line. Further, since the word line in the erasable area is not selected, the ground voltage Vss is applied.

  On the other hand, when 1 to 16383 is input as the row address, the word line corresponding to the row address in the erasable area is selected. At this time, the word line selection circuit 101 in the erasable region applies the word line voltage Vw to the selected word line. Further, the ground voltage Vss is applied to the unselected word lines in both the word line selection circuit 100 in the re-erasure prohibited area and the word line selection circuit 101 in the erasable area.

  Memory block selection circuits 102 and 103 select a memory block by decoding the row address. Although not shown in FIG. 1, the row address is input to the memory block selection circuits 102 and 103. Further, the power supply voltage Vcc and the ground voltage Vss are supplied.

  Hereinafter, the erase operation, write operation, and read operation of the AND flash memory chip 201 will be described.

  First, the erase operation will be described with reference to FIGS. The detailed procedure of the erase operation will be described below using FIG.

  (Step 801) After / CE is asserted from outside the chip, an erase command is input. The erase command is input to the control circuit 211 via the multiplexer 210.

  (Step 802) An address (row address + column address) is input from outside the chip. Of the inputted addresses, the row address is inputted to the row address buffer 204 and the control circuit 211, and the column address is inputted to the column address counter 206.

  (Step 803) The control circuit 211 determines whether or not the input row address is zero.

  (Step 804) When the row address is not 0, an erase start command is input from the outside of the chip.

  (Step 805) On the other hand, when the row address is 0, the control circuit 211 first sets the control signal CNF to “1”. Next, a control signal for reading is issued to the internal power generation circuit 213 and the input data control circuit 209, and the erased byte in the management information area is read to the latch circuit 205. During this time, the R / B signal outputs “0” to indicate that the inside of the chip is busy. After the reading is completed, the control circuit 211 sets the control signal CNF to “0”.

  (Step 806) After the processing of step 805 is completed, an erase start command is input from the outside of the chip.

  (Step 807) When at least one bit among all the bits in the erased byte is “0” (that is, when erasing has never been performed), or after the processing of Step 804 is finished, the control circuit 211 A control signal for erasing is output to internal power supply generation circuit 213 and input data control circuit 209. At this time, the high voltage Vpp is applied to the selected word line, and the ground voltage Vss is applied to the data lines D1 to D528. Thereby, erasing of the flash memory cell connected to the selected word line is started. While the flash memory cell is being erased, the output signal R / B is ‘0’, indicating that the inside of the chip is busy. Further, when / OE is asserted during erasing, the contents of the status register 212 can be read. At this time, bit 0 (R_B) of FIG. 7 is “0”.

  (Step 808) When erasing is finished, the output signal R / B returns to high impedance, that is, ready state. Thereafter, when / OE is asserted and the status register 212 is read, bit 0 (R_B) in FIG. 7 is ‘1’ and bit 4 (EIH) is ‘0’.

  (Step 809) When all the bits of the erased byte are “1” (that is, when erasing is performed once), a control signal for erasing is output to the internal power generation circuit 213 and the input data control circuit 209 To do. At this time, the ground voltage Vss is applied to the selected word line, and no potential difference is generated between the selected word line and erasing cannot be performed. Here, the output signal R / B is in a high impedance state. When the status register 212 is read here, bit 0 (R_B) in FIG. 7 is ‘1’ and bit 4 (EIH) is ‘1’.

  FIG. 9 shows a timing chart when an erase command is issued to the erasable area. FIG. 10 shows a timing chart when the erase command is first issued to the re-erasure prohibited area. FIG. 11 shows a timing chart when the erase command is issued to the re-erasure prohibited area for the second time and thereafter. As for the write operation and the read operation, after inputting the address, the control circuit 211 does not determine whether the row address is 0 or read the erased byte to the latch circuit 205.

  For the write operation, a negative voltage Vnn is applied to the selected word line and a non-selected word line is applied to the selected word line regardless of whether the word line specified by the row address is in the re-erasure prohibited area or the erasable area. Apply ground voltage Vss. Therefore, data can be written without distinction between the re-erasure prohibited area and the erasable area.

  In the read operation, the power supply voltage Vcc is applied to the selected word line regardless of whether the word line specified by the row address is in the re-erasure prohibited area or the erasable area, and the non-selected word line is applied. Apply ground voltage Vss. Therefore, data can be read without distinction between the re-erasure prohibited area and the erasable area.

  According to the present embodiment, an erasable area can be provided only once in a part of the memory area of the AND type flash memory.

  In this embodiment, the number of erasures allowed for the re-erasure prohibited area is one. This can be expanded to prohibit erasure after erasing a predetermined number of times. At this time, the number of erasures is stored in the management information area instead of the erased bytes. The number of times of erasure is written by the control circuit 211 by controlling the input data control circuit 209.

  In the present embodiment, the AND type flash memory has been described. However, the effect of the present embodiment is not limited to the AND type. In other flash memory cell structures such as DINOR type, NOR type, and NAND type, the re-erasure prohibition region can be provided in the same manner.

  The same effect as that of the present embodiment can also be obtained by a flash memory card 310 including a flash memory chip group 311 and a card controller chip 312 as shown in FIG. That is, the card controller chip 312 may incorporate a means for reading the erase byte and controlling the erase to the re-erasure prohibited area. Further, a re-erasure error can be displayed using the card status register 313 in the card controller chip 312. As a result, the contents of the card status register 313 can be read from a host device such as a notebook PC. At this time, the flash memory chip group 311 may be formed of a conventional flash memory chip.

(Third embodiment)
Next, a third embodiment will be described with reference to FIGS. This embodiment develops the re-erasure prohibition area described in the first embodiment and further has a function of preventing overwriting. That is, in addition to being erasable only once, it is an object to realize an area that can be written only once.

  FIG. 13 shows the data configuration of the cell array group 202 in this embodiment. Row address 0 is a re-erase / re-write prohibited area. In the management information area at row address 0, 1 byte of written bytes is stored in addition to the erased bytes. This written byte cannot be read or written from outside the chip 201.

  In the write operation, the control circuit 211 reads the written byte, determines whether all the bit data is “0”, and sets the control signal OTP to the row decoder 203. In the first write operation to the re-erase / rewrite prohibited area, the control circuit 211 controls the input data control circuit 209 to store “0” in all bits of the written byte.

  FIG. 15 shows the bit configuration of the status register 212. A rewrite error bit (PIH) is newly added to bit 5 with respect to the bit configuration of the status register in the first embodiment. Bit 5 (PIH) is set to ‘1’ when a write command is issued for the second or later re-erasure / re-write prohibited area.

  The write operation will be described with reference to FIGS. Hereinafter, the procedure of the write operation will be described with reference to FIG.

  (Step 1601) After / CE is asserted from outside the chip, a write command is input. The write command is input to the control circuit 211 via the multiplexer 210.

  (Step 1602) An address (row address + column address) is input from outside the chip. Of the inputted addresses, the row address is inputted to the row address buffer 204 and the control circuit 211, and the column address is inputted to the column address counter 206.

  (Step 1603) The control circuit 211 determines whether or not the input row address is zero.

  (Step 1604) When it is determined that the row address is not 0, write data is input byte by byte from the outside of the chip. At this time, a maximum of 526 bytes can be input. The input data is stored in the latch circuit 205.

  (Step 1605) After the input is completed, a write start command is input from the outside of the chip.

  (Step 1606) On the other hand, if it is determined in Step 1603 that the row address is 0, the control circuit 211 first sets the control signal CNF to “1”. Next, a control signal for reading is output to the internal power generation circuit 213 and the input data control circuit 209, and the erased bytes and written bytes in the management information area are read into the latch circuit 205. During this time, the output signal R / B outputs “0” to indicate that the inside of the chip is busy. After the reading is completed, the control circuit 211 sets the control signal CNF to “0”.

  (Step 1607) Write data is input byte by byte from outside the chip. At this time, a maximum of 526 bytes can be input. The input data is latched by the latch circuit 205. After the input is completed, the input data control circuit 209 latches “0” in the eight latches corresponding to the data line D527 in the cell array group 202.

  (Step 1608) A write start command is input from outside the chip.

(Step 1609) When all the bits of the erased byte do not satisfy “1” and all the bits of the written byte satisfy “0”, or after the processing of Step 1605 ends, the control circuit 211 executes the internal power generation circuit 213 and A control signal for writing to the input data control circuit 209 is output. At this time, a negative voltage Vnn is applied to the selected word line. The voltage applied to the data line corresponds to the value stored in the latch circuit 205. Thereby, writing of the flash memory cell connected to the selected word line is started. In the first writing in the re-erase / re-write prohibited area, “0” is written in all bits of the written byte in the management information area. During this time, the output signal R / B is “0”, indicating that the inside of the chip is busy. Further, when / OE is asserted during writing, the contents of the status register 212 can be read. At this time, bit 0 (R_B) of FIG. 15 is “0”.

  (Step 1610) When the writing is completed, the output signal R / B returns to the high impedance, that is, ready state. Thereafter, when / OE is asserted and the status register 212 is read, bit 0 (R_B) in FIG. 15 is ‘1’ and bit 5 (PIH) is ‘0’.

  (Step 1611) When all the bits of the erased byte are “1” and all the bits of the written byte are “0” (that is, when erasing and writing have already been performed), the control circuit 211 uses the internal power generation circuit. A control signal for writing to 213 and the input data control circuit 209 is output. At this time, the ground voltage Vss is applied to the selected word line, and no potential difference is generated between the selected word line and the data line applied to the ground voltage Vss or the power supply voltage Vcc, or writing is not generated because the potential difference is small. Here, the output signal R / B is in a high impedance state. When the status register 212 is read, bit 0 (R_B) in FIG. 15 is “1” and bit 5 (PIH) is “1”.

  FIG. 17 shows a timing chart when a write command is issued to the erasable / writable area. FIG. 18 shows a timing chart when a write command is first issued to the re-erase / re-write prohibited area. FIG. 19 shows a timing chart when a write command is issued to the re-erase / rewrite prohibited area for the second time and thereafter. The erase operation and read operation are the same as in the first embodiment.

  According to this embodiment, it is possible to provide an area in which data can be written only once in a part of the memory area of the AND type flash memory. By not permitting not only erasing but also writing to the data in the re-erase / re-write prohibited area, it is possible to prevent data destruction due to overwriting.

  Also in this embodiment, the same effect can be obtained with a flash memory card 310 including a flash memory chip group 311 and a card controller chip 312 as shown in FIG.

(Fourth embodiment)
Next, a fourth embodiment will be described with reference to FIGS. In this embodiment, the erasure prohibition area of the second embodiment is developed in a different form from that of the third embodiment.

  FIG. 20 shows a block configuration of an AND type flash memory chip 901. Hereinafter, a block newly added in the present embodiment and a block having a different function from the block described in the first embodiment will be described.

  The cell array group 902 is composed of an 8-sided cell array as in the first embodiment. FIG. 21 shows a data structure of the cell array group 902.

  The row address 0 is a erasure prohibition area of 528 bits × 8 = 528 bytes as in the second embodiment. The sector data area of the re-erasure prohibition area is composed of an area for storing identification numbers within 256 bytes and an area for storing inverted data of identification numbers within 256 bytes. The inverted data of the identification number is data obtained by inverting “0” to “1” and “1” to “0” when the identification number is expressed in binary numbers of “0” and “1”. Row address 1 to row address 16383 are erasable areas, and user data is stored in the sector data area.

  Similar to the second embodiment, the row decoder 903 includes a word line selection circuit for a re-erasure prohibition area, a word line selection circuit for an erasable area, and a memory block selection circuit. FIG. 22 shows a word line selection circuit in the re-erasure prohibited area. Even if the row address input from the outside of the chip is not 0, the word line is selected by the control signal RID from the controller circuit 211 so that the power supply voltage Vcc necessary for reading can be applied. The word line selection circuit in the erasable area is the same as the word line selection circuit 101 in the erasable area in FIG. Therefore, the circuit for each word line is the same as in FIG. The memory block selection circuit is also the same as the memory block selection circuits 102 and 103 in FIG.

  The data line voltage control circuit 906 corresponds to the input data control circuit 209 in FIG. The data line voltage control circuit 906 controls the voltage applied to the data line in accordance with the control signal OPR from the control circuit 211 in each of the erase, write, and read operations.

  FIG. 23 is a detailed diagram of the inversion / collation circuit 907, the multiplexers 904 and 905, the gate circuit 908, and the latch circuit 205.

  The inversion / collation circuit 907 has two roles. One role is to generate inverted data of the identification number in the inversion / collation circuit 907 in writing the identification number, and to output the identification number and its inverted data to the data line. Another role is to check the alteration of the identification number before accessing the user data. Here, the check is to read two data stored in the identification number area and the inverted data area and verify whether they are in an inverted relationship. When the two data are in an inverted relationship, the MOS switch in the gate circuit 908 is turned on, so that user data can be read / written. On the other hand, when the two data are not reversed, the MOS switch in the gate circuit 908 is turned off, so that user data cannot be read / written.

  The multiplexers 904 and 905 perform input / output switching control for the re-erasure prohibited area or input / output for the erasable area. Switching control is performed by a control signal UDID from the control circuit 211.

  The bit configuration of the status register 212 is shown in FIG. Compared to the case of the first embodiment, bit 5 (TMP) is newly added. When bit 5 (TMP) is “1”, it indicates that the user data cannot be accessed because the identification number is overwritten.

  The access procedure for the identification number will be described below. Here, the procedure will be described using the writing of the identification number as an example with reference to FIG.

  (Step 2501) After / CE is asserted from outside the chip, a write command is input. The write command is input to the control circuit 211 via the multiplexer 210.

  (Step 2502) An address (however, row address = 0) is input from outside the chip. Of the inputted addresses, the row address is inputted to the row address buffer 204 and the control circuit 211, and the column address is inputted to the column address counter 206.

  (Step 2503) The control circuit 211 sets the control signal UDID to the multiplexers 904 and 905 to “0”.

  (Step 2504) After determining that the row address is 0, the control circuit 211 sets the control signal RID to the row decoder 903 to “0”.

  (Step 2505) An identification number and management information are input byte by byte from the outside of the chip. At this time, the maximum number of bytes that can be input is (256 + 15) = 271 bytes. The input identification number and inverted data of the identification number are stored in a latch circuit in the inversion / collation circuit 907. Management information is stored in the latch circuit 205.

  (Step 2506) A write start command is input from outside the chip.

  (Step 2507) The controller circuit 211 outputs a control signal for performing writing to the internal power generation circuit 213 and the data line voltage control circuit 906. At this time, the word line selection circuit in the re-erasure prohibited area in the row decoder 903 applies a negative voltage Vnn to the selected word line. The data line voltage control circuit 906 does not apply a voltage to the data line, and a voltage corresponding to a value stored in the inversion / collation circuit 907 and a value stored in the latch circuit 205 is applied to the data line. As a result, writing to the row address 0 is started. During this time, the output signal R / B is “0”, indicating that the inside of the chip is busy. Further, when / OE is asserted during writing, the contents of the status register 212 can be read. At this time, bit 0 (R_B) of FIG. 24 is “0”.

  (Step 2508) When the writing is completed, the output signal R / B returns to the high impedance, that is, ready state. Thereafter, when / OE is asserted and the status register 212 is read, bit 0 (R_B) in FIG. 24 is “1”.

  Through the above procedure, the identification number and its inverted data are written in each area. FIG. 28 shows an identification number writing timing chart.

  Next, the user data access procedure will be described. Here, an example of writing user data will be described with reference to FIG.

  (Step 2601) After / CE is asserted from outside the chip, a write command is input. The write command is input to the control circuit 211 via the multiplexer 210.

  (Step 2602) An address (however, a row address ≠ 0) is input from outside the chip. Of the inputted addresses, the row address is inputted to the row address buffer 204 and the control circuit 211, and the column address is inputted to the column address counter 206.

  (Step 2603) The control circuit 211 sets the control signal UDID to the multiplexers 904 and 905 to “0”.

  (Step 2604) After determining that the row address is not 0, the control circuit 211 sets the control signal RID to the row decoder 903 to ‘1’. At this time, the word line selection circuit in the re-erasure prohibition region applies the power supply voltage Vcc to the word line at the row address 0. Also, the data line voltage control circuit 906 applies a predetermined positive voltage to the data line in accordance with a control signal from the control circuit 211, and reads the data in the identification number area and the inverted data area to the latch in the inversion / collation circuit 907. . During this time, the output signal R / B outputs ‘0’, indicating that the chip is busy.

  In the inversion / collation circuit 907, it is determined whether or not the identification number and the inverted data read by the latch are in an inversion relationship.

  Generally, in a flash memory, data can be written only in one direction by a write command. For example, in the AND flash memory, the value stored in the memory cell in the written state is ‘0’, and in the erased state, the value is ‘1’. At this time, the change of the storage data by the write command occurs only in one direction from “1” to “0”. That is, when the information stored in the memory cell is “0”, it cannot be set to “1” by the write command. If this property is used to overwrite the already stored normal data and its inverted data, the two data after overwriting are not in an inverted relationship as shown in FIG. Therefore, it is possible to know whether or not the identification number has been overwritten by checking whether or not the two data are in an inverted relationship. As a result of the determination, when the two data are in an inverted relationship, the MOS transistor group of the gate circuit 908 is turned on. If the inversion relationship is not established, the MOS transistor group is turned off.

  (Step 2605) The controller circuit 211 sets the control signal RID to the row decoder 903 to ‘0’ and the control signal UDID to the multiplexers 904 and 905 to ‘1’. Also, the output signal R / B is returned to high impedance, indicating that the chip is ready.

  (Step 2606) User data and management information are input byte by byte from outside the chip. At this time, the maximum number of bytes that can be input is 527 bytes. The input user data is stored in the latch circuit 205.

  (Step 2607) A write start command is input from the outside of the chip. The controller circuit 211 outputs a control signal for writing to the internal power generation circuit 213 and the data line voltage control circuit 906. At this time, the word line selection circuit in the erasable region in the row decoder 903 applies a negative voltage Vnn to the selected word line. The data line voltage control circuit 906 does not apply a voltage to the data line.

  (Step 2608) If the identification number is not overwritten, that is, if the MOS transistor group in the gate circuit 908 is ON, a voltage corresponding to the value stored in the latch in the latch circuit 205 is applied to the data line. User data can be written. At this time, the output signal R / B is “0”. Further, when / OE is asserted, the contents of the status register 212 can be read. At this time, bit 0 (R_B) in FIG. 24 is ‘0’, and bit 5 (TMP) is ‘0’.

  (Step 2609) When the writing is completed, the output signal R / B returns to the high impedance, that is, ready state. Thereafter, when / OE is asserted and the status register 212 is read, bit 0 (R_B) in FIG. 24 is ‘1’ and bit 5 (TMP) is ‘0’.

  (Step 2610) On the other hand, if the identification number is overwritten, that is, if the MOS transistor group in the gate circuit 908 is OFF, data cannot be written in the user data area. At this time, the output signal R / B is high impedance. Further, when / OE is asserted, the contents of the status register 212 can be read. At this time, bit 0 (R_B) in FIG. 24 is ‘1’, and bit 5 (TMP) is ‘1’.

  FIG. 29 shows a write timing chart of user data when the identification number has not been tampered with. FIG. 30 shows a timing chart for writing user data when the identification number is falsified.

  In this embodiment, the identification number cannot be overwritten, but it can be detected that the identification number has been tampered with. Furthermore, when the identification number has been tampered with, it becomes possible to apply such that the user data cannot be accessed, and the user data can have a security function.

  The same effect as that of the present embodiment can also be obtained with a flash memory card 310 including a flash memory chip group 311 and a card controller chip 312 as shown in FIG. That is, the card controller chip 312 may include a means for generating inverted data and a means for checking whether the normal data and the inverted data are in an inverted relationship. Further, the card status register 313 in the card controller chip 312 can be used to display a re-erase error or an overwrite error. As a result, the contents of the card status register 313 can be read from a host device such as a notebook PC. At this time, the flash memory chip group 311 may be formed of a conventional flash memory chip.

It is a figure which shows the detail of a cell array and its periphery in the 2nd Example of this invention. It is a figure which shows the block structure of the AND type flash memory in the 1st to 3rd Example of this invention. It is a figure which shows the structure of the cell array of AND type flash memory. It is a figure which shows the structure of the cell array group in the 2nd Example of this invention. FIG. 10 is a diagram showing a word line selection circuit in a re-erasure prohibited area in the second embodiment of the present invention. FIG. 10 is a diagram showing a selection circuit corresponding to one word line in a word line selection circuit in an erasable region in the second embodiment of the present invention. It is a figure which shows the bit structure of a status register in the 1st to 3rd Example of this invention. It is a figure which shows the procedure of erasure | elimination operation | movement in the 2nd Example of this invention. It is a figure which shows the timing chart of the erasure | elimination to the erasable area | region in the 2nd Example of this invention. It is a figure which shows the first erase timing chart to the re-erasure prohibition area | region in the 2nd Example of this invention. It is a figure which shows the erasing timing chart of the 2nd time or more to the re-erasure prohibition area | region in the 2nd Example of this invention. It is a figure which shows the detail of a cell array and its periphery in the 3rd Example of this invention. It is a figure which shows the structure of the cell array group in the 3rd Example of this invention. It is a figure which shows the word line selection circuit of the re-erasure prohibition area | region in the 3rd Example of this invention. It is a figure which shows the bit structure of a status register in the 3rd Example of this invention. It is a figure which shows the procedure of the write-in operation | movement in the 3rd Example of this invention. It is a figure which shows the timing chart of the writing to the erasable and writable area | region in the 3rd Example of this invention. It is a figure which shows the first write-in timing chart to the non-re-erasable / re-writeable area in the 3rd Example of this invention. It is a figure which shows the write-timing chart after the 2nd time to the non-re-erasable / re-writable area in the 3rd Example of this invention. It is a figure which shows the block configuration of AND type flash memory in the 4th Example of this invention. It is a figure which shows the structure of the cell array group in the 4th Example of this invention. It is a figure which shows the word line selection circuit of the re-erasure prohibition area | region in the 4th Example of this invention. It is a figure which shows the detail of the inversion / collation circuit, a multiplexer, etc. in the 4th Example of this invention. It is a figure which shows the bit structure of a status register in the 4th Example of this invention. It is a figure which shows the write-in procedure of the identification number in the 4th Example of this invention. It is a figure which shows the write-in procedure of user data in the 4th Example of this invention. It is a figure which shows the overwriting with respect to the identification number and its inversion data in the 4th Example of this invention. It is a figure which shows the write-in timing chart of the identification number in the 4th Example of this invention. It is a figure which shows the write-in timing chart of the user data in case the identification number is not falsified in the 4th Example of this invention. It is a figure which shows the write-in timing chart of the user data in case the identification number is tampered in the 4th Example of this invention. It is a figure which shows the internal structure of the flash memory card in the 4th Example of this invention. It is a figure which shows the structure of the cell array group in the 1st Example of this invention. It is a figure which shows the detail of a cell array and its periphery in 1st Example of this invention. FIG. 3 is a diagram showing a word line selection circuit in an erase prohibition area in the first embodiment of the present invention. FIG. 3 is a diagram showing a selection circuit corresponding to one word line in the word line selection circuit in the erasable region in the first embodiment of the present invention. It is a figure which shows the internal structure of the flash memory card in the 2nd Example of this invention.

Explanation of symbols

201 AND type flash memory chip 202 cell array group 203 row decoder 211 control circuit 212 status register 907 inversion / collation circuit

Claims (7)

A storage area composed of a plurality of erasing unit areas, and having a normal data area for each erasing unit area and a management information area for storing management information of the entire erasing unit area;
A selection device for selecting a word line, a data line or a source line according to an address value inputted from the outside and applying a predetermined voltage;
An operation control device for controlling operations such as erasing, writing, and reading;
In a nonvolatile semiconductor memory device having a temporary storage device that stores the state of the nonvolatile semiconductor memory device,
A device that generates data having a one-to-one mapping relationship with each bit of normal data, and the normal data and the write data in the same write unit area with respect to a part or all of the storage area A non-volatile semiconductor memory device, wherein mapping-related data is written. The nonvolatile semiconductor memory device according to claim 1,
Nonvolatile semiconductor memory device characterized in that the data having a one-to-one mapping relationship with each bit of the normal data is 1's complement data of the normal data, that is, inverted data related to '0' / '1' . The nonvolatile semiconductor memory device according to claim 1,
The non-volatile semiconductor memory device, wherein the normal data is an identification number unique to the non-volatile semiconductor memory device. The nonvolatile semiconductor memory device according to claim 1,
When writing to and reading from the data area other than the area for storing the normal data and the mapping data, the normal data and the mapping data are verified in advance and mapped to each other. A non-volatile semiconductor memory device comprising means for setting writing and reading to be possible when in a relationship, and setting to make writing and reading to the data area impossible when not in a mapping relationship with each other. The nonvolatile semiconductor memory device according to claim 4,
A non-volatile semiconductor memory device comprising means for informing the outside of the device that writing and reading are impossible when the normal data and the mapping data are not mapped to each other. The nonvolatile semiconductor memory device according to claim 5,
The non-volatile semiconductor memory device, wherein the means for notifying the outside of the non-volatile semiconductor memory device that writing and reading are impossible is the temporary memory device. The nonvolatile semiconductor memory device according to claim 5,
The non-volatile semiconductor memory device, wherein the means for informing the outside of the non-volatile semiconductor memory device that writing and reading are impossible is a signal value output from one or a plurality of dedicated output pins.

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